JPH10161602A - Liquid crystal display - Google Patents

Abstract

(57) Abstract: Provided is a liquid crystal display device in which power consumption is reduced by reducing the load capacitance and the amplitude of a driving voltage. SOLUTION: When a horizontal clock Hc is sequentially taken into a horizontal shift register section 2, a write voltage selection section 4 outputs upper three bits "b3, b4, b5" of 6-bit digital data D at the timing of the horizontal clock Hc. And the lower three bits "b0, b1, b2"
Respectively. Then, in the selector 40, the first bit corresponding to the size of the upper three bits “b3, b4, b5”
And a second reference voltage one level higher than the reference voltage are selected, and the voltage dividing circuit 41 divides the level between the first and second reference voltages into eight levels. Then, the selector 42 selects a voltage of a level corresponding to the magnitude of the lower three bits from among the divided voltages, and writes the selected voltage to each pixel 14 of the liquid crystal panel unit 1 as a pixel write voltage. It is.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display for driving a liquid crystal panel using digital data corresponding to an image signal.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a conventional liquid crystal display device. This liquid crystal display device includes a driver 101
Supplies analog driving voltages R ′, G ′, B ′ corresponding to the image signals R, G, B from the decoder 100 to the liquid crystal panel 10.
2 Specifically, as shown in FIG. 11, a horizontal line is vertically scanned by a vertical shift register 103 of the liquid crystal panel 102. And the horizontal shift register 1
04 opens the H switch 105 at the timing of the horizontal clock, and writes the driving voltages R ′, G ′, and B ′ to the pixels on the horizontal line scanned by the vertical shift register 103.

[0003]

However, the above-mentioned conventional liquid crystal display device has the following problems. As shown in FIG. 11, the liquid crystal panel 102 includes H switches 105, signal lines 106, and pixel transistors 107 in a number corresponding to the number of pixels on the horizontal line.
, B ′ are directly input to such a liquid crystal panel 102, so that the load capacitance seen from the input terminals of the drive voltages R ′, G ′, B ′ may be 100 pF or more. . In addition, as shown in FIG.
′, G ′, and B ′ have a very large amplitude, for example, 9 volts with respect to the counter electrode voltage Vcom of the liquid crystal, and each of the driving voltages R ′, G ′, and B ′ having the large amplitude is one. Must be applied to the signal line 106 for a short time of several tens to several hundreds of ns. That is, in the conventional liquid crystal display device, it is necessary to apply the driving voltages R ', G', and B 'having a large amplitude to the liquid crystal panel 102 having a large load at a high speed. Power consumption becomes very large. For this reason, the conventional liquid crystal display device cannot be applied to a portable terminal or the like that requires low power consumption. In addition, since the power consumption of the driver is large, a plastic package cannot be used for the IC part. Therefore, a high-cost package such as a ceramic package must be used, which increases the product cost.

By the way, the analog driving voltages R ', G
Consider a technology for reducing power consumption by converting ', B' into digital data, selecting a reference voltage having a level corresponding to the size of the digital data, and applying the reference voltage to the liquid crystal panel. Can be. However, in the case of this technique, it is necessary to prepare various types of reference voltages corresponding to the size of the digital data, and the structure for the reference voltage becomes complicated. For example, even when the digital data is only 6-bit data, 64 levels of reference voltages must be prepared, so that connection between these reference voltages and the liquid crystal panel is complicated, and
The wiring space in the liquid crystal panel becomes enormous, which is not practical.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a liquid crystal display device in which power consumption is reduced by reducing the load capacitance and the amplitude of a driving voltage. I have.

[0006]

In order to solve the above-mentioned problems, a liquid crystal display device according to the present invention comprises: a liquid crystal panel section in which a pixel write voltage is written to a plurality of pixels on a selected horizontal line; A horizontal shift register for sequentially taking in horizontal clocks in units of one horizontal period and writing the pixel write voltage to the pixels at the timing of the horizontal clock; and a higher-order bit of n-bit digital data at the timing of the horizontal clock. The m bits and the lower nm bits are separately held, and among the reference voltages of 2 m + 1 levels different from each other, a first reference voltage corresponding to the magnitude of the upper m bits and the first reference voltage After selecting the second reference voltage that is one level higher than the first reference voltage, the voltage between the first and second reference voltages is divided into 2 nm-level voltages, and among these divided voltages, The level of the voltage corresponding to the magnitude of the lower n-m bits has a configuration comprising a write voltage selector for selecting as the pixel writing voltage. With such a configuration, when the horizontal clock is sequentially taken into the horizontal register unit, the write voltage selection unit separately holds the upper m bits and the lower nm bits of the n-bit digital data at the timing of the horizontal clock. Then, the first reference voltage corresponding to the magnitude of the retained upper m bits and the second reference voltage one level higher are selected, and the level between these first and second reference voltages is 2−n−. The voltage is divided into m-th level voltages. Then, of these divided voltages, a voltage of a level corresponding to the magnitude of the lower nm bits is selected, and the selected voltage is written to each pixel of the liquid crystal panel as a pixel write voltage.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention. This liquid crystal display device includes a liquid crystal panel section 1, a horizontal shift register section 2, and a write voltage selection section 4.

The liquid crystal panel unit 1 includes a plurality of H switches 10
A plurality of signal lines 11 extending vertically from the output end of the pixel and a plurality of gate lines 13 extending horizontally from the vertical shift register section 12 are crossed in a non-contact manner.
Is formed. The pixel 14 has a liquid crystal 16
, A storage capacitor 17 connected in parallel to the liquid crystal 16, and a thin film transistor (TF
T) 15. Each liquid crystal 16 is held between a pixel electrode and a counter electrode. The pixel electrode is TFT1
5 and a predetermined voltage Vcom is applied to the opposite electrode.
Is applied. Thereby, the vertical clock Vc having one vertical period between the vertical start pulses Vs.
At this timing, the plurality of gate lines 13 are sequentially scanned from top to bottom, and a constant voltage is applied to the gate of the TFT 15 of the plurality of pixels 14 on each gate line 13.

Further, the horizontal shift register section 2 is provided with a horizontal clock H having one horizontal period between horizontal start pulses Hs.
c is sequentially taken in. The write voltage selection unit 4 captures the 6-bit digital data D at the timing of the horizontal clock Hc, and outputs a pixel write voltage corresponding to the 6-bit digital data D to the pixels 14 on the horizontal line of the liquid crystal panel unit 1.
This is the part to be written. Specifically, the first latch 30
, A second latch 31, a first selector 40, a voltage dividing circuit 41, and a second selector 42. The 6-bit digital data D is a signal obtained by digitizing the driving voltages R, G, and B output from the decoder shown in FIG. 10 by an analog / digital converter (not shown). .About.b5 are taken in parallel by the write voltage selection section 4 at the timing of the horizontal clock Hc.

The latch 30 is a section for holding the upper three bits "b3, b4, b5" of the 6-bit digital data D, and the latch 31 is provided for the lower three bits "b0,
b1 and b2 ”.

The selector 40 is a circuit for selecting the first and second reference voltages corresponding to the upper three bits "b3, b4, b5" output from the latch 30. Specifically, as shown in FIG. 2, the selector 40 sets the upper three bits “b3,
b4, b5 ", the reference voltages V0 to V8 (V0 <V1 <
.., <V8) are input to the selector 40, and the input terminals 40c of these reference voltages are connected to the selector 40.
Is drawn into. Also, the upper 3 bits “b3, b
Since the size of "4, b5" is eight levels, the lowest level to the highest level are sequentially associated with the reference voltages V0 to V7. The movable contact 40a is connected to the input terminal 40c of the reference voltage corresponding to the magnitude of the upper three bits "b3, b4, b5", and the movable contact 40b is connected to the reference voltage one level higher than the selected reference voltage. To the input terminal 40c of the voltage dividing circuit 4
1 is output. That is, for example, when the upper 3 bits are “0, 0, 0”, the movable contact 40
a, 40b respectively select the reference voltages V0, V1 as the first and second reference voltages, and when the upper 3 bits are "0, 1, 0", the movable contacts 40a, 40b are connected to the reference voltages V2, V3.
Is selected.

The voltage dividing circuit 41 is a circuit for dividing the voltage between the first and second reference voltages selected by the selector 40. Specifically, eight resistors 41a are connected between the output terminals of the movable contacts 40a and 40b, and the area between the first and second reference voltages is divided into eight levels of pixel write voltages V0 'to V7'. , To the selector 42 side.

The selector 42 is provided with the pixel write voltage V0 '.
To V7 ', the lower three bits "b0, b1, b" of the 6-bit digital data D fetched from the latch 31.
This is a circuit for selecting a pixel write voltage corresponding to “2”. Specifically, since the size of the lower three bits "b0, b1, b2" is eight levels, the lowest level to the highest level are sequentially associated with the pixel write voltages V0 'to V7'. . The movable contact 42a is connected to the lower three bits "b0,
b1, b2 ", and connects the pixel write voltage to the H switch 1 of the liquid crystal panel unit 1.
0 is output. That is, for example, when the lower three bits are “0, 0, 0”, the movable contact 42
a selects the pixel writing voltage V0 ', and when the lower three bits are "0, 1, 1", the movable contact 42a selects the pixel writing voltage V3'. The H switch 10 connected to such a selector 42 is opened at the timing of the horizontal clock Hc taken into the horizontal shift register 2.

Here, reference numeral 6 shown in FIG. 1 denotes an inverting circuit, which is interposed between the output terminals of the reference voltages V0 to V8 and the selector 40 of the write voltage selector 4. That is, the driving voltages R ′, G ′, and B ′ output from the driver correspond to those in FIG.
As shown in (1), the inversion is performed every one horizontal period based on the common electrode voltage Vcom. Therefore, it is necessary to change the pixel write voltage from the selector 42 correspondingly.
Therefore, the inverting circuit 6 changes the reference voltages V0 to V8 to
The inversion is performed at the timing of the horizontal start pulse Hs with reference to the common electrode voltage Vcom of No. 6. In addition,
For ease of understanding, the inversion circuit 6 is described as if it were inside the device shown in FIG. 1, but it is actually provided outside the device.

Next, the operation of the liquid crystal display of this embodiment will be described. In FIG. 1, a liquid crystal panel 1
A vertical start pulse V is supplied to the vertical shift register 12 of FIG.
When s is input, at the timing of the vertical clock Vc,
The pixel 14 on each gate line 13 is scanned, and a constant voltage is applied to the gate of the TFT 15 in the pixel 14 on the gate line 13 during the horizontal start pulse Hs, that is, during one horizontal period. That is, when the vertical clock Vc is input with the vertical start pulse Vs as a starting point, first, the uppermost gate line 13-1 is scanned, and the gate line 13-1 is scanned.
The above voltage is applied thereto, and the horizontal clock Hc is sequentially input to the horizontal shift register unit 2 starting from the first horizontal start pulse Hs. Then, 6-bit digital data D obtained by digitizing the driving voltages R, G, and B from the decoder is held in the latches 30 and 31 of the write voltage selection unit 4 at the timing of the horizontal clock Hc.
As described above, since the output signal from the decoder is digital data D, its amplitude is about 3 to 5 volts.
Very small. Also, the load seen from the decoder is only the latches 30 and 31, and the capacitance is smaller by one to two digits as compared with the conventional liquid crystal display device.

The first horizontal start pulse Hs
The inverting circuit 6 operates at the timing shown in FIG.
V8 is inverted with reference to the common electrode voltage Vcom. That is, assuming that the 6-bit digital data D corresponds to the waveform A shown in FIG. 12, the reference voltages V0 to V8 are inverted below the common electrode voltage Vcom.

The upper three bits "b3, b4, b5" and the lower three bits "b0, b" held in the latches 30 and 31, respectively.
1, b2 "are input to the selectors 40 and 42, respectively. For example, the upper three bits “b” held by the latch 30
Assuming that "3, b4, b5" is "0, 1, 0", the size of this bit corresponds to the reference voltage V2, and as shown in FIG.
The movable contact 40b is connected to the input terminal 40c of the reference voltage V3. As a result, the reference voltage V2 and V3 are divided into eight levels in the voltage dividing circuit 41, and the pixel writing voltages V0 '(= V2) to V7' can be output to the eight output terminals 42b. . In parallel with the above operation, the lower three bits “b0, b1, b2” held in the latch 31 are input to the selector. Assuming that the lower three bits "b0, b1, b2" are "0, 1, 1", the movable contact 42a of the selector 42 is connected to the output terminal 42b of the pixel writing voltage V4 ', and the pixel writing voltage V3 'is output from the selector 42. At this time, since the leftmost H switch 10 shown in FIG. 1 is opened by the first horizontal clock Hc, the pixel writing voltage V4 'is applied to the liquid crystal 1 through the leftmost TFT 15 of the gate line 13-1.
6 and the storage capacitor 17. Since then
Similarly, the upper three bits “b3, b4, b5” and the lower three bits “b0, b” of each subsequent 6-bit digital data D
1, b2 "are sequentially held in the latches 30 and 31 at the timing of the horizontal clock Hc, and the 6-bit digital data D
Is applied to each TF on the gate line 13-1.
The liquid crystal 16 and the storage capacitor 1 are sequentially applied through T15.
7 is written.

When the gate line 13 below the gate line 13-1 is scanned by the next vertical clock Vc, a horizontal start pulse Hs is input to the horizontal shift register 2. At this time, the 6-bit digital data D is
2 corresponds to the waveform B shown in FIG.
To V8 are inverted by the inverting circuit 6 above the common electrode voltage Vcom. Then, as in the case of scanning the gate line 13-1, the 6-bit digital data D for the next one horizontal period is sequentially held in the latches 30 and 31.
A pixel write voltage corresponding to the bit digital data D is sequentially written to the pixels 14 of the gate line 13. Hereinafter, the remaining gate line 1 is output at the timing of the vertical clock Vc.
3 are sequentially scanned, and the pixel writing operation for one field is completed.

As described above, according to the liquid crystal display device of this embodiment, the horizontal clock Hc corresponding to each pixel 14 is used.
Since the portion of the signal which operates at high speed is 6-bit digital data D, the amplitude is small, and the load on the 6-bit digital data D is limited to the latches 30 and 31 of the write voltage selection section 4 only. Load capacity is small. As a result, the power consumed for driving the liquid crystal panel unit 1 can be extremely reduced. Further, since the size of the 6-bit digital data D is of 64 weeks, 64 levels of reference voltages corresponding to these are required. In this embodiment, the write voltage selector 4 is composed of the selector 40, the voltage dividing circuit 41 and the selector 42 shown in FIG. Since the reference voltage can be obtained, the connection between the input lines of the reference voltages V0 to V8 and the selector 40 and the number of wirings can be reduced. As a result, in a liquid crystal display device in a narrow space,
Input lines for the reference voltages V0 to V8 can be actually wired.

(Second Embodiment) FIG. 3 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention. The liquid crystal display device of this embodiment differs from the first embodiment in that a plurality of write voltage selection units are provided to reduce the operation speed of the liquid crystal panel unit 1. In this liquid crystal display device, two write voltage selectors 4-1 and 4-2 are provided in parallel, and the second and third latches 32 are provided before the second write voltage selector 4-2. , 33 are connected. Then, these write voltage selection units 4-
H switch 10 in which the output terminals of 1,4-2 are connected in parallel
-1, 10-2. The horizontal clock Hc input stage of the horizontal shift register unit 2 has a horizontal clock Hc
A frequency dividing circuit 7 for dividing the frequency by half is provided. And
The latches 32 and 33 of the pre-stage latch unit 3 are operated by the horizontal clock Hc input from the frequency divider 7, and the write voltage selector 4-1 is operated by the frequency-divided horizontal clock Hb divided by the frequency divider 7. , And 4-2 of the latches 30 and 31 are operated.

Next, the operation of the liquid crystal display of this embodiment will be described. FIG. 4 is a time chart of each signal during operation. FIG. 4A shows the horizontal clock Hc, FIG. 4B shows the divided horizontal clock Hb, and FIG. FIG. 4D shows the 6-bit digital data D captured at the timing of the horizontal clock Hc. FIG. 4D shows the 6-bit digital data D held in the two write voltage selectors 4-1 and 4-2. The latches 32 and 33 of the preceding latch unit 3 operate at the timing of the horizontal clock Hc. Therefore, as shown in FIGS. 4A and 4C, the upper three bits "b3, b4, b5" and the lower three bits "b0, b" of the first 6-bit digital data D1.
"1, b2" is held in the latches 32, 33 at the timing of the horizontal clock Hc1. Then, the next horizontal clock H
c2, the upper 3 bits of the next 6-bit digital data D2
Bit “b3, b4, b5”, lower 3 bits “b0, b1,
b2 ”is held in the latches 32 and 33. At this time,
As shown in FIG. 4B, the frequency-divided horizontal clock Hb1 activates the latches 30 and 31 of the write voltage selection units 4-1 and 4-2.
Bit “b3, b4, b5”, lower 3 bits “b0, b1,
b2 ”is held in the latches 30 and 31 of the write voltage selection unit 4-1, and is held in the latches 32 and 33.
The upper three bits "b3, b" of the bit digital data D1
4, b5 "and the lower three bits" b0, b1, b2 "are also held in the latches 30, 31 of the write voltage selector 4-2. As a result, the two pixel write voltages corresponding to the 6-bit digital data D1 and D2 are changed to the write voltage selection units 4-1 and 4 respectively.
-2 are output simultaneously. At this time, the divided horizontal clock Hb1 is input to the horizontal shift register unit 2,
By keeping the switches 10-1 and 10-2 open at the same time, the pixel write voltage from the write voltage selectors 4-1 and 4-2 is applied via the H switches 10-1 and 10-2. The data is simultaneously written to the pixels 14-1 and 14-2 on the gate line 13.

As shown in FIG. 4A, when the latches 32 and 33 are activated by the horizontal clock Hc3, the 6-bit digital data D3 is latched.
Is held. At this time, as shown in FIG.
Since there is no frequency-divided horizontal clock Hb from the frequency divider 7, the latches 30 and 31 of the write voltage selectors 4-1 and 4-2 do not operate. As a result, as shown in FIG. 4D, the 6-bit digital data D1 and D2 are divided by the divided horizontal clock Hb.
It will be kept held until 2 is input. The same processing as the above 6-bit digital data D1, D2 is performed on the digital data after the 6-bit digital data D3, and "D3, D4", "D5, D6",... Are held at the period of the divided horizontal clock Hb. It will be scared. As described above, the liquid crystal display device according to the present embodiment operates at the cycle of the frequency-divided horizontal clock Hb, that is, at half the driving speed of the liquid crystal display device according to the first embodiment.
, The power consumption can be reduced accordingly. The other configuration, operation, and effect are the same as those of the first embodiment, and the description thereof is omitted.

The present invention is not limited to the above-described embodiment, and various modifications and changes can be made within the scope of the invention. For example, in the first embodiment,
Although the digital data input to the write voltage selection section 4 has a 6-bit configuration, it goes without saying that the number of bits is not limited. Further, the 6-bit digital data D is divided into upper 3 bits and lower 3 bits and held in the latches 30 and 31. However, the 6-bit digital data D is divided into upper 1 bits and lower 5 bits and held in the latches 30 and 31. You may do it. For example, when the 6-bit digital data D is divided into upper one bit and lower five bits, three levels of reference voltages V0 to V2 are input to the selector 40, and a voltage division is performed between the two reference voltages selected by the selector 40. The circuit 41 is divided into 32, and one of the voltages is selected by the selector 42.

Further, in the liquid crystal display device according to the second embodiment, two write voltage selectors 4-1 and 4-2 are provided so that pixel writing corresponding to two 6-bit digital data D is performed. The configuration is such that the voltage is written to two pixels 14 at the same time. However, the configuration is not limited to this, and a configuration in which three or more write voltage selection units 4 are provided and three or more pixels are simultaneously written may be employed. . That is, when the P write voltage selectors 4 are provided, the horizontal clock Hc
Is divided by 1 / P, and P−2 delay circuits are connected in series between the frequency dividing circuit 7 and the horizontal shift register unit 2.
Then, a Q-1 pre-stage latch unit 3 composed of latches 32 and 33 is connected in series in front of the Q (= 1 to P) -th write voltage selection unit 4, and the P-th write The first-stage latch unit 3 of the first stage of the voltage selection unit 4 is operated by the horizontal clock Hc, the first-stage latch unit 3 of the first stage of the (P-1) th write voltage selection unit 4 is operated by the divided horizontal clock Hb, and Are sequentially operated by the delay clock.

FIG. 5 is a schematic diagram showing a configuration example when four write voltage selectors are provided. Here, in order to facilitate understanding, the latches 30 and
31 is a latch unit 3-11, and the latches 32 and 33 and the latches 30 and 31 of the write voltage selection unit 4-2 are latch units 3-2.
1, 3-22, and latch 3 of write voltage selection section 4-3.
2, 33 and latches 30, 31 are connected to latch units 3-31,.
3-33, and the latches 32, 3 of the write voltage selection unit 4-4.
3 and latches 30 and 31 are connected to latch portions 3-41,.
4 will be described. In this example, since the four write voltage selectors 4-1 to 4-4 are provided, the frequency divider 7 divides the horizontal clock Hc into quarters. The output stage of the frequency divider 7 is connected in series with 4-2 delay circuits 70 and 71 for delaying the frequency-divided horizontal clock Hb by one clock, that is, two delay circuits. Further, the pre-stage latch section is not connected to the write voltage selection section 4-1, one latch section 3-21 is provided in the write voltage selection section 4-2, and one latch section 3-21 is provided in the write voltage selection section 4-3. The two latch units 3-31 and 3-32 are connected to the write voltage selection unit 4-4.
Are connected to three latch units 3-41 to 3-43. Then, the first-stage latch section 3-41 of the fourth write voltage selection section 4-4 is operated by the horizontal clock Hc, and the latch section 3-4 is operated.
-42 and the first-stage latch section 3-31 of the third write voltage selection section 4-3 are operated by the divided horizontal clock Hb, and the latch sections 3-21, 3-32 and 3-43 are delayed. It operates with the delayed clock Hd1 from the latch 70, and latches 3-11,
3-22, 3-33 and 3-44 are configured to operate with the delayed clock Hd2 from the delay circuit 71. FIG. 6 is a time chart of each signal in this example. FIG. 6A shows the horizontal clock Hc, FIG. 6B shows the divided horizontal clock Hb, and FIG. FIG. 6D shows the delay clock Hd1, and FIG. 6D shows the delay clock Hd2.
FIG. 6E shows the 6-bit digital data D captured at the timing of the horizontal clock Hc, and FIG. 6F shows the 6-bit digital data D held by the four write voltage selectors 4-1 to 4-4. This shows bit digital data D. According to the liquid crystal display device of this example, as shown in FIG. 6F, four digital data "D1, D2, D3, D4", "D5, D
6, D7, D8 "... At the timing of the delay clock Hd2, the latch units 3-1 of the write voltage selection units 4-1 to 4-4.
The driving speed of the liquid crystal panel unit 1 is reduced to 1/4.

FIG. 7 is a schematic diagram showing a modification of FIG.
In this example, delay circuits 70, 71, 7 for delaying the divided horizontal clock Hb by one clock are provided at the output stage of the frequency dividing circuit 7.
2 are connected in series. Further, the write voltage selection section 4-1
To 4-4, latch units 3-11, 3-21, 3-3
1, 3-41 are connected. Then, the write voltage selector 4-
4 is operated by the frequency-divided horizontal clock Hb from the frequency divider 7, the latch 3-31 of the write voltage selector 4-3 is operated by the delay clock Hd1 from the delay circuit 70, The latch section 3-21 of the write voltage selection section 4-2 is operated by the delay clock Hd2 from the delay circuit 71, and the latch sections 3-11, 3-22, 3-33, 3-44 are operated by the delay circuit 7
It is configured to operate with the delayed clock Hd3 from the second. FIG. 8 is a time chart of each signal in this example. As shown in FIG. 8, according to such a configuration, it is possible to obtain substantially the same effects as in the configuration example of FIG. 5 with a small number of latch units.

The level intervals of the reference voltages V0 to V8 in the first and second embodiments may be equal, and the reference voltages V0 to V8 may be adjusted to match the γ characteristics of the liquid crystal 16.
May be varied between levels. That is, the first
In the voltage dividing circuit 41 according to the second embodiment,
As shown in FIG. 2, the first and second reference voltages selected by the selector 40 are equally divided by the plurality of resistors 41a.
It is also possible to adopt a configuration in which the division level can be set freely. For example, as shown in FIG. 9, the voltage dividing circuit 8 can be configured. This voltage dividing circuit 8 includes a switch S
A division level circuit 80 that can equally divide the first and second reference voltages Vr and Vr + 1 input from the selector 40 via W1 and SW2, a division level circuit 81 that divides the voltage at different levels, and a selection circuit 82 Provided, switch SW
1 and SW2 and the switches SW3 and SW4 on the output side of the division level circuits 80 and 81 are switched by the selection circuit 82 in accordance with the size of the upper three bits "b3, b4, b5", thereby writing various pixels. Voltages V0 'to V7' can be obtained.

[0028]

As described in detail above, according to the liquid crystal display device of the present invention, since the n-bit digital data is used as the signal corresponding to the image signal, the amplitude can be reduced. Further, since the upper 3 bits and lower 3 bits of the n-bit digital data are held by the first and second latches of the write voltage selector, the load depends only on these latches, and the capacity is small. . As a result, there is an excellent effect that the driving power consumption of the liquid crystal panel can be reduced. Further, since the number of reference voltages corresponds to the number of upper bits of the n-bit digital data, there is an effect that the number of wirings from the reference voltage can be reduced. In addition, since a pixel write voltage can be written to a plurality of pixels at the same time, the driving frequency for the liquid crystal panel can be reduced, and power consumption can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a write voltage selection unit.

FIG. 3 is a block diagram showing an entire liquid crystal display device according to a second embodiment of the present invention.

4 is a time chart of each signal when the liquid crystal display device of FIG. 3 operates.

FIG. 5 is a block diagram showing a configuration example when four write voltage selection units are provided.

6 is a time chart of each signal when the liquid crystal display device of FIG. 5 operates.

FIG. 7 is a block diagram showing a modification of FIG. 5;

8 is a time chart of each signal when the liquid crystal display device of FIG. 7 operates.

FIG. 9 is a block diagram showing a modification of the voltage division circuit.

FIG. 10 is a block diagram showing a conventional liquid crystal display device.

FIG. 11 is a block diagram showing the liquid crystal panel of FIG.

FIG. 12 is a waveform chart showing an analog drive voltage.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel part, 2 ... Horizontal shift register part, 4 ... Writing voltage selection part, 14 ... Pixel,
Latch, 40, 42 Selector, 41: Voltage dividing circuit, D: 6-bit digital data, Hc: Horizontal clock Hc, V0
V8: Reference voltage.

Claims (6)

[Claims] 1. A liquid crystal panel section in which a pixel write voltage is written to a plurality of pixels on a selected horizontal line, and a horizontal clock sequentially taken in in units of one horizontal period, and the pixel write is performed at the timing of the horizontal clock. A horizontal shift register unit for writing a voltage to the pixel; and at the timing of the horizontal clock, the upper m bits and the lower nm bits of the n-bit digital data are separately held, and the 2 m + 1 level After selecting a first reference voltage corresponding to the magnitude of the upper m bits and a second reference voltage one level higher than the first reference voltage, the first and second reference voltages are selected from the different reference voltages. The level between the reference voltages is divided into voltages of 2 nm levels, and a voltage having a level corresponding to the magnitude of the lower nm bits among the divided voltages is used as the pixel write voltage. The liquid crystal display device characterized by comprising a write voltage selector selecting to, a. 2. The liquid crystal display device according to claim 1, wherein said write voltage selection unit comprises: a first latch holding said upper m bits; and a second latch holding said lower nm bits. A first selector for selecting the first and second reference voltages; and a voltage of 2 nm level between the levels of the first and second reference voltages selected by the first selector. A voltage dividing circuit, and among the divided voltages by the voltage dividing circuit, the lower n−
A second selector for selecting a voltage of a level corresponding to the size of m bits, and a liquid crystal display device. 3. The liquid crystal display device according to claim 2, wherein P (> 1) write voltage selectors are provided in parallel, and a divided horizontal clock obtained by dividing the horizontal clock by 1 / P is used. P-2 for providing a frequency dividing circuit for outputting, between the output stage of the frequency dividing circuit and the input stage of the horizontal shift register section, outputting a delayed horizontal clock sequentially delayed by one clock from the divided horizontal clock. Delay circuits are connected in series, and the third and fourth latches respectively connected to the first and second latches are provided before the Q (= 1 to P) th write voltage selector.
Of the P-th write voltage selection unit, the first-stage latch unit of the first stage of the P-th write voltage selection unit is operated by the horizontal clock, and the P-1 th write voltage By operating the first-stage pre-stage latch unit of the selection unit with the frequency-divided clock and sequentially operating the remaining pre-stage latch units with the delay clock, the pixel write voltages from the P write-voltage selection units can be adjusted as described above. A liquid crystal display device, wherein data is simultaneously written to P pixels on a horizontal line. 4. The liquid crystal display device according to claim 1, wherein the different reference voltages of the (2 m) +1 level are inverted every one horizontal period with reference to a common electrode voltage of a liquid crystal forming the pixel. A liquid crystal display device characterized by the above-mentioned. 5. The liquid crystal display device according to claim 2, wherein the different reference voltages of the (2 m +1) level are inverted with respect to a counter electrode voltage of a liquid crystal forming the pixel for each one horizontal period. A liquid crystal display device characterized by the above-mentioned. 6. The liquid crystal display device according to claim 3, wherein the different reference voltages of 2 m + 1 levels are inverted every one horizontal period with reference to a common electrode voltage of a liquid crystal forming the pixel. A liquid crystal display device characterized by the above-mentioned.