JPH10162514A5 - - Google Patents
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- JPH10162514A5 JPH10162514A5 JP1997037365A JP3736597A JPH10162514A5 JP H10162514 A5 JPH10162514 A5 JP H10162514A5 JP 1997037365 A JP1997037365 A JP 1997037365A JP 3736597 A JP3736597 A JP 3736597A JP H10162514 A5 JPH10162514 A5 JP H10162514A5
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Description
【図面の簡単な説明】
【図１】本発明の符号復号装置の構成例を示すブロック図である。
【図２】図１の実施の形態における最小連続長に対する補正動作を説明するフローチャートである。
【図３】図１の実施の形態の動作を説明するタイミングチャートである。
【図４】図１の実施の形態の他の動作を説明するタイミングチャートである。
【図５】図１のメモリと違反長検出回路の構成例を示すブロック図である。
【図６】図１のメモリとパターン検出回路の構成例を示すブロック図である。
【図７】図１の補正位置検出回路と補正処理回路の構成例を示すブロック図である。
【図８】図７の構成例の動作を説明するタイミングチャートである。
【図９】図２のフローチャートの処理を説明する図である。
【図１０】図１の補正位置検出回路と補正処理回路の他の構成例を示すブロック図である。
【図１１】図１の補正位置検出回路のメモリの構成例を示すブロック図である。
【図１２】図１１の構成例の動作を説明するタイミングチャートである。
【図１３】図１の実施の形態における最大連続長に対する補正動作を説明するフローチャートである。
【図１４】図１３のフローチャートの処理を説明する図である。
【図１５】エッジデータを検出するコンパレータの動作を説明する図である。
【図１６】図１の実施の形態における逆ＮＲＺＩ変調時の最小連続長に対する補正動作を説明するフローチャートである。
【図１７】図１の違反長検出回路の他の構成例を示すブロック図である。
【図１８】図１のパターン検出回路の他の構成例を示すブロック図である。
【図１９】図１の補正位置検出回路と補正処理回路の他の構成例を示すブロック図である。
【図２０】図１の補正位置検出回路と補正処理回路のさらに他の構成例を示すブロック図である。
【図２１】図１６のフローチャートの処理を説明する図である。
【図２２】図１の実施の形態における逆ＮＲＺＩ変調時の最大連続長に対する補正動作を説明するフローチャートである。
【図２３】図２２のフローチャートの処理を説明する図である。
【図２４】従来の符号復号装置の構成例を示すブロック図である。[Brief explanation of the drawings]
FIG. 1 is a block diagram showing an example of the configuration of a coding/decoding device according to the present invention.
2 is a flowchart illustrating a correction operation for a minimum run length in the embodiment of FIG. 1;
3 is a timing chart illustrating the operation of the embodiment of FIG. 1;
4 is a timing chart illustrating another operation of the embodiment of FIG. 1;
5 is a block diagram showing an example of the configuration of the memory and the error length detection circuit shown in FIG. 1;
6 is a block diagram showing an example of the configuration of the memory and pattern detection circuit shown in FIG. 1;
7 is a block diagram showing an example of the configuration of a correction position detection circuit and a correction processing circuit shown in FIG. 1;
8 is a timing chart illustrating the operation of the configuration example of FIG. 7;
9 is a diagram illustrating the process of the flowchart of FIG. 2. FIG.
10 is a block diagram showing another example of the configuration of the correction position detection circuit and the correction processing circuit shown in FIG.
11 is a block diagram showing an example of the configuration of a memory of the correction position detection circuit of FIG. 1;
12 is a timing chart illustrating the operation of the configuration example of FIG. 11;
13 is a flowchart illustrating a correction operation for the maximum continuous length in the embodiment of FIG. 1;
14 is a diagram illustrating the process of the flowchart of FIG. 13.
15A and 15B are diagrams illustrating the operation of a comparator that detects edge data .
16 is a flowchart illustrating a correction operation for a minimum run length during inverse NRZI modulation in the embodiment of FIG. 1;
17 is a block diagram showing another example of the configuration of the error length detection circuit of FIG. 1;
18 is a block diagram showing another example of the configuration of the pattern detection circuit of FIG. 1;
19 is a block diagram showing another example of the configuration of the correction position detection circuit and the correction processing circuit shown in FIG. 1;
20 is a block diagram showing still another example of the configuration of the correction position detection circuit and the correction processing circuit in FIG. 1;
21 is a diagram illustrating the process of the flowchart of FIG. 16.
22 is a flowchart illustrating a correction operation for the maximum continuous length during inverse NRZI modulation in the embodiment of FIG. 1;
23 is a diagram illustrating the process of the flowchart of FIG. 22.
FIG. 24 is a block diagram showing an example of the configuration of a conventional encoding/decoding device.
Claims (20)
前記伝送符号の同一の前記シンボルの連続長が、前記規定に違反している違反長の長さであることを検出する違反長検出手段と、
前記違反長のシンボルにより構成される前記違反ビット列を含む前記伝送符号のビット列のパターンを検出するパターン検出手段と、
前記パターン検出手段の検出結果に対応して、前記違反ビット列を含む前記伝送符号の補正位置を指定する指定手段と、
前記違反長が前記規定長となるように、前記指定手段の指定する補正位置の前記伝送符号のビットを補正する補正手段と
を備えることを特徴とする符号復号装置。A coding/decoding device that decodes a transmission code transmitted via a predetermined transmission path, the transmission code being a code in which a consecutive length, which is a length of other symbols consecutively arranged between identical symbols in a code sequence composed of two symbols, is predefined as a predetermined specified length, comprising:
a violation length detection means for detecting that the length of successive identical symbols in the transmission code is a violation length that violates the rule;
a pattern detection means for detecting a pattern of a bit string of the transmission code including the violation bit string constituted by symbols of the violation length;
a designation means for designating a correction position of the transmission code including the violation bit sequence in response to the detection result of the pattern detection means;
a correction means for correcting a bit of the transmission code at a correction position designated by said designation means so that the violation length becomes the specified length.
ことを特徴とする請求項１に記載の符号復号装置。2. The encoding/decoding device according to claim 1, further comprising a comparison means for comparing the signal transmitted via the transmission path with at least one reference level and outputting the transmission code.
ことを特徴とする請求項１に記載の符号復号装置。2. The encoding/decoding device according to claim 1, wherein said pattern detection means detects at least one of a pattern of a bit string preceding the violation bit string and a pattern of a bit string following the violation bit string.
ことを特徴とする請求項４に記載の符号復号装置。5. The encoding/decoding device according to claim 4, wherein the pattern detection means detects, as the pattern, whether the consecutive length of the bit string before or after the illegal bit string is the specified length.
ことを特徴とする請求項５に記載の符号復号装置。6. The encoding/decoding device according to claim 5, wherein when the pattern detection means detects that the bit string preceding the violation bit string is composed of the same symbols of the specified length, the designation means designates a bit of the bit string following the violation bit string as the correction position.
ことを特徴とする請求項５に記載の符号復号装置。6. The encoding/decoding device according to claim 5, wherein when the pattern detection means detects that the bit string following the violation bit string is composed of the same symbol of the specified length, the designation means designates a bit of the bit string preceding the violation bit string as the correction position.
ことを特徴とする請求項４に記載の符号復号装置。5. The encoding/decoding device according to claim 4, further comprising a storage means for temporarily storing the correction position designated by said designation means until the correction position is designated by said designation means again.
ことを特徴とする請求項４に記載の符号復号装置。5. The encoding/decoding device according to claim 4, wherein when the error length is detected by the error length detection means and the pattern detection means detects that the pattern of the bit string before or after the error bit string is not a pattern that specifies a bit before or after the error bit string as a correction position, the designation means designates a current correction position corresponding to the correction position at the time of the previous detection of the error length.
ことを特徴とする請求項４に記載の符号復号装置。5. The encoding/decoding device according to claim 4, wherein when the error length is detected by the error length detection means and the pattern detection means detects that the pattern of the bit string before or after the error bit string is not a pattern that specifies a bit after or before the error bit string as the correction position, the designation means designates a bit before or after the error bit string, whichever is designated in advance, as the correction position.
ことを特徴とする請求項１に記載の符号復号装置。2. The encoding/decoding device according to claim 1, wherein said correction means performs said correction by inverting the logic level of said bit at said correction position designated by said designation means.
前記規定長は、前記符号系列の”１”と”１”の間に連続して配置される”０”の最小連続長がｄである符号をＮＲＺＩ変調した後の、同一のシンボルの最小連続長ｄ’（＝ｄ＋１（ｄ≧１））であり、
前記違反長検出手段は、チャネルビットのビット列の同一のシンボルの連続長が（ｄ’−１）である連続長を前記違反長として検出し、
前記補正手段は、前記違反ビット列を含むビット列を、前記同一のシンボルの連続長がｄ’となるように補正する
ことを特徴とする請求項１に記載の符号復号装置。The symbols are "1" and "0",
the specified length is the minimum consecutive length d' (=d+1 (d≧1)) of the same symbol after NRZI modulation of a code in which the minimum consecutive length of "0"s placed consecutively between "1"s in the code sequence is d,
the error length detection means detects, as the error length, a consecutive length of identical symbols in a bit string of channel bits that is (d'-1);
2. The encoding/decoding device according to claim 1, wherein the correction means corrects the bit string including the illegal bit string so that the length of consecutive identical symbols becomes d'.
前記規定長は、前記符号系列の”１”と”１”の間に連続して配置される”０”の最大連続長がｋである符号をＮＲＺＩ変調した後の、同一のシンボルの最大連続長ｋ’（＝ｋ＋１）であり、
前記違反長検出手段は、チャネルビットのビット列の同一のシンボルの連続長が（ｋ’＋１）である連続長を前記違反長として検出し、
前記補正手段は、前記違反ビット列を含むビット列を、前記同一のシンボルの連続長がｋ’となるように補正する
ことを特徴とする請求項１に記載の符号復号装置。The symbols are "1" and "0",
the specified length is the maximum length k' (=k+1) of consecutive identical symbols after NRZI modulation of a code in which the maximum length of consecutive "0"s placed consecutively between "1"s in the code sequence is k,
the error length detection means detects, as the error length, a consecutive length of identical symbols in a bit string of channel bits that is (k'+1);
2. The encoding/decoding device according to claim 1, wherein the correction means corrects the bit string including the illegal bit string so that the length of consecutive identical symbols becomes k'.
前記規定長は、前記符号系列の”１”と”１”の間に連続して配置される”０”の最小連続長がｄである符号の、”０”の連続長ｄ（ｄ≧１）であり、
前記違反長検出手段は、エッジデータからなる前記伝送符号から、チャネルビットのビット列の同一のシンボルの連続長が（ｄ−１）である連続長を前記違反長として検出し、
前記補正手段は、前記違反ビット列を含むビット列を、前記同一のシンボルの連続長がｄとなるように補正する
ことを特徴とする請求項１に記載の符号復号装置。The symbols are "1" and "0",
the specified length is a length d (d≧1) of consecutive "0"s of a code in which the minimum length of consecutive "0"s placed between consecutive "1"s in the code sequence is d;
the error length detection means detects, from the transmission code consisting of edge data, a length of consecutive identical symbols in a bit string of channel bits that is (d-1) as the error length;
2. The encoding/decoding device according to claim 1, wherein the correction means corrects the bit string including the illegal bit string so that the length of consecutive identical symbols becomes d.
ことを特徴とする請求項１６に記載の符号復号装置。17. The encoding/decoding device according to claim 16, wherein the designation means designates at least one of the first bit of the error length and the bit immediately before it, or the last bit of the error length and the bit immediately after it as the correction position.
前記規定長は、前記符号系列の”１”と”１”の間に連続して配置される”０”の最大連続長がｋである符号の、”０”の連続長ｋであり、
前記違反長検出手段は、エッジデータからなる前記伝送符号から、チャネルビットのビット列の同一のシンボルの連続長が（ｋ＋１）である連続長を前記違反長として検出し、
前記補正手段は、前記違反ビット列を含むビット列を、前記同一のシンボルの連続長がｋとなるように補正する
ことを特徴とする請求項１に記載の符号復号装置。The symbols are "1" and "0",
the specified length is a length k of consecutive "0"s of a code in which the maximum length of consecutive "0"s placed between "1"s in the code sequence is k,
the error length detection means detects, from the transmission code consisting of edge data, a length of consecutive identical symbols in a bit string of channel bits that is (k+1) as the error length;
2. The encoding/decoding device according to claim 1, wherein the correction means corrects the bit string including the illegal bit string so that the length of consecutive identical symbols becomes k.
ことを特徴とする請求項１８に記載の符号復号装置。20. The encoding/decoding device according to claim 18, wherein the designation means designates at least one of the first bit of the error length and the bit immediately thereafter, or the last bit of the error length and the bit immediately before it as the correction position.
前記伝送符号の同一の前記シンボルの連続長が、前記規定に違反している違反長の長さであることを検出する違反長検出ステップと、
前記違反長のシンボルにより構成される前記違反ビット列を含む前記伝送符号のビット列のパターンを検出するパターン検出ステップと、
前記パターン検出ステップの検出結果に対応して、前記違反ビット列を含む前記伝送符号の補正位置を指定する指定ステップと、
前記違反長が前記規定長となるように、前記指定ステップの指定する補正位置の前記伝送符号のビットを補正する補正ステップと
を備えることを特徴とする符号復号方法。A coding and decoding method for decoding a transmission code transmitted via a predetermined transmission path, the transmission code being a code in which a consecutive length, which is a length of other symbols consecutively arranged between identical symbols in a code sequence composed of two symbols, is predefined as a predetermined specified length, comprising:
a violation length detection step of detecting that the length of succession of the same symbols in the transmission code is a violation length that violates the rule;
a pattern detection step of detecting a pattern of a bit string of the transmission code including the violation bit string constituted by symbols of the violation length;
a designation step of designating a correction position of the transmission code including the violation bit sequence in accordance with the detection result of the pattern detection step;
a correction step of correcting the bit of the transmission code at the correction position designated in the designation step so that the violation length becomes the specified length.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03736597A JP3882953B2 (en) | 1996-10-01 | 1997-02-21 | Code decoding apparatus and method |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8-260667 | 1996-10-01 | ||
| JP26066796 | 1996-10-01 | ||
| JP03736597A JP3882953B2 (en) | 1996-10-01 | 1997-02-21 | Code decoding apparatus and method |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH10162514A JPH10162514A (en) | 1998-06-19 |
| JPH10162514A5 true JPH10162514A5 (en) | 2004-11-04 |
| JP3882953B2 JP3882953B2 (en) | 2007-02-21 |
Family
ID=26376497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03736597A Expired - Fee Related JP3882953B2 (en) | 1996-10-01 | 1997-02-21 | Code decoding apparatus and method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3882953B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4193262B2 (en) * | 1999-01-19 | 2008-12-10 | ソニー株式会社 | Decoding device, data reproducing device, and decoding method |
| KR100532475B1 (en) * | 2003-10-16 | 2005-12-01 | 삼성전자주식회사 | A restore system and method for the optical discs |
-
1997
- 1997-02-21 JP JP03736597A patent/JP3882953B2/en not_active Expired - Fee Related
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