JPH10163111A - Epitaxial wafer - Google Patents

Abstract

(57) [Problem] To provide an epitaxial wafer capable of manufacturing a device having excellent characteristics. SOLUTION: The lifetime measured by the μ-PCD method is 300 μsec or more, the epitaxial wafer in which the occurrence of junction leak current is suppressed, and the Mo concentration in the epitaxial layer is 4 × 10 ¹⁰ cm ^−3. An epitaxial wafer in which the occurrence of junction leakage current is suppressed, and an epitaxial wafer in which Fe is detected by the DLTS method and Mo is not detected, wherein the lifetime is measured by the μ-PCD method. Is 100 μsec or more,
An epitaxial wafer that suppresses the occurrence of junction leakage current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an epitaxial wafer having a long lifetime measured by the .mu.-PCD method, and more particularly to an epitaxial wafer suitable for application to MOS devices.

[0002]

2. Description of the Related Art It is generally considered that a metal impurity existing in a Si wafer forms a deep level and becomes a recombination center. In particular, it is considered that the presence of metal impurities near the wafer surface affects device characteristics. For example, if a metal impurity is present in a depletion layer formed by applying a reverse bias at a PN junction, charges are exposed from the generation center, and as a result, a generation current is generated to lower the junction voltage. Therefore, it is important to reduce the level of metal impurities in the wafer, especially near the wafer surface.

[0003] Recently, an epitaxial wafer which has been used as a wafer for MOS devices has an epitaxial layer formed on a base wafer. Although the epitaxial wafer is relatively expensive, it can be improved in characteristics and simplified in design and process. Therefore, the importance of the epitaxial wafer has been recently recognized and is being applied.

[0004]

SUMMARY OF THE INVENTION
To manufacture a wafer, a substrate wafer, eg, C
An epitaxial layer having a thickness of less than 1 μm to about 100 μm is formed on the surface of the z wafer by controlling the type and concentration of impurities. At present, tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, or the like is used as a material for an epitaxial layer, and a substrate wafer is subjected to 1000-12
A vapor phase epitaxial growth method of obtaining an epitaxial wafer by heating to 00 ° C. is often used.

There are several specific examples of such methods. Initially, a resistance heating method was used in which heating was performed by energizing the susceptor that supports the wafers.However, in order to increase the number of wafers processed at one time and to make the heat distribution uniform at that time, heating by high frequency was performed. Has been taken. At present, a method of heating by combining heating with infrared rays is employed.

On the other hand, various devices for performing epitaxial growth by such heating have been proposed and put into practical use. Specifically, there are a horizontal furnace, a disk type (vertical type) furnace, a cylinder type (barrel type) furnace, and others.

However, using any method or apparatus,
The characteristics of the obtained epitaxial wafer are limited, and it has been difficult to suppress the generation of minute leakage current to a certain degree or less when the device is used as a device. As a result of the investigation, this is because the epitaxial layer is formed at a high temperature in order to manufacture an epitaxial wafer, and when the epitaxial layer is deposited, the epitaxial wafer is contaminated by the metallic impurity if present in the apparatus. I understand. These metal contamination sources include, in addition to silicon crystals and silicon-containing compounds used as raw materials, reaction vessels such as quartz bell jars and quartz cylinders, metal impurities adhered during cleaning or drying, and metals contained in the materials constituting the reaction vessel. Impurities and stainless components commonly used in piping systems of equipment can be considered.

[0008]

SUMMARY OF THE INVENTION Conventionally, epitaxial
The relationship between the metal impurity in the wafer or the minute leakage current caused by the impurity and the lifetime by the μ-PCD method has not been clarified. -It was found that the micro leak current was small in the wafer.

That is, the epitaxial wafer having a specific lifetime according to the present invention eliminates a factor of metal contamination at the time of manufacturing a wafer and eliminates metal impurities in the wafer, specifically, Mo, Fe, Ni, and the like. Cu, especially M
can be obtained by reducing the content of o.
Specifically, this is achieved by the following means or a combination thereof. (1) Purify the raw materials to be used, (2) Reduce the amount of impurities contained in the materials constituting the manufacturing apparatus to be used,
(3) purifying a cleaning agent for cleaning the manufacturing apparatus;
(4) coating the exposed portion of the manufacturing apparatus with a material having a low impurity content; (5) reducing the metal impurity content of the manufacturing atmosphere itself; (6) and other methods that do not impair the effects of the present invention.

In the epitaxial wafer of the present invention,
The metal diffuses or precipitates in the crystal due to heat treatment or the like and is unevenly distributed. The metal impurities in the wafer are measured by various methods. For analysis of metal impurities on the wafer surface, ICP (Inductively Coupled Plasma) -MA
SS method, AA (Atomic Absorption) method, or IC (Ion
Chromatography) method is used. In addition, DLTS (Deep Level Transi
ent Spectroscopy) or SPV (SurfacePhoto Vo)
ltage) method. These methods are described in various books, for example, "Advanced Electronics Series I-5 Silicon-Crystal Growth and Wafer Processing" by Takao Abe (Baifukan).

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

EXAMPLE 1 An example of impurity measurement of a typical epitaxial wafer by DLTS is as shown in FIGS. FIG.
Shows the measurement results of impurities in the epitaxial layer of the P-type wafer, where an Fe-B peak is observed at a position of 57K and a Mo peak is observed at a position of 190K. FIG.
Shows the measurement results of impurities in the epitaxial layer of the N-type wafer in the same manner, and Mo peaks are observed at 160K and 190K. Although these two peaks have not been determined to be due to Mo, HAMAGUCHI
From these reports (JJAP 30 (1991) L1837) and the diffusion behavior described below, it was estimated to be due to Mo.

Similarly, DLTS measurements were performed on various types of epitaxial wafers, and the results obtained are summarized from the viewpoint of the presence or absence of a peak as shown in FIG.
For P-type wafers, (A) Fe and Mo, (A) Mo
Only, (c) only Fe, and (d) no peak is observed, and there are four cases. On the other hand, for an N-type wafer, Fe
Are not observed, (e) Mo alone, (f) no peak is observed, and (e) has two peaks at (e) -1 160K and 190K. Observed, (e) -2 peak observed only at 160K, and (e) -31
Peak is observed only at the 90K position. The reason why there are three types of appearance of Mo peaks is unknown at present.

Next, the depth distribution of Fe and Mo was measured.
As a method of measuring the depth distribution, etching is performed to an arbitrary depth from the surface of the epitaxial wafer to the epitaxial layer or the substrate wafer with an HF + HNO ₃ solution,
A Schottky electrode was formed on the surface, and DLTS measurement was performed. As a wafer to be measured, a cylindrical furnace having a quartz bell jar is used, and an epitaxial wafer in which a Si epitaxial layer is grown on a Cz wafer, in which the depth distribution is easily measured and the thickness of the epitaxial layer is 30 μm. In order to measure the impurity concentration with high sensitivity, a P / P or N / N structure was selected.
The etching depth is 5, 10, 15, 20, 25, 3
0, 32, 37, and 42 μm.

The results obtained are as shown in FIGS. From this result, as shown below, it was found that each impurity element had a characteristic depth distribution. FIG.
It shows the depth distribution of e, and it can be seen that the concentration decreases due to outward diffusion toward the surface, but it diffuses almost uniformly to the substrate inside. On the other hand, FIG. 5 shows a depth distribution of Mo, in which Mo has the highest concentration at the interface between the epitaxial layer and the substrate and shows a distribution in which the concentration decreases toward the surface.
However, unlike Fe, Mo is present only in the epitaxial layer and hardly distributed in the substrate.

The difference in the depth distribution due to such elements is as follows.
This can be explained from the ease of diffusion of each element. FIG. 6 is for explanation. FIGS. 6A to 6E respectively show the behavior of impurities and the depth distribution during the wafer growth process.

First, in the case of Fe, when the temperature reaches the surface of the substrate wafer, the temperature of the epitaxial layer becomes high (for example, 110 ° C.).
(0 ° C. or higher), so that it diffuses into the substrate wafer. Even if the growth of the epitaxial layer proceeds as shown in (b) and (c), since the supply of Fe from the outside and the diffusion in the inside always occur, the concentration distribution of Fe is considered to be almost constant in the wafer. . Further, in the process (d) in which the temperature is lowered after the epitaxial layer growth is completed, the amount of outward diffusion of Fe from the epitaxial layer becomes larger than the supply of Fe from the outside, and a profile in which the distribution of Fe is small near the surface is low. It is formed.

On the other hand, Mo is known to be hardly diffused into the substrate, and as shown in FIG. 6B or 6C, the Mo distribution in the substrate becomes extremely small. ing.

Such a result is characteristic of an epitaxial wafer and is understood to be a general result that does not depend on the thickness of the epitaxial layer. Therefore, it is considered that the present invention is applicable to everything from an epitaxial wafer having an epitaxial layer thickness of 2 to 3 μm to an epitaxial wafer having an epitaxial layer thickness of 6 to 10 μm or 25 μm or more.

On the other hand, it is possible to estimate how impurities are introduced from the Mo profile that is difficult to diffuse. As shown in FIG. 5, the Mo depth distribution is highest at the start of epitaxial layer growth, and gradually decreases toward the surface. From now on, it is assumed that the amount of impurities in the atmosphere will be reduced by covering the inner surface of the reaction device considered to be a Mo contamination source, for example, a quartz bell jar, and the exposed portion of the susceptor pipe with the Si wall deposit. Presumed.

As described above, since the diffusion behavior of the metal impurities introduced into the epitaxial wafer is very different depending on the element, the gettering behavior is completely different. Since Fe is easily diffused, getter sites (P ⁺ substrate for P / P ⁺ wafer, IG layer when substrate is IG substrate, poly Si film for substrate with backside poly-Si, or phosphorus diffusion treatment Although gettering is possible to easily reach the (phosphorus diffusion layer), Mo is hardly diffused and is not gettered. Therefore, it is particularly important to prevent Mo from being introduced into the epitaxial layer when producing a high-quality epitaxial wafer. Although an epitaxial wafer having a P / P or N / N structure is used in this embodiment as described above, a substrate having a gettering effect (P ⁺ substrate, IG substrate, or substrate with backside poly-Si) is used as the substrate. Is used, the same applies to the depth distribution of Mo. Although Fe may be gettered, it is re-emitted during the high temperature treatment of the process, and the surface concentration increases to the same level as the inside, as shown in FIG. Therefore, the device may be adversely affected, so that it is necessary to prevent Fe from being introduced.

From the above, the effect of Mo, which seems to have the greatest effect on the wafer, on the device was examined. In FIG. 3, for the wafers of (a), (d), (e), and (f) in which only Mo was observed or in which nothing was observed, the lifetime measured by the μ-PCD method and the Mo measured by the DLTS The relationship with concentration was investigated. The obtained result is as shown in FIG. There is a negative correlation between Mo concentration and lifetime (indicated by a black diamond in Fig. 3) and a non-correlated part (indicated by a white diamond in Fig. 3) I understand.

Next, the effect of the epitaxial wafer having such an impurity distribution on the device was examined. (A), (D), shown in FIG.
Diodes were prepared using the wafers of (e) and (f), and the minute junction leak current having a reverse breakdown voltage was examined. D
FIG. 8 shows the relationship between the Mo concentration measured by the LTS and the minute leak current, and FIG. 9 shows the relationship between the lifetime and the minute leak current. From these results, it can be seen that in order to obtain a device having a small amount of small leak current, the lifetime of the wafer needs to be 300 μsec or more, preferably 400 μsec or more. Also, Mo
Focusing on a portion having a negative correlation between the concentration and the lifetime, it is understood that the concentration of Mo needs to be 4 × 10 ¹⁰ cm ⁻³ or less.

Example 2 In FIG. 7, the portion where there is no correlation between the Mo concentration and the lifetime is because Mo is not observed in DLTS.
It was thought that the material contained DLTS-inactive impurities that reduced the lifetime other than o. Therefore, these samples were dissolved in a mixed solution of HF and HNO3, and the obtained solution was concentrated and analyzed by ICP-MASS. The obtained results are as shown in Table 1, and it was found that Ni and Cu were contained.

Table 1 Sample 1 Sample 2 Sample 3 Sample 4 Ni 1.4 × 10 ¹² 9.0 × 10 ¹¹ 1.0 × 10 ¹² <DL Cu 5.4 × 10 ¹¹ 6.6 × 10 ¹¹ <DL 4.0 × 10 ¹¹ (DL: measurement limit Ni: 5.0 × 10 ¹¹ Cu: 2.0 × 10 ¹¹ ) From this result, in order to obtain a device with a small amount of small leak current, the Ni concentration is 9 × 10 ¹¹ cm ⁻³ or less, preferably 5 × 10 ¹¹ cm ⁻³ or less. Cu concentration of 4 × 10 ¹¹ cm ^-3
Or less, preferably 2 × 10 ¹¹ cm ⁻³ or less.

Example 3 The wafer shown in FIG.
The effect of Fe, which is an impurity, on the minute leak current was examined using a wafer in which only the peak was observed. As can be seen from FIG. 4, the distribution concentration of Fe differs by about one digit between the surface and the inside. Therefore, for each wafer, the Fe concentration in the as epi state was DLTS, and the Fe concentration inside was SPV.
(Surface Photo Voltage), and the relationship between them and the micro leak current was examined. The results obtained are shown in FIG.
0.

As described above, the Fe concentration is, for example, as low as 3 × 10 ¹⁰ cm ^{−3 on the} surface, but 2 × 10 ¹² c in the inside.
m ⁻³ , so that Fe
Is diffused from the inside to the low concentration surface layer, and the surface and the inside have the same concentration during the process (see FIG. 6E). Therefore, as shown in FIG. 10, in order to reduce the minute leak current, the Fe concentration is 1 × 10 ¹¹ cm on the surface in the as epi state.
It turns out that it is necessary to be ^-3 . Further, FIG.
FIG. 11 shows the relationship between the lifetime and the minute leak current by the μ-PCD method for each point of 0. From this, it can be seen that a lifetime of 100 μsec or more, and preferably 200 μsec or more, is required to obtain a device with a small amount of small leak current.

According to the present invention, in the epitaxial wafer in which the lifetime of the μ-PCD is within a predetermined range, or in the epitaxial wafer in which the content of metal impurities in an epitaxial layer is within a predetermined range, generation of a leak current is suppressed. Is what it is. Therefore, the characteristics of the device made using the epitaxial wafer of the present invention are extremely good.

[Brief description of the drawings]

FIG. 1 is a view showing an example of DLTS measurement data of a P-type epitaxial wafer containing Fe and Mo.

FIG. 2 is a diagram showing an example of DLTS measurement data of an N-type epitaxial wafer containing Mo.

FIG. 3 is a diagram schematically showing DLTS data of a P-type or N-type epitaxial wafer containing Fe and / or Mo.

FIG. 4 is a diagram showing a depth distribution of Fe concentration in an epitaxial wafer.

FIG. 5 is a diagram showing a depth distribution of Mo concentration in an epitaxial wafer.

FIG. 6 is a view schematically showing a state in which an epitaxial wafer is contaminated by Fe or Mo in a manufacturing process.

FIG. 7 is a view showing a relationship between Mo concentration in a wafer and lifetime.

FIG. 8 is a diagram showing a relationship between Mo concentration in a wafer and minute leak current.

FIG. 9 is a diagram showing a relationship between a minute leak current and a lifetime in a wafer containing Mo.

FIG. 10 is a graph showing the relationship between the Fe concentration in a wafer and a minute leakage current.

FIG. 11 is a diagram showing a relationship between a minute leak current and a lifetime in a wafer containing Fe.

Claims (6)

[Claims] 1. The life time measured by the μ-PCD method is 3
An epitaxial wafer wherein the occurrence of junction leakage current is suppressed, wherein the epitaxial wafer is at least 00 μsec. 2. An epitaxial layer having a Mo concentration of 4 × 10
^2. The epitaxial wafer according to claim 1, wherein the epitaxial wafer is ¹⁰ cm ^-3 or less. 3. The method according to claim 1, wherein the Ni concentration in the epitaxial layer is 9 × 10 ¹¹ cm ⁻³ or less, or the Cu concentration is 4 × 10 ¹¹ c.
3. The epitaxial wafer according to claim 2, which is not more than m- ³ . 4. The epitaxial wafer according to claim 2, wherein the Fe concentration in the epitaxial layer is 1 × 10 ¹¹ cm ⁻³ or less. 5. The epitaxial wafer according to claim 4, wherein the Ni concentration is 9 × 10 ¹¹ cm ⁻³ or less, or the Cu concentration is 4 × 10 ¹¹ cm ⁻³ or less. 6. The method according to claim 6, wherein Fe is detected by the DLTS method, and Mo is detected.
Is not detected on the epitaxial wafer, and μ
-An epitaxial wafer in which the occurrence of junction leakage current is suppressed, wherein the lifetime measured by the PCD method is 100 µsec or more.