JPH10164153A5 - - Google Patents
Info
- Publication number
- JPH10164153A5 JPH10164153A5 JP1996334514A JP33451496A JPH10164153A5 JP H10164153 A5 JPH10164153 A5 JP H10164153A5 JP 1996334514 A JP1996334514 A JP 1996334514A JP 33451496 A JP33451496 A JP 33451496A JP H10164153 A5 JPH10164153 A5 JP H10164153A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33451496A JP3729366B2 (ja) | 1996-11-29 | 1996-11-29 | パケットｆｓｋ受信機用クロック再生回路 |
| US08/878,973 US5999577A (en) | 1996-11-29 | 1997-06-19 | Clock reproducing circuit for packet FSK signal receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33451496A JP3729366B2 (ja) | 1996-11-29 | 1996-11-29 | パケットｆｓｋ受信機用クロック再生回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH10164153A JPH10164153A (ja) | 1998-06-19 |
| JPH10164153A5 true JPH10164153A5 (ja) | 2004-10-21 |
| JP3729366B2 JP3729366B2 (ja) | 2005-12-21 |
Family
ID=18278263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33451496A Expired - Fee Related JP3729366B2 (ja) | 1996-11-29 | 1996-11-29 | パケットｆｓｋ受信機用クロック再生回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5999577A (ja) |
| JP (1) | JP3729366B2 (ja) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11330916A (ja) * | 1998-05-14 | 1999-11-30 | General Res Of Electronics Inc | 掃引受信機 |
| JP2000349840A (ja) * | 1999-06-03 | 2000-12-15 | Matsushita Electric Ind Co Ltd | ベースバンド信号オフセット補正回路及び方法、この補正回路を備えたｆｓｋ受信装置 |
| US6614271B1 (en) * | 2002-06-13 | 2003-09-02 | Intel Corporation | Signal detect circuit for high speed data receivers |
| US7269233B2 (en) * | 2003-01-27 | 2007-09-11 | Novatek Microelectronics Corp. | Algorithm of bit synchronization for a digital FSK correlation receiver |
| US7529329B2 (en) * | 2004-08-10 | 2009-05-05 | Applied Micro Circuits Corporation | Circuit for adaptive sampling edge position control and a method therefor |
| US7453926B2 (en) * | 2005-06-01 | 2008-11-18 | Mediatek Incorporation | Bit synchronization detection methods and systems |
| JP4642563B2 (ja) * | 2005-06-29 | 2011-03-02 | パナソニック株式会社 | Ｆｓｋ受信装置 |
| JP6129549B2 (ja) * | 2012-12-26 | 2017-05-17 | 株式会社日立国際電気 | 送信機 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4696016A (en) * | 1986-10-02 | 1987-09-22 | Rockwell International Corporation | Digital clock recovery circuit for return to zero data |
| US5267267A (en) * | 1989-03-13 | 1993-11-30 | Hitachi, Ltd. | Timing extraction method and communication system |
| US5090024A (en) * | 1989-08-23 | 1992-02-18 | Intellon Corporation | Spread spectrum communications system for networks |
| US5175544A (en) * | 1990-04-27 | 1992-12-29 | Veda Systems Incorporated | Digitally controlled bit synchronizer |
| JP3347848B2 (ja) * | 1993-11-08 | 2002-11-20 | 株式会社ゼネラル リサーチ オブ エレクトロニックス | 多値信号復号回路 |
| US5539784A (en) * | 1994-09-30 | 1996-07-23 | At&T Corp. | Refined timing recovery circuit |
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1996
- 1996-11-29 JP JP33451496A patent/JP3729366B2/ja not_active Expired - Fee Related
-
1997
- 1997-06-19 US US08/878,973 patent/US5999577A/en not_active Expired - Fee Related