JPH10172927A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

(57) [PROBLEMS] To form a flat interlayer insulating film using a BPSG film containing a high concentration of boron and to form a plug in a part of a contact or a connection hole of a wiring,
Foreign substances such as moisture are prevented from reaching the inside of the chip through cracks generated at the interface between the BPSG film and another insulating film. SOLUTION: Further outside a guard ring GR formed along an outer peripheral portion of a main surface of a semiconductor chip 1, a bottom portion has at least an interlayer insulating film 23 and a BPSG film 2 thereunder.
A slit S that reaches a position deeper than the interface with 0 and has a width of 20 times or more the plug diameter is formed, and cracks generated at the interface between the BPSG film 20 containing high-concentration boron and the interlayer insulating film 23 are generated. Advancing along the interface to the inside of the chip is prevented by the slit S.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a BPSG (Boron-doped Phospho Silicate Glass) film as a part of an interlayer insulating film and a polycrystalline silicon or a polycrystalline silicon as a part of a wiring. The present invention relates to a technique which is effective when applied to a device using a plug using a metal such as tungsten.

[0002]

2. Description of the Related Art With the miniaturization and high integration of LSIs, wiring steps on semiconductor elements are increasing. For example, a recent DRAM (Dynamic Random Access Memory) adopts a stack capacitor structure in which an information storage capacitor is arranged above a memory cell selection MISFET.
A step is generated between the memory array and the peripheral circuit, which is substantially equivalent to the height of the information storage capacitor. Also, steps occur in the memory array area and the peripheral circuit area. If a wiring is formed on such a step, the exposure light may be defocused at the time of photolithography, or an etching residue may be left on the step, so that the wiring cannot be formed with high accuracy, and short-circuiting, disconnection, etc. Failure occurs. In addition, the increase in the level difference is accompanied by the miniaturization, and the aspect ratio of the contact hole and the connection hole of the wiring (hole depth / hole diameter).
, The coverage of the wiring is reduced, and the reliability such as migration resistance is reduced.

In order to solve the above problem, a technique for planarizing an interlayer insulating film that insulates a lower wiring from an upper wiring is indispensable. For the planarization of the interlayer insulating film, a BPSG film having a high reflow property or a spin-on-glass
A method using a (glass) film is widely used. The BPSG film contains boron (B) and phosphorus (P) each in a mole%.
After the film is formed by the CVD method, the surface is flattened by reflow with annealing.
When using a spin-on-glass film, the plasma C
A silicon oxide film is deposited by the VD method, and a spin-on glass film is deposited thereon by a spin coating method. Next, after the spin-on-glass film is baked to densify the film, the surface is flattened by etch back, and the plasma CV
A silicon oxide film is deposited by the method D to form a flat interlayer insulating film. Along with such flattening of the interlayer insulating film, plugs are formed in the contacts and connection holes in order to promote the flattening of the wiring in the contacts and connection holes having a high aspect ratio. Usually, a plug is formed by depositing a thin adhesive layer such as titanium nitride (TiN) by a sputtering method, and then forming a C
A tungsten (W) film is formed by the VD method, and the contacts and the connection holes are filled with W. Further, a plug is formed by etching back while leaving W in the contact and the connection hole. Thereafter, an aluminum (Al) wiring is formed by a sputtering method.

[0004]

In the LSI manufacturing process, a semiconductor wafer on which an LSI is formed is diced and divided into semiconductor chips, which are mounted one by one on a lead frame (pelleting) and wire-bonded. Thereafter, sealing with a mold resin is performed.
Since the dicing of the semiconductor wafer is performed mechanically using a diamond blade or the like, fine cracks are generated on the side walls of the semiconductor chip, from which moisture or foreign substances enter the chip and cause corrosion of wiring. May cause.

In order to prevent this, a guard ring is usually provided around the semiconductor chip. The guard ring is formed by embedding a wiring material (Al alloy or W) for a circuit in a groove formed along a peripheral portion of a semiconductor chip.
This wiring material blocks moisture or foreign matter that has entered from the side wall of the chip from entering the inside of the chip. However, when the BPSG film is used as a part of the interlayer insulating film, if the concentration of boron in the film is high, cracks generated at the end of the chip penetrate through the guard ring and reach the inside of the chip. As a result, moisture or the like penetrates into the inside of the chip through the cracks to cause wiring corrosion. this is,
Since the BPSG film containing boron has high hygroscopicity,
When an insulating film is deposited on the PSG film, the adhesiveness of the interface between these films is reduced, and a small crack generated at the end of the chip occurs because it grows along the interface.

In order to prevent this, there is a method in which a slit deeper than the interface between the BPSG film and the interlayer insulating film deposited thereon and below is formed in the periphery of the semiconductor chip. According to this method, cracks generated at the interface between the BPSG film and the upper and lower insulating films can be prevented from progressing along the interface into the chip by the slits. Wiring corrosion due to moisture entering from the wire can be reliably prevented.
However, when plugs are formed in the contact and connection holes of the wiring, these slits are also filled with the plugs, so that growth at the interface of minute cracks generated at the chip end cannot be prevented by the slits. It has been clarified by the study of the present inventor that moisture and the like enter the inside and cause wiring corrosion.

Further, even when a plug material is present in the slit portion, a method has been proposed in which only a plug material in the slit portion is selectively removed by using an appropriate chemical (JP-A-6-232256). However, the use of this method not only increases the number of steps but also limits the combination of materials that can be selectively etched by chemicals to tungsten and aluminum, so that it can be used in general-purpose processes such as highly integrated memories such as DRAMs. There is a problem that it is difficult to use.

An object of the present invention is to planarize an interlayer insulating film using a BPSG film containing a high concentration of boron, and to deposit a BPSG film and a device on the device in a device using plugs for wiring contacts and connection holes. It is an object of the present invention to provide a technique capable of effectively preventing a crack generated at the interface with the insulating film from reaching the inside of the chip.

Another object of the present invention is to provide a versatile technique capable of achieving the above object without increasing the number of device manufacturing steps.

[0010]

In the semiconductor integrated circuit device of the present invention, a part of an interlayer insulating film deposited on a semiconductor chip is constituted by a silicon oxide film containing boron, and is formed in a contact or a connection hole of a wiring. A plug is formed, and the slit is formed deeper than the interface between the boron-containing silicon oxide film and the interlayer insulating film deposited thereon or below and having a width larger than twice the diameter of the plug. This is provided along the periphery of the chip. When a slit having such a width is provided, when a plug is formed by etch-back, continuous embedding by a plug material is mainly prevented in the slit, so that a crack generated from an end portion of the chip is prevented from progressing inside. Can be prevented by slits. In addition, in the case of a structure in which a thin film of the plug forming material is deposited on the side wall of the slit, the effect of preventing the progress of the crack increases.

In the semiconductor integrated circuit device according to the present invention, the slit is provided outside a guard ring.

A semiconductor integrated circuit device according to the present invention is a DRAM including a memory cell having a stack structure in which an information storage capacitance element is disposed above a memory cell selection MISFET, and the boron-containing silicon oxide film is The plug constitutes a part of an interlayer insulating film in an upper layer of the memory cell, and the plug is used for filling a connection hole of a part of a wiring in an upper layer of the memory cell.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a DRAM according to an embodiment of the present invention.
FIG. 4 is a plan view showing the appearance of a semiconductor chip on which a semiconductor chip is formed. As shown in the figure, a large number of memory arrays MA are arranged on the main surface of the semiconductor chip 1 made of single crystal silicon along the X direction (long side direction of the semiconductor chip 1) and the Y direction (short side direction of the semiconductor chip 1). Are arranged in a matrix.

A sense amplifier array SA is arranged between memory arrays MA adjacent to each other along the X direction.
A word shunt portion WS is arranged between memory arrays MA adjacent to each other along the Y direction. At the center of the main surface of the semiconductor chip 1, control circuits such as a word line drive circuit and a data line selection circuit, input / output circuits, bonding pads, and the like are arranged (not shown). . Also,
An outer peripheral portion of the main surface of the semiconductor chip 1 is provided with a guard for protecting the circuit from moisture, contaminants or surrounding electric disturbance.
The dring GR is continuously arranged without a break so as to surround the above-described circuit.

A feature of the semiconductor chip 1 of the present embodiment is that a crack generated at an interface between a BPSG film described later and an insulating film thereon is prevented from reaching the inside of the chip. This is because a slit (groove) S having a width twice or more the diameter of a plug described later is provided at the outermost peripheral portion, that is, further outside the guard ring GR. The slits S are continuously arranged without a break so as to surround the guard ring GR.

Next, the configuration of the memory array MA and the configurations of the guard ring GR and the slit S formed on the outer peripheral portion of the chip will be described with reference to FIG. The left side of the figure is a cross-sectional view of the memory array MA, and the right side is a cross-sectional view of the outer peripheral portion of the chip.

A p-type well 2 is formed on a main surface of a semiconductor substrate 1 made of P- type single crystal silicon. The main surface of the non-active region of the p-type well 2 is provided with a field for element isolation.
A field oxide film 3 is formed, and a p-type channel stopper layer 4 is formed in a p-type well 2 including a lower portion of the field oxide film 3.

A memory cell of the DRAM is formed on a main surface of an active region of a p-type well 2 surrounded by a field oxide film 3. The memory cell includes an n-channel type MISFET Qt for memory cell selection and an information storage capacitive element C disposed on the MISFET Qt. The memory cell selecting MISFET Qt includes a gate oxide film 5, a gate electrode 6, and a pair of n + type semiconductor regions 7,
7 (source, drain region). Gate electrode 6 is formed integrally with word line WL. Gate electrode 6 and word line WL are formed of a first-layer polycrystalline silicon film. An n-type impurity (P or the like) is introduced into this polycrystalline silicon film in order to reduce its resistance value. The gate electrode 6 (word line WL)
WSix, MoSix, Ti on top of the polycrystalline silicon film
A polycide film formed by laminating a high-melting metal silicide film such as Six or TaSix or a polymetal film formed by laminating a high-melting metal film such as W or Mo may be used.

On the side wall of the gate electrode 6, a side wall spacer 8 of silicon oxide is formed. On the gate electrode 6, a silicon oxide film 9 is formed. Side wall spacer 8 and oxide silicon 9
A silicon oxide film 10 is formed on the upper surface of the substrate, and a silicon nitride film 12 is formed on the silicon oxide film 10.

Above the silicon nitride film 12, the storage electrode 11 of the information storage capacitor C is formed. The storage electrode 11 includes a first-layer fin 11a and a second-layer fin 11b formed thereon. N-type impurities are introduced into these polycrystalline silicon films constituting the fins 11a and 11b in order to reduce their resistance. The storage electrode 11 of the information storage capacitor C is connected to one semiconductor region 7 of the memory cell selection MISFET Qt through the silicon nitride film 12, the silicon oxide film 10, and the connection hole 13 formed in the silicon oxide film. I have.

Above the storage electrode 11, a plate electrode 15 of the information storage capacitor C is formed with a dielectric film 14 interposed therebetween. The dielectric film 14 is formed of an insulating film in which a silicon nitride film and a silicon oxide film are stacked. Play
The gate electrode 15 is formed of a fourth-layer polycrystalline silicon film. An n-type impurity is introduced into the polycrystalline silicon film in order to reduce its resistance.

A data line DL is formed above the information storage capacitor C of the memory cell via a BPSG film 17 and a silicon oxide film 27. On the silicon oxide film 27 on the outer periphery of the chip, a wiring 18 constituting a part of the guard ring GR is formed. The BPSG film 17 is composed of an information storage capacitor C and an upper data line D.
L and the memory cell selection MI.
It is provided to reduce a step in the memory array MA and a step in the peripheral circuit caused by disposing the information storage capacitive element C above the SFET Qt. This B
The PSG film 17 contains 10 mol% or more of boron in order to improve the reflow property.

The data line DL and the wiring 18 are formed on a polysilicon film by a tungsten silicide film (WSi).
x) It is composed of a polycide film in which films are stacked. Date
The data line DL is composed of the silicon oxide film 27 and the BPSG film 17.
Memory cell selecting MI through connection hole 19 opened in
It is electrically connected to one semiconductor region 7 of the SFET. The wiring 18 is formed of the silicon oxide film 27 and the BP
It is electrically connected to the semiconductor region 7 of the p-type well 2 through a connection hole 29 opened in the SG film 17.

On the upper layer of the data line DL, a Y select line YS is formed via a silicon oxide film 28 and a BPSG film 20. Further, the BPSG film 20 on the outer peripheral portion of the chip
Above, a wiring 21 forming a part of the guard ring GR is formed. The BPSG film 20 electrically separates the data line DL from the Y select line YS thereabove, and forms a memory array formed by arranging the data line DL above the information storage capacitor C. It is provided to reduce a step in the MA and a step in the peripheral circuit. As in the case of the BPSG film 17, the BPSG film 20 contains 10 mol% or more of boron in order to improve the reflow property.

The Y select line YS and the wiring 21 are formed of a tungsten (W) film. Wiring 21 is BP
It is connected to a lower wiring 18 through a connection hole 22 formed in the SG film 20 and the silicon oxide film 28. In a peripheral circuit region (not shown), a wiring made of a W film in the same layer as the Y select line YS and the wiring 21 is formed.

A shunt word line SWL is formed above the Y select line YS via an interlayer insulating film 23. In addition, on the interlayer insulating film 23 around the chip,
The wiring 24 forming a part of the dring GR is formed. The interlayer insulating film 23 is composed of a three-layer insulating film in which a silicon oxide film, a spin-on-glass film, and a silicon oxide film are stacked. The shunt word line SWL and the wiring 24 are formed of a three-layer conductive film in which a titanium tungsten (TiW) film or a titanium nitride (TiN) film, an Al film, and a TiW film or a TiN film are laminated.

The wiring 24 is connected to the lower wiring 21 through a connection hole 25 formed in the interlayer insulating film 23. That is, the garbage provided on the outer peripheral portion of the semiconductor chip 1
The drilling GR includes a connection hole 29 formed in the silicon oxide film 27 and the BPSG film 17, a connection hole 22 formed in the BPSG film 20 and the silicon oxide film 28, and a connection hole formed in the interlayer insulating film 23. And three layers of wirings 18, 21, and 24 connected to each other through the hole 25.
These wirings 18, 21, 24 shield moisture or the like entering from the side wall of the semiconductor chip 1 from entering the inside of the chip.

Shunt word line SWL and wiring 24
On the upper layer, a passivation film 26 for protecting the surface of the semiconductor chip 1 is formed. The passivation film 26 is a silicon oxide film 2 deposited by a plasma CVD method.
6a and a silicon nitride film 26b.

A deep slit S extending from the surface of the passivation film 26 to the BPSG film 17 is formed in the outermost peripheral portion of the semiconductor chip 1. The width of this slit is at least twice the diameter of the plug described above. For this reason, the inside of the slit is not continuously filled with the plug material. In order to make the plug material inside the slit discontinuous, it is possible in principle to have a slit width that is at least twice the film thickness of the plug material (thus, more than the diameter). Considering this, a slit width of twice or more is actually desirable. The bottom of the slit S needs to penetrate at least the interface between the interlayer insulating film 23 and the underlying BPSG film 20 containing high-concentration boron, and further penetrates the BPSG film 17 and the underlying insulating film. There is no problem even if it reaches the surface of the semiconductor substrate 1.

As described above, in the DRAM of the present embodiment, the bottom is formed at least outside the guard ring GR formed along the outer peripheral portion of the main surface of the semiconductor chip 1 and has at least the interlayer insulating film 23 and the lower layer. A slit S is formed to reach a position deeper than the interface with the BPSG film 20.

With this configuration, B containing a high concentration of boron
Even if a crack generated at the interface between the PSG film 20 and the interlayer insulating film 23 grows along the interface into the inside of the chip, the progress is stopped by the slit S, so that the gardening GR is cut by the crack. It will not be done. Therefore, moisture and contaminants that have entered from the outside through the cracks are blocked by the guard ring GR, and do not enter the inside of the chip any more.
Wiring corrosion caused by the crack is reliably prevented.

Next, an embodiment of a method for forming the slit S will be described with reference to FIGS.

First, a MISFET Qt for selecting a memory cell which constitutes a memory cell of a DRAM is formed on a semiconductor substrate 1, and a capacitor C for storing information is formed thereon. Then, as shown in FIG. A BPSG film 17 containing about 13 mol% of boron is deposited on the plate electrode 15 of the capacitive element C for use by CVD. BPSG film 17
Has a thickness of about 500 nm. Subsequently, at 850 ° C., 2
Anneal for about 0 minutes to reflow the BPSG film 17.
I do.

Next, as shown in FIG.
A silicon oxide film 27 is deposited thereon by a CVD method, and the silicon oxide film 27 and the BPSG film 17 are etched to form a connection hole 19 reaching one semiconductor region 7 of the memory cell selecting MISFET and a semiconductor region 7 on the outer peripheral portion of the chip. After forming the contact holes 29 which reach each other, the polycide film deposited by the CVD method on the silicon oxide film 27 is patterned to form the data lines DL and the wirings 18.

Next, as shown in FIG.
And silicon oxide films 28 and 13
A BPSG film 20 containing about mol% of boron is deposited by a CVD method. The thickness of the BPSG film 20 is about 400 nm. Subsequently, annealing is performed at 850 ° C. for about 20 to reflow the BPSG film 20.

Next, as shown in FIG.
After the silicon oxide film 28 is etched to form a connection hole 22 reaching the wiring 18, a TiN film is deposited on the BPSG film 20 by a sputtering method, and then a W film is patterned by a CVD method to select Y. YS and wiring 21 are formed. The surface of the BPSG film 20 containing boron at a high concentration is exposed to moisture and absorbed by the process of forming the connection holes 22 and the process of forming the Y select YS and the wiring 21 by patterning the W film. Therefore, when the interlayer insulating film 23 is deposited on the BPSG film 20, cracks are easily generated at the interface because the adhesive force at the interface between these films is very small.

Next, as shown in FIG.
A silicon oxide film, a spin-on-glass film, and a silicon oxide film are sequentially deposited on the S and the wiring 21 to form an interlayer insulating film 23. Then, the interlayer insulating film 23 is etched to form a connection hole 25 and a slit reaching the wiring 21. Sa is simultaneously formed. The diameter of the connection hole is 0.4 μm. The silicon oxide film is deposited by a plasma CVD method, and the spin-on-glass film is deposited by a spin coating method. In this case, the slit Sa
Has a diameter of 1 μm.

Next, as shown in FIG.
After a TiN film is deposited to a thickness of about 50 nm on the upper layer by a sputtering method, a W film is laminated to a thickness of 500 nm by a CVD method, and the W film is buried in the connection hole by an etch-back process to form a plug P. In the slit Sa, a TiN film and W
A laminated film with the film remains. Thereafter, 3 deposited by sputtering is used.
By patterning the conductive films (TiN film, Al film, TiN film) of the layers to form the shunt word line SWL and the wiring 24, the guard ring GR is completed.

Next, as shown in FIG.
A silicon oxide film 26a forming a part of the passivation film 26 is deposited on the drain line SWL and the wiring 24 by a plasma CVD method. Subsequently, the silicon oxide film 26a in a region not shown in the figure is etched to expose a part of the wiring (wiring of the peripheral circuit) in the same layer as the shunt word line SWL, and a pad for probe inspection is formed. To form At this time,
Silicon oxide film 26 buried inside slit Sa
Etching for removing a is simultaneously performed to newly form a slit Sb. The slit Sb is the slit Sa
Is formed at the same position as that of the slit Sa in consideration of misalignment of the photomask (diameter of 12 μm).
Formed. In this step, the laminated film of the TiN film and the W film deposited on the side wall of the slit Sa is partially etched, and the laminated film of the TiN film and the W film is removed on the side wall of the slit Sb. Next, after applying a probe to the probe inspection pad to perform a characteristic test of the circuit, a silicon oxide film 26a is deposited again on the silicon oxide film 26a, and the probe inspection pad is removed. Cover.

Next, as shown in FIG. 10, a silicon nitride film 26b constituting a part of the passivation film 26 is deposited on the silicon oxide film 26a by a plasma CVD method. The silicon nitride film 26b and the underlying silicon oxide film 26a are etched to form bonding pads for wire connection. At this time, the slit S is completed by simultaneously performing etching for removing the silicon oxide film 26a and the silicon nitride film 26b embedded in the slit Sb. Since the slit S is formed at the same position as the slit Sb, the slit S is formed in consideration of misalignment of the photomask.
It is formed with a diameter (about 14 μm) larger than b.

As described above, in the above method, the slit Sa is formed in the etching step for forming a part of the guard ring GR, and the slit Sb is formed in the etching step for forming the bonding pad. In the etching process for forming the pad, the slit S
Is formed, the slit S can be formed without increasing the number of manufacturing steps of the DRAM.

In FIG. 7 of the previous embodiment, the slit Sa
Was increased every 0.2 μm in the range of 0.4 μm to 2 μm, and the change in the defect rate was examined. If the diameter is smaller than twice the plug diameter (0.4, 0.6 μm width), as described later, the progress of cracks between the BPSG film and the upper interlayer insulating film cannot be sufficiently prevented, and the defect rate Was high,
In the case of twice or more, the defective rate was significantly reduced. FIG. 11 shows the relationship between the defect rate and the slit width. It is probable that the reason why the defective rate was reduced was that the progress of cracks was prevented by the slit because the plug material did not continuously remain inside the slit. From this examination result, it is understood that setting the slit width to twice or more the plug diameter is effective in preventing crack failure.

In the above embodiment, the case where the present invention is applied to a DRAM in which a data line is arranged above an information storage capacitor is described. However, the present invention is not limited to this. The present invention can also be applied to a DRAM in which a storage capacitor is arranged.

Further, the present invention is not applied only to a DRAM, but a BPSG film containing a high concentration of boron is used as a part of an interlayer insulating film and a plug is used as a part of a contact or a connection hole of a wiring. It can be applied to all devices such as SRAM, FRAM, logic, and the like.

[0046]

According to the present invention, even if a crack generated at the interface between the silicon oxide film containing high concentration boron and another interlayer insulating film grows along the interface into the inside of the chip, the slit is used. Since the progress is stopped, it is possible to reliably prevent the wiring corrosion caused by the crack.

Further, according to the present invention, an etching step for forming a guard ring and an etching step for forming a pad by opening a passivation film covering the surface of a semiconductor chip are utilized. By forming the slits, the slits can be formed without increasing the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a plan view showing the appearance of a semiconductor chip on which a DRAM according to one embodiment of the present invention is formed.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor chip showing a DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of a semiconductor chip showing a method of manufacturing a DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of a semiconductor chip showing a method of manufacturing a DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of a semiconductor chip showing a method of manufacturing a DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor chip showing the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor chip showing the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of a semiconductor chip showing a method of manufacturing a DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor chip showing the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of a semiconductor chip showing a method of manufacturing a DRAM according to one embodiment of the present invention;

FIG. 11 is a diagram showing a relationship between a slit width and a defect rate due to a crack in a DRAM manufacturing method according to one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate (chip) 2 p-type well 3 field oxide film 4 channel stopper layer 5 gate oxide film 6 gate electrode 7 semiconductor region (source, drain region) 8 side wall spacer 9 oxidation Silicon film 10 silicon oxide film 11 storage electrode 11a fin 11b fin 12 silicon nitride film 13 connection hole 14 dielectric film 15 plate electrode 17 BPSG film 18 wiring 19 connection hole 20 BPSG film 21 wiring 22 connection hole 23 interlayer insulating film 24 Wiring 25 Connection hole 26 Passivation film 26a Silicon oxide film 26b Silicon nitride film 27 Silicon oxide film 28 Silicon oxide film 29 Connection hole C Information storage capacitance element DL Data line GR Guard ring MA Memory array P Plug Qt Memory MISFET for cell selection S Slit (groove) SA Sense amplifier row SWL shunt word line T target pattern WL word line WS word shunt YS Y select line.

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Shinji Nishihara 5-2-1, Josuihoncho, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd.

Claims (11)

[Claims] A part of an interlayer insulating film deposited on a semiconductor chip is composed of a silicon oxide film containing high concentration of boron, and a contact hole between a wiring and a silicon substrate or a connection hole between a wiring and a wiring is formed. A semiconductor device having a plug made of a semiconductor material or a metal material at a portion thereof, wherein the plug has a depth smaller than an interface between the boron-containing silicon oxide film and an interlayer insulating film deposited thereover, and a minimum width of the plug. A semiconductor integrated circuit device, wherein a slit having a width of at least twice the diameter is provided along a peripheral portion of the semiconductor chip. 2. A semiconductor integrated circuit device according to claim 1, wherein a guard ring is provided at a peripheral portion of said semiconductor chip to block moisture entering from a side wall of said semiconductor chip. The semiconductor integrated circuit device according to claim 1, wherein the slit is provided outside the guard ring. 3. The semiconductor integrated circuit device according to claim 1, wherein said slit has a thin film of said plug material deposited only on a side wall thereof. 4. The semiconductor integrated circuit device according to claim 1, wherein said slit is provided continuously along a peripheral portion of said semiconductor chip. 5. The semiconductor integrated circuit according to claim 1, wherein the concentration of boron in the silicon oxide film is 10 mol% or more. 6. The semiconductor integrated circuit device according to claim 1, wherein said plug is made of conductive polycrystalline silicon containing impurities as a semiconductor material. 7. The semiconductor integrated circuit device according to claim 1, wherein tungsten, titanium nitride, aluminum, copper, or a material obtained by laminating these metals is used as a metal material for forming said plug. Semiconductor integrated circuit. 8. The semiconductor integrated circuit device according to claim 1, wherein tungsten, titanium nitride, aluminum, copper, or a material obtained by laminating these metals is used as a metal material for forming said plug. Semiconductor integrated circuit. 9. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device has a memory cell selecting MI.
A DRAM including a memory cell having a stacked structure in which an information storage capacitor is disposed above an SFET, wherein the boron-containing silicon oxide film forms a part of an interlayer insulating film above the memory cell, and The semiconductor integrated circuit according to claim 1, wherein the plug is used in a connection hole between wirings in an upper layer of the memory cell. 10. A step of forming a first insulating film on a main surface of a semiconductor substrate, a step of forming a first wiring on the first insulating film, and a step of forming boron on the first wiring. Forming a second insulating film made of a silicon oxide film containing silicon, a step of forming a second wiring layer on the second insulating film, and a silicon oxide containing no boron on the second wiring Forming a film; opening a connection hole exposing the second wiring layer in the third insulating film; and forming the third insulating film and the third hole in a peripheral portion of a main surface of the semiconductor substrate. Forming a groove reaching the interface with the second insulating film and having a width of at least twice the diameter of the connection hole; and forming a film on the third insulating film having a thickness of at least twice the diameter of the connection hole. After the semiconductor film or metal film is deposited, dry etching is performed on the entire surface and semiconductor or Forming a genus plug, method of manufacturing a semiconductor integrated circuit which comprises a step of forming a third wiring layer on the plug. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein said groove is continuously opened along a peripheral portion of said semiconductor substrate. Method.