JPH10172980A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a FLR (field limiting ring) 15 in a semiconductor device having a buried layer, but it has not been possible to sufficiently improve the breakdown voltage. SOLUTION: A buried layer 14 is formed in a first region 14 at the center.
a and the second region 14b surrounding this. The distance between the surface of the semiconductor substrate 8 and the second region 14b is larger than the distance between the surface of the semiconductor substrate 8 and the first region 14a. The PN junction of the transistor is arranged on the first region 14a. The FLR region 15 is arranged on the second region 14b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a buried layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional transistor having a planar structure having a buried layer is composed of a P-type semiconductor substrate region 1, an N ^{+ -type} buried layer 2, an N ^{+ -type} collector extraction region 3, and an N-type epitaxial layer, as shown in FIG. The collector region 4,
It has a P-type base region 5, an N ⁺ -type emitter region 6, and a P-type isolation diffusion region 7. An insulating film 9 is provided on the surface of the silicon semiconductor substrate 8 including these, and the collector electrode 10, the base electrode 11, the emitter electrode 1
2 are provided. The collector electrode 10 is in low-resistance contact with the N ^{+ -type} collector extraction region 3, the base electrode 11 is in low-resistance contact with the P-type base region 5, and the emitter electrode 12 is in low contact with the N ⁺ -type emitter region 6. In the semiconductor device of FIG. 1, other elements such as a MOSFET are also formed. These elements are electrically isolated from the transistor by an isolation diffusion region 7.

[0003]

In order to improve the breakdown voltage of the PN junction 13 formed at the interface between the N-type collector region 4 and the P-type base region 5 in the transistor as shown in FIG. A field limiting ring or FLR (Field Lim) composed of the same P-type semiconductor region so as to surround the outer periphery of the P-type base region 5.
It is possible to form an iting Ring) region. The FLR is also called a guard ring, and contributes to the improvement of the breakdown voltage of the planar structure. However, simply forming the FLR does not provide a sufficient improvement in breakdown voltage. This is because the depletion layer extending from the FLR region reaches the N-type buried layer 2 (reach-through), the extension of the depletion layer is restricted, and the electric field relaxation effect by the depletion layer is not sufficiently exhibited. If the N-type buried layer 2 is sufficiently separated from the P-type base region 5, the reach-through is prevented, but the operating resistance of the transistor, that is, the on-resistance increases, which is not desirable.

An object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage and a method of manufacturing the same.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the above object, an invention of an apparatus comprises a main region including at least one PN junction, and a field region formed so as to surround the main region. A semiconductor device comprising a limiting ring region and a buried layer, wherein the buried layer has a first region and a second region, wherein the first region is disposed below the main region; The second region is disposed below the field limiting ring region, and the surface of the semiconductor substrate on the side where the main region and the field limiting ring region are formed, and the second region Is set larger than the distance between the surface and the first region. Also, the invention of the method is characterized in that the first impurity is diffused into the first predetermined region of the semiconductor substrate to form the first impurity.
Forming an impurity diffusion region of the first type and a second impurity having a lower diffusion rate than the first impurity in a second predetermined region including the first predetermined region and the peripheral region. Forming a second impurity diffusion region by diffusing shallower than the diffusion region; and forming a semiconductor epitaxial layer by an epitaxial growth method on a surface of the semiconductor substrate on which the first and second impurity diffusion regions are formed; At the same time, by diffusing impurities in the first and second impurity diffusion regions, the first region having a first distance with respect to the surface of the semiconductor epitaxial layer and the first region with respect to the surface of the semiconductor epitaxial layer. Obtaining a buried layer comprising: a second region having a second distance longer than the first distance; and a first region of the semiconductor epitaxial layer. Forming a semiconductor device comprising at least one PN junction in the upper part of the region, the field in the upper part of the second region of the semiconductor epitaxial layer
And a step of forming a limiting ring region.

[0006]

According to the invention of each claim, the distance between the second region and the substrate surface is made longer than the distance between the first region of the buried layer and the substrate surface. Is maintained, and reach-through based on the field limiting ring area can be prevented. According to the second aspect of the present invention, the first and second regions of the buried layer can be easily formed.

[0007]

Next, a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to FIGS. FIG.
The semiconductor device (integrated circuit) of the present embodiment shown in FIG. 1 includes a transistor having a planar structure as in FIG. This transistor has a P-type semiconductor substrate region 1, an N ^{+ type} buried layer 14,
N ^{+ type} collector extraction region 3, collector region 4 comprising an N type epitaxial layer, P type base region 5, N ^{+ type} emitter region 6, P type isolation diffusion region 7, and P type FLR
(Field limiting ring) region 15. An insulating film 9 is provided on the surface of the silicon semiconductor substrate 8 including these components. A collector electrode 10, a base electrode 11, and an emitter electrode 12 are provided in openings of the insulating film 9. The collector electrode 10 is in low resistance contact with the N ^{+ -type} collector extraction region 3, the base region 11 is in low contact with the P-type base region 5, and the emitter electrode 12 is in low contact with the N ⁺ -type emitter region 6. In the semiconductor device of FIG. 2, other elements such as a MOSFET and the like are further formed, and these are electrically separated from the transistor by an isolation diffusion region 7.

The P-type FLR region 15 is formed so as to surround the base region 5 in a ring shape when viewed in plan. The collector extraction region 3 is formed so as to surround the FLR region 15 in a ring shape when viewed in plan.

The buried layer 14 comprises a first region 14a provided below the main region of the transistor and a second region 14b provided on the outer peripheral side. The first region 14a of the buried layer 14 is formed so as to substantially overlap the P-type base region 5 as a main region in plan view, that is, so that its outer peripheral edge is located immediately below the outer peripheral edge of the P-type base region 5. Have been. The thickness of the first region 14a is about 17 μm, and its impurity concentration is about 1 × 10 ¹⁹ cm ⁻³ . The second region 14b of the buried layer 14 is formed in a planar annular shape so as to surround the outer periphery of the first region 14a.
It is disposed between the first region 14a and the collector extraction region 3 across the region directly below the region 15, and is connected to them. The thickness of the second region 14b is about 13 μm, and the impurity concentration is about 1 × 10 ¹⁸ cm ⁻³ .

The first region 14a of the buried layer 14 is
A step is generated between these regions and the region 14b based on the difference in thickness. The first area 14a is the second area 14b
Since it is formed thicker, the distance between the surface of the semiconductor substrate 8 and the first region 14a is smaller than the distance between the surface of the semiconductor substrate 8 and the second region 14b. Therefore, the second region 14b is far from the FLR region 15 and the FLR region 1
5 and the buried layer 14 are shorter than before, and the breakdown voltage of the PN junction 13 is improved. That is, the PN formed at the interface between the P-type base region 5 and the N-type collector region 4
When a voltage in the direction of reverse biasing the junction 13 is applied,
A depletion layer extends from the PN junction 13. This depletion layer spreads mainly toward the N-type collector region 4 because the N-type collector region 4 has a lower impurity concentration than the P-type semiconductor region 5. When the applied voltage increases, the FLR region 15
Junction 1 formed at the interface between the N-type collector region 4 and
The depletion layer expands from 6. However, the upper surface of the second region 14b of the buried layer 14 below the FLR region 15 is displaced downward from the first region 14a.
The depletion layer extending downward from the R region 15 does not easily reach the buried layer 14. Therefore, the extension of the depletion layer on the surface of the semiconductor substrate 8 is not limited, and a high breakdown voltage is satisfactorily achieved. Further, since the first region 14a is formed below the P-type base region 5 so as to have the same interval as that of the conventional example, the ON resistance of the transistor is sufficiently low similarly to the transistor of FIG. Maintained at the level.

Next, a method of manufacturing the semiconductor device of FIG. 2 will be described with reference to FIGS. First, as shown in FIG. 3, a P-type silicon semiconductor substrate 21 for epitaxial growth is formed.
Is formed, an oxide film mask 23 having an opening 24 corresponding to the first region 14a is formed, and phosphorus (first impurity), which is an N-type impurity, is diffused into the P-type substrate 21 through the opening 24. An N ^{+ -type} phosphorus diffusion region 24 is formed as a first impurity diffusion region. Phosphorus diffuses relatively deeply in a short time because of its relatively large diffusion coefficient (velocity).

Next, as shown in FIG. 4, an oxide mask 26 having an opening 25 substantially corresponding to both the first and second regions 14a and 14b of the buried layer 14 of FIG.
Then, antimony (second impurity), which is an N-type impurity, is diffused through the opening 25. Since antimony has a smaller diffusion coefficient (speed) than phosphorus, it is suitable for obtaining a shallow diffusion layer. By this diffusion, an antimony diffusion region as a second impurity diffusion region shallower than the phosphorus diffusion region 24 in FIG. 27 are obtained. In this embodiment, since antimony is diffused so as to overlap with the phosphorus diffusion region 24 in FIG. 3, after the diffusion is completed, as shown in FIG. 4, both the phosphorus diffusion region 24a and both phosphorus and antimony are formed in the central portion. Diffusion region 24b. And
The phosphorus diffusion region 24a protrudes below the diffusion region 27 containing only antimony.

Next, after providing a P-type diffusion region for obtaining the isolation region 7, an N-type epitaxial layer 28 is formed on a P-type substrate 21 by a known epitaxial growth method as shown in FIG. By the heating in this epitaxial growth step, each of the diffusion regions 24a, 24b,
Out-diffusion of impurities 27 occurs both above and below, and each diffusion region 24a, 24b, 27 in FIG.
The first and second regions 14a, 14 shown in FIG.
The buried layer 14 having b is obtained. Further, the separation diffusion region 7a is obtained. The buried layer 14 in FIG. 5 is the same as the buried layer 14 indicated by the same reference numeral in FIG. FIG.
And the first region 14a of FIG. 5 is composed of a combination of a region in which both phosphorus and antimony are diffused and a region in which substantially only phosphorus is diffused, and a region in which only antimony is substantially diffused. The average impurity concentration is higher than that of the second region 14b. In addition, during epitaxial growth, the substrate 2
Phosphorus and antimony evaporate from 1 and are mixed into the epitaxial layer 28. However, since this amount is smaller than these amounts in the regions 14a and 14b, this is ignored in FIG.

Next, the N ^{+ -type} collector extraction region 3, the P-type base region 5, the N ⁺ -type emitter region 6, and the isolation region 7 shown in FIG. 2 are added to the epitaxial layer 28 of FIG. To complete the semiconductor device.

When the first and second regions 14a and 14b of the buried layer 14 are formed by the method shown in FIGS. 3 to 5, the first and second regions 14a and 14b are formed by utilizing the difference between the diffusion rates of phosphorus and antimony. , 14b can be easily obtained.
In addition, the on-resistance can be reduced by increasing the impurity concentration of the first region 14a.

[0016]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Depletion layer from FLR region 15 is buried layer 14
, The impurity concentration of the FLR region 15 may be lower than the impurity concentration of the P-type base region 5. By doing so, the cover of the PN junction is alleviated, the electric field concentration in this portion is satisfactorily alleviated, and the withstand voltage is sufficiently improved. (2) Although a transistor having one emitter region 6 is shown in principle in FIG. 2, a power transistor can be provided by providing a large number of emitter regions or by providing an emitter region in a mesh shape. In the main region above the first region 14a of the buried layer 14, other semiconductor elements such as a MOS transistor, a diode, and a thyristor can be provided without being limited to the bipolar transistor. (3) In FIG. 4, antimony can be diffused only to the portion corresponding to the second region 14b without diffusing to the phosphorus diffusion region 24. (4) The N-type collector region 4 is a P-type semiconductor region,
The LR region 15 can be an N-type semiconductor region. Further, the conductivity type of all the semiconductor regions in FIG. 2 can be made the opposite conductivity type.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 2 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view showing one of manufacturing steps of the semiconductor device of FIG. 2;

FIG. 4 is a sectional view showing a state where antimony is diffused into the substrate of FIG. 3;

5 is a cross-sectional view showing a state in which an epitaxial layer is formed on the substrate of FIG. 4 to obtain a buried layer.

[Explanation of symbols]

 5 base region 14 buried layer 14a first region 14b second region 15 FLR region

Claims (2)

[Claims] 2. A semiconductor device comprising: a main region including at least one PN junction; a field limiting ring region formed so as to surround the main region; and a buried layer. 1st area and 2nd
Wherein the first region is disposed below the main region, the second region is disposed below the field limiting ring region, and the main region and the main region of a semiconductor substrate are provided. A semiconductor device, wherein a distance between a surface on which a field limiting ring region is formed and the second region is set to be larger than a distance between the surface and the first region. 2. A step of diffusing a first impurity into a first predetermined region of a semiconductor substrate to form a first impurity diffusion region; and a second step including the first predetermined region and a peripheral region thereof. Forming a second impurity diffusion region by diffusing a second impurity having a lower diffusion rate than the first impurity into a predetermined region to a depth smaller than that of the first impurity diffusion region; Forming a semiconductor epitaxial layer by an epitaxial growth method on the surface of the semiconductor substrate having the impurity diffusion region formed thereon, and simultaneously out-diffusing the impurities in the first and second impurity diffusion regions, thereby forming a semiconductor epitaxial layer on the surface of the semiconductor epitaxial layer. A first region having a first distance and a second region longer than the first distance with respect to the surface of the semiconductor epitaxial layer;
Obtaining a buried layer having a second region having a distance of: and forming a semiconductor device including at least one PN junction in a portion of the semiconductor epitaxial layer above the first region; Forming a field limiting ring region in a portion of the layer above the second region.