JPH10173137A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A semiconductor device capable of forming two gate electrodes having different distances from a channel layer on the same GaAs substrate with good controllability and a method of manufacturing the same are provided. SOLUTION: On a GaAs substrate 1, an i-GaAs buffer layer 2, an i-InGaAs channel layer 3, an n-AlGa
As electron supply layer 4, n-InGaP gate layer 5, n-G
aAs contact layer 6 is sequentially grown, and n-GaAs contact layer 6 is etched to form n-InGaP gate layer 5.
The surface is exposed, and then the n-InGaP gate layer 5 is etched to expose the n-AlGaAs electron supply layer 4.
Then, a gate metal is deposited on the entire surface to form a gate electrode of each FET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a GaAs compound semiconductor device having a different distance from a channel layer on the same substrate.
The present invention relates to a structure in which two gate electrodes can be formed with good controllability.

[0002]

2. Description of the Related Art In recent years, in the field of semiconductor devices, with the demand for higher performance of devices, GaAs, which is advantageous for higher speed, has been developed.
Development of an IC using a heterojunction type epitaxial crystal on an s-substrate has been actively conducted. In response to demands for higher functionality, ICs having FETs with different threshold voltages formed on the same substrate, and FETs (dual gate FETs) having two gate electrodes in one transistor have become necessary. I have.

For example, an IC for digital signal processing has both a positive E-FET and a negative D-FET with a positive threshold voltage (Vth) in order to reduce power consumption. Further, a dual gate FET is required to have a function of controlling the gain of the FET by an external signal.

[0004] In these semiconductor devices, it is necessary to form two gate electrodes so that the distance from the channel layer is different.

FIG. 5 shows an E-FET and a D-FET formed on the same substrate as a conventional example of this type of semiconductor device.
1 shows an example of the cross-sectional structure of FIG. Table 1 shows an example of the thickness, composition, and doping amount of each crystal layer.

[0006]

[Table 1]

In FIG. 5, reference numeral 1 denotes a semi-insulating GaAs substrate, and 2 denotes an i formed on the semi-insulating GaAs substrate 1.
-GaAs buffer layer 3, 3 is an i-InGaAs channel layer formed on the i-GaAs buffer layer 2, and 4 is n-InGaAs channel layer formed on the i-InGaAs channel layer 3.
The AlGaAs electron supply layer 44 is made of n-AlGaAs.
An n-GaAs layer 55 formed on the electron supply layer 4 is an n-AlGaAs layer formed on the n-GaAs layer 44.
A gate layer 6 is an n-GaAs contact layer formed on the n-AlGaAs gate layer 55, and 7 is an n-G
a hydrogen implantation region formed to reach from the surface of the aAs contact layer 6 to the inside of the semi-insulating GaAs substrate 1;
Reference numerals 101, 102, and 103 denote a source electrode, a drain electrode, and a gate electrode 201 and 20, respectively, of the E-FET 100 formed in a region on the left side of the hydrogen implantation region 7 in FIG.
Reference numerals 2203 denote a source electrode, a drain electrode, and a gate electrode of the D-FET 200 formed in a region on the right side of the hydrogen implantation region 7 in FIG.

The FETs 100 and 200 are supplied from an n-AlGaAs electron supply layer 4 having a relatively high concentration of n-type impurities having a small electron affinity and disposed on an i-InGaAs channel layer 3 having a low impurity concentration. The so-called HEMT (High-Electro-Mechanical Transistor) that operates by accumulating electrons in the channel layer 3 having a large electron affinity and acting as a channel.
An electron mobility transistor (high electron mobility transistor), which changes the electron concentration of the channel layer 3 by changing the bias voltage of the gate electrode to perform the transistor operation.

Incidentally, the threshold voltage Vth of the FET is controlled by the distance between the gate electrode and the channel layer, and the shorter the distance, the larger the threshold voltage Vth. FET of FIG.
As for the E-FET 100, the layer thickness (d1) of the n-AlGaAs electron supply layer 4 corresponds to the interval, and the D-FET 100
200, the n-AlGaAs electron supply layer 4 and the n-GaAs
Sum of the thicknesses of the s layer 44 and the n-AlGaAs gate layer 55 (d
2) corresponds to the interval, and the E-FET and the D-FET are separately formed by controlling the thickness of each layer.

FIG. 6 shows an E-FET and a DF formed on the same substrate as a conventional example of this type of semiconductor device.
The method for producing ET will be described.

First, as shown in FIG. 6A, an epitaxial layer, that is, an i-GaAs buffer layer (5,000 angstrom thick, undoped) 2, i-type is formed on a semi-insulating GaAs substrate 1 by MOCVD or the like. InGaAs channel layer (thickness 200 Å, undoped)
3, n-AlGaAs electron supply layer (thickness 220 Å, doping amount 2 × 10 ¹⁸ cm ⁻³ ) 4, n-G
aAs layer (thickness 200 Å, doping amount 1 × 10 ¹⁷ cm ⁻³ ) 44, n-AlGaAs gate layer (thickness 50 Å, doping amount 2 × 10 ¹⁸⁾
cm ^-3 ) 55, n-GaAs contact layer (thickness 100)
0 Å, doping amount 3 × 10 ¹⁸ cm ^-3 )
6 are sequentially grown, for example, hydrogen is ion-implanted to electrically isolate the FET sections from each other, and high-resistance regions 7 are formed between the regions where FETs are formed (see FIG. 6B). ). Next, n-Ga in a region including a region where a gate is formed
A first recess groove 8 is formed in the As contact layer 6 using a resist (not shown) as a mask to expose the n-AlGaAs gate layer 55 (see FIG. 6C). Next, for example, S
An n− film including an insulating film 9 such as iO in the first recess groove 8.
It is deposited on the entire surface of the GaAs contact layer 6 (see FIG. 6D), and the opening 1 for gate formation is formed by photolithography.
0 is formed on the insulating film 9 (see FIG. 6E).

Next, by photolithography, a resist 11 or the like covering only the opening 10 for forming the D-FET portion is formed, and the insulating film 9 is used as a mask to form an n-type film on the opening for forming the E-FET portion. AlGaAs gate layer 55 and n-
The GaAs layer 44 is etched to form the second recess groove 12, exposing the n-AlGaAs electron supply layer 4 (see FIG. 6 (f)). And after removing the resist 11,
A gate metal made of, for example, WSi 13 is deposited on the entire surface of the insulating film 9 including the inside of the second recess groove 12 and the inside of the gate opening 10 (see FIG. 6G), and then a resist (not shown) is masked. And gate electrodes 103 and 203 of each FET are formed (see FIG. 6 (h)). Then, an opening of the insulating film 9 is formed in the ohmic electrode forming portion by photolithography, and an ohmic electrode (for example, a source and a drain electrode of each FET) 101 made of, for example, AuGe / Ni / Au14 is provided therein.
And 102, 201 and 202, respectively, are selectively provided to complete these FETs.

Incidentally, this type of FET has a threshold Vth
Is important, and the etching process is important when forming the recess.

For example, in the step of FIG. 6C, since the etching of the first recess groove is a step of determining the threshold Vth of the D-FET, only the n-GaAs contact layer 6 is selectively etched to -AlGaAs gate layer 55
A method is used in which the surface is exposed. For example, dry etching using a chlorine-based gas or wet etching using citric acid is used.

In the etching of the second recess groove in the next step of FIG. 6F, first, only the n-AlGaAs gate layer 55 is etched to expose the surface of the n-GaAs layer 44. As in the step of FIG. 6 (c), n-Ga
It is conceivable to use a method of etching only the As layer 44 to expose the surface of the n-AlGaAs electron supply layer 4.

[0016]

However, at present, there is no method of etching only AlGaAs and stopping it with GaAs. Therefore, when forming the second recess groove as described above, first, a mixture of phosphoric acid and hydrogen peroxide is used. N-
The AlGaAs gate layer 55 is completely removed, the etching of the n-GaAs layer 44 is advanced with the same etchant, and the etching is stopped in the middle of the n-GaAs layer 44 by time control. The n-GaAs layer 44 is completely removed by selective etching using gas or citric acid, and n-AlGaAs is removed.
It is necessary to expose the surface of the electron supply layer 4. Therefore n
The GaAs layer 44 needs to have a certain thickness from the margin in the process.

However, the gain of each FET is equal to the distance d between the gate and the channel similarly to the threshold Vth.
1 and d2, the smaller the interval, the higher the gain. Therefore, increasing the thickness of the n-GaAs layer 44 is characteristically disadvantageous for the D-FET.

Therefore, it is difficult to realize a D-FET having a high gain in the above-described conventional example. If the n-GaAs layer 44 is made thinner in order to realize a D-FET with a high gain, the margin in the process of forming the second recess groove becomes small, and it is difficult to control the threshold value Vth of the E-FET. there were.

Meanwhile, as a second conventional example which can solve such a problem, there is a technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-142686. The semiconductor device described in this publication is
-Only one layer is interposed between the bottom surface of the gate electrode of the FET and the bottom surface of the gate electrode of the D-FET.

FIG. 7 shows a second conventional example of this type of semiconductor device, in which E-FETs and D-FETs formed on the same substrate are used.
1 shows an example of a cross-sectional structure of an FET.

In FIG. 7, reference numeral 61 denotes a GaAs substrate;
Denotes a GaAs channel layer formed on the GaAs substrate 61; 621, a two-dimensional electron gas formed on the GaAs channel layer 62; 63, an n-InGaP electron supply layer formed on the GaAs channel layer 62; This n-
N-GaAs formed on the InGaP electron supply layer 63
The second cap layer 65 is an n-InGaP etching stop layer formed on the n-GaAs second cap layer 64, and 66 is an n-GaAs first cap layer formed on the n-InGaP etching stop layer 65. , 67
Denotes an n ⁺ -InGaAs contact layer formed on the n-GaAs first cap layer 66, 68 denotes an element isolation region, 701 denotes an E-mode HEMT source electrode, 702 denotes an E-mode HEMT gate electrode, and 703 denotes E. Mode HE
A common electrode of the drain electrode of the MT and the source electrode of the D-mode HEMT; 704, a gate electrode of the D-mode HEMT;
Reference numeral 05 denotes a drain electrode of the D-mode HEMT.

FIG. 8 shows a method of manufacturing an E-FET and a D-FET formed on the same substrate as a second conventional example of this type of semiconductor device.

First, an MOCV is placed on a GaAs substrate 61.
By using an epitaxial growth technique such as the D method, a GaAs channel layer (thickness of 6000 angstroms, undoped) 62, an n-InGaP electron supply layer (thickness of 200 angstroms, impurity concentration of 2 × 10 ¹⁸ cm)
^-3 ) 63, n-GaAs second cap layer (thickness 500 Å, impurity concentration 2 × 10 ¹⁸ cm ^-3 ) 64,
n-InGaP etching stop layer (thickness 30 Å, impurity concentration 2 × 10 ¹⁸ cm ^-3 ) 65, n-
A GaAs first cap layer (thickness 300 Å, impurity concentration 2 × 10 ¹⁸ cm ⁻³ ) 66 is sequentially laminated.

Next, the n-GaAs first cap layer 66
The region where the gate electrode of the E-mode HEMT is to be formed is removed (recessed) by selective dry etching using photolithography technology. Also,
The n-InGaP etching stop layer 65 is removed using the resist used in this photolithography technique (first step: see FIG. 8A).

After removing the photoresist used in the photolithography technique of the first step,
Again by MOCVD or the like, an n ⁺ -InGaAs contact layer (600 Å thick, impurity concentration 1 × 10 ¹⁹ c) is formed on the n-GaAs first cap layer 66.
m- ³ ) 67 is grown on the entire surface (second step: see FIG. 8B).

Thereafter, the E-mode HEMT and the D-mode HE
After ion implantation of oxygen around the region where the MT is to be formed to increase the resistance to form an isolation region 68, the photoresist 69 is used as a mask to form the n ⁺ -InGaAs contact layer 67 in the gate portion of the D-mode HEMT. The n ⁺ -InGaAs contact layer 67 at the gate of the E-mode HEMT is removed (third step: see FIG. 8C).

The photoresist 69 used in the third step
Is patterned again to form an opening in a region where an ohmic electrode is to be formed.
The n-GaAs first cap layer 66 in the T gate portion is removed, and the n-GaAs second cap layer 64 in the E-mode HEMT gate portion is removed.

At this time, the n ⁺ -InGaAs contact layer 67 exposed in the opening of the resist is not etched. Further, the etching of the gate portion of the D-mode HEMT is stopped by the n-InGaP etching stop layer 65, and the etching of the gate portion of the E-mode HEMT is nI
Stop at the nGaP electron supply layer 63 (fourth step: FIG. 8)
(d)).

Next, a metal such as Al is formed on the entire surface including the openings formed in the third step and the fourth step by vapor deposition or sputtering, and lift-off is performed, so that the source electrode 701 of the E-mode HEMT and the E-mode HEMT are formed. The gate electrode 702, the drain electrode of the E-mode HEMT and the common electrode 703 of the source electrode of the D-mode HEMT, the gate electrode 704 of the D-mode HEMT, and the drain electrode 705 of the D-mode HEMT are formed at the same time. In addition, GaAs
On the n-InGaP electron supply layer 63 side of the channel layer 62, a two-dimensional electron gas 621 is formed under the influence of the n-InGaP electron supply layer 63 (fifth step: see FIG. 8E).

In the second conventional example, the E mode H
A common electrode 70 of the source electrode 701 of the EMT, the drain electrode of the E-mode HEMT, and the source electrode of the D-mode HEMT
3. n ⁺ as the drain electrode 705 of the D-mode HEMT
-Since it employs an InGaAs layer, it is non-alloy, and the degree of freedom of the metal material is large.

The semiconductor integrated circuit device of the second conventional example manufactured by this manufacturing method uses the same resist after re-exposure, so that the mask for manufacturing the gates of the E-mode device and the D-mode device is used. Since there is no need to consider the alignment margin, the distance between the source and the gate can be reduced, and as a result, the source resistance can be reduced and the characteristics can be improved.

Further, the semiconductor integrated circuit device of the second conventional example is such that n-GaAs is provided between the bottom surface of the gate electrode of the E-mode HEMT and the bottom surface of the gate electrode of the D-mode HEMT.
Since only the cap layer 64 is present and the selectivity between the n-GaAs cap layer 64 and the n-InGaP electron supply layer 63 below the cap layer 64 is large, the etching can be reliably stopped at the interface between these layers. As in the case of the n-GaAs layer 44 in the example, this n-G layer is formed without stopping the etching.
The aAs cap layer 64 can be etched.
Therefore, the n-GaAs cap layer 64 can be formed without considering the process margin. Therefore, the thickness of this n-GaAs cap layer 64 is
First conventional n-AlGaAs gate layer 55 and n-G
It is sufficiently possible to form a thinner than 250 angstroms, which is the sum of the thicknesses of the aAs layers 44, thereby realizing a high gain of the D-mode HEMT without impairing the controllability of the threshold value of the E-mode HEMT. be able to.

However, in the semiconductor integrated circuit device of the second conventional example, the n-GaAs cap layer 64 located between the gate electrodes 702 and 704 is made of the same crystal (GaAs) as the GaAs channel layer 62. However, according to this configuration, electrons emitted from the n-InGaP electron supply layer 63 may accumulate not only at the interface with the GaAs channel layer 62 but also at the interface with the n-GaAs cap layer 64. For this reason, a state similar to that in which two layers are formed in one HEMT is obtained, whereby a high Gm (gain) cannot be obtained, and a preferable operation cannot be obtained. there were.

In the second conventional example, when forming the gate electrode 704, the etching stop layer 65 for stopping the etching at the interface between the n-GaAs cap layer 66 and the n-GaAs cap layer 64 is formed. Provided,
For this reason, there has been a problem that the process is slightly complicated.

The present invention has been made to solve the above-mentioned conventional problems, and controls two gate electrodes having different distances from the channel layer on the same substrate without complicating the process. It is an object of the present invention to provide a semiconductor device which can be formed with good performance and can obtain a device having a favorable operation and a high gain, and a method of manufacturing the same.

[0036]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a channel layer formed on a GaAs substrate; and a first layer formed on the channel layer and having a larger band gap than the channel layer. A second gate layer formed on the first gate layer with a material different from that of the first gate layer and having a larger band gap than the channel layer; and a second gate layer formed on the first gate layer. And a second gate electrode formed on the second gate layer so as to be in contact with the first gate electrode.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, ohmic electrodes are arranged on both sides of the first gate electrode, and the threshold voltage is a positive value. Enhancement type FET (E
-FET), ohmic electrodes are arranged on both sides of the second gate electrode, and a depletion type FET (D-FE) having a negative threshold voltage is provided.
T) is formed.

According to a third aspect of the present invention, in the semiconductor device of the first aspect, the first gate electrode and the second gate electrode are formed between two ohmic electrodes, and It is assumed that a gate FET is formed.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the channel layer is made of GaAs or InGaAs.

According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the first gate layer is made of AlGaAs, and the second gate layer is made of InGaP. It is something that was taken.

According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the first gate layer is made of InGaP, and the second gate layer is made of AlGaAs. It is something that was taken.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a channel layer on a GaAs substrate; and forming a first gate layer having a larger band gap than the channel layer on the channel layer. Forming the first, and the first
Forming a second gate layer having a bandgap larger than that of the channel layer using a material different from that of the first gate layer on the first gate layer; and forming a first gate layer on the first gate layer so as to contact the first gate layer. And forming a second gate electrode so as to be in contact with the second gate layer.

According to a eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, an ohmic electrode is disposed on both sides of the first gate electrode, and Forming an enhancement-type FET (E-FET) having a positive voltage; and arranging ohmic electrodes on both sides of the second gate electrode to form a depletion-type FET having a negative threshold voltage. FE
And forming a T (D-FET).

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the seventh aspect, wherein the first gate electrode and the second gate electrode are located therebetween. The method further includes a step of forming a dual gate FET by arranging two ohmic electrodes.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the seventh to ninth aspects, wherein the channel layer is formed of GaAs or InGaAs. is there.

According to a method of manufacturing a semiconductor device according to claim 11 of the present invention, in the method of manufacturing a semiconductor device according to any one of claims 7 to 10, the first gate layer may be formed of AlG.
aAs, and the second gate layer is formed of InGaP.
Is formed.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the seventh to tenth aspects, the first gate layer is formed of InG.
aP, and the second gate layer is formed of AlGaAs.
Is formed.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 shows a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a high-resistance i-GaAs buffer layer formed on the GaAs substrate 1, and 3 is this i-GaAs buffer layer.
Undoped i-InG formed on s buffer layer 2
The aAs channel layer 4 is an electron supply layer made of n-AlGaAs having a larger band gap than the channel layer 3 formed on the i-InGaAs channel layer 3, and the channel 5 is formed on the electron supply layer 4. A gate layer made of n-InGaP having a larger band gap than the layer 3;
6 is a contact layer made of n-GaAs formed on the gate layer 5, and 7 is an E-FET 100 and a D-FET 2
00 is a high-resistance region for electrically isolating them from each other, for example, a region formed by ion implantation of hydrogen. Also, 101, 102 and 103 are E
-A source electrode, a drain electrode, and a gate electrode of the FET 100, and 201, 202, and 203 represent D-FE, respectively.
5 shows a source electrode, a drain electrode, and a gate electrode of T200. Table 2 shows an example of the thickness, composition, and doping amount of each crystal layer.

[0049]

[Table 2]

These FETs have a low impurity concentration of i-In.
N-AlGaAs having a relatively high concentration of n-type impurities having a small electron affinity and disposed on the GaAs channel layer 3
The electrons supplied from the s-electron supply layer 4 accumulate in the channel layer 3 having a large electron affinity and act as a channel, so-called HEMT (High Electron Mobility Transistor:
A high electron mobility transistor) that changes the electron concentration of the channel layer 3 by changing the bias voltage of the gate electrode to perform the transistor operation.

FIG. 2 shows a method of manufacturing these FETs. First, a semi-insulating GaAs substrate 1 by MOCVD, for example.
An i-GaAs buffer layer (5000 angstrom thick, undoped) 2, an i-InGaAs channel layer (200 angstrom thick, undoped) 3, n-
AlGaAs electron supply layer (thickness 220 Å, doping amount 2 × 10 ¹⁸ cm ⁻³ ) 4, n-InGa
P-gate layer (thickness 200 Å, doping amount 1 × 10 ¹⁸ cm ⁻³ ) 5, n-GaAs contact layer (thickness 1000 Å, doping amount 3 × 1)
0 ¹⁸ cm ⁻³ ) 6 are epitaxially grown in sequence (FIG. 2).
(a)). Next, in order to electrically isolate each FET unit,
For example, hydrogen is ion-implanted to form a high resistance region 7 between the FETs (see FIG. 2B). Next, in a region including a region where a gate is to be formed, the n-GaAs contact layer 6 is etched by ordinary photolithography and a tartaric acid-based etchant to form a first recess groove 8, and the n-InGaP gate layer 5 is formed.
Is exposed (see FIG. 2 (c)). Since the tartaric acid-based etchant does not etch the n-InGaP gate layer 5, the surface of the n-InGaP gate layer 5 can be exposed with good controllability.

Next, an insulating film 9 made of, for example, SiO
2D is deposited on the entire surface of the n-GaAs contact layer 6 including the inside of the recess groove 8 (see FIG. 2D), and an opening 10 for forming a gate is formed in the insulating film 9 by ordinary photolithography and dry etching. (See FIG. 2 (e)).

Next, the opening 10 of the D-FET portion is covered with a resist 11 or the like, and the n-InGaP gate layer 5 in the gate opening of the E-FET is etched with a hydrochloric acid-based etchant using the insulating film 9 as a mask. N-AlGa
The As electron supply layer 4 is exposed (see FIG. 2 (f)). Since the hydrochloric acid-based etching does not etch the n-AlGaAs electron supply layer 4, the surface of the n-AlGaAs electron supply layer 4 can be exposed with good controllability.

After removing the resist, a gate metal made of, for example, WSi13 is deposited on the entire surface by sputtering (see FIG. 2 (g)), and then the WSi is processed using the resist patterned by photolithography as a mask. Each F
An ET gate electrode is formed (see FIG. 2 (h)). Thereafter, an opening portion of the insulating film is provided in the ohmic electrode forming portion by photolithography, and an ohmic electrode (for example, a source and drain electrode of each FET) made of, for example, AuGe / Ni / Au14 is provided in the opening portion. It is completed (see FIG. 2 (i)).

As described above, according to the semiconductor device and the method of manufacturing the same according to the first embodiment, as described above, the i-InGaAs channel layer is used as the channel layer, and the E-FE
An n-AlGaAs electron supply layer as a T gate layer
An n-InGaP gate layer as a gate layer of the FET,
Since an n-GaAs contact layer is used as a contact layer and has a crystal structure used, n-In
Since the GaP gate layer serves as an etching stopper layer for the n-GaAs contact layer and the n-AlGaAs electron supply layer serves as an etching stopper layer for the n-InGaP gate layer, the recess etching can be performed with good controllability and the two gates can be formed. Since only one layer is interposed between the bottom surfaces of the electrodes, the two gate electrodes can be formed at positions having different distances from the channel layer with good controllability and without complicating the process. Two different FETs
(E-FET, D-FET)
The controllability of th is remarkably improved, and a D-FET with a high gain can be realized without impairing the controllability of the threshold value Vth of the E-FET.

Further, since both the electron supply layer and the gate layer are made of a material having a bandgap larger than that of the channel layer, two channel layers are not formed and the gain is large and the operation is preferable. Two FETs
And a method for producing the same.

Embodiment 2 FIG. 3 is a sectional structural view of a dual gate FET according to the second embodiment of the present invention.
In the figure, 1 is a semi-insulating GaAs substrate, 2 is this G
High resistance i-GaAs buffer layer 3 formed on aAs substrate 1, undoped i-InGaAs channel layer 3 formed on i-GaAs buffer layer 2, 4 on i-InGaAs channel layer 3 The formed n-AlGaAs having a larger band gap than the channel layer 3
The electron supply layers 5 and 5 formed on the electron supply layer 4 have a band gap of n−I larger than that of the channel layer 3.
a gate layer 6 made of nGaP; 6 a contact layer made of n-GaAs formed on the gate layer 5;
Reference numeral 302 denotes a source electrode and a drain electrode formed on the contact layer 6, and 303 and 333 denote first and second gate electrodes, respectively.

This FET has an HE similar to that of the first embodiment.
MT, in which electrons accumulated in the channel layer 3 become carriers and perform transistor operation. However, since this FET is a dual gate and is used as a variable gain amplifier, its operation is different from that of the first embodiment. That is, the first gate electrode 303 is biased to a desired voltage to operate as an amplifier, and the gain can be controlled by changing the bias voltage of the second gate electrode 333.

FIG. 4 shows a method of manufacturing this dual gate FET. First, semi-insulating G by MOCVD, for example.
a-GaAs buffer layer 2, i-In
A GaAs channel layer 3, an n-AlGaAs electron supply layer 4, an n-InGaP gate layer 5, and an n-GaAs contact layer 6 are sequentially epitaxially grown (see FIG. 4A). Next, the n-GaAs contact layer 6 is etched in a region including a region where a gate is to be formed by ordinary photolithography and a tartaric acid-based etchant to form a first recess groove 88 to expose the n-InGaP gate layer 5 ( Fig. 4 (b)
reference). The tartaric acid-based etchant does not etch the n-InGaP gate layer 5 so that the n-InGa
The surface of the P gate layer 5 can be exposed.

Next, an insulating film 9 made of, for example, SiO
Is deposited on the entire surface of the n-GaAs contact layer 6 including the inside of the recess groove 88 (see FIG. 4C), and the insulating film 9 is etched by ordinary photolithography and dry etching to form an opening for gate formation. 10 are formed (see FIG. 4D).

Next, the gate opening for forming the second gate electrode is covered with a resist 11 or the like, and the gate opening for forming the first gate electrode is covered with, for example, a hydrochloric acid-based etchant using the insulating film as a mask. The n-InGaP gate layer 5 is etched to expose the n-AlGaAs electron supply layer 4 (see FIG. 4E). Hydrochloric acid type etchant is n-
Since the AlGaAs electron supply layer 4 is not etched, the surface of the n-AlGaAs electron supply layer 4 can be exposed with good controllability.

After the resist is removed, a gate metal 13 made of, for example, WSi is deposited on the entire surface by sputtering (see FIG. 4F), and then the WSi is processed using the resist patterned by photolithography as a mask. Then, respective gate electrodes are formed (see FIG. 4 (g)). Thereafter, an opening portion of the insulating film is provided in the ohmic electrode forming portion, and an ohmic electrode (which becomes a source and drain electrode) made of, for example, AuGe / Ni / Au14 is provided, whereby the dual gate FET is completed (FIG. 4 (h)). reference).

As described above, according to the semiconductor device and the method of manufacturing the same according to the second embodiment, as described above, the i-InGaAs channel layer is used as the channel layer, and the n-type channel layer is used as the gate layer corresponding to the first gate electrode. An AlGaAs electron supply layer is formed as a gate layer corresponding to the second gate electrode by n.
-InGaP gate layer is used as a contact layer with n-Ga
Since the As contact layer has a crystal structure used, the n-InGaP gate layer is formed of n-GaAs.
n serves as an etching stopper layer for the s contact layer and n
-Since the AlGaAs electron supply layer serves as an etching stopper layer for the n-InGaP gate layer, each recess etch can be performed with good controllability and without complicating the process, and a layer interposed between the bottom surfaces of the two gate electrodes is formed. 1
Since only two layers are provided, the two gate electrodes can be formed at positions having different distances from the channel layer with good controllability, so that controllability of the threshold value Vth is remarkably improved.

Further, since both the electron supply layer and the gate layer are made of a material having a band gap larger than that of the channel layer, two channel layers are not formed, and a large gain is obtained. A dual gate FET and a method for manufacturing the same can be obtained.

Embodiment 3 In the first embodiment, n-AlGaAs is used for the first gate layer, and n-AlGaAs is used for the second gate layer.
-InGaP was used, but n-InG
Even if aP is used and n-AlGaAs is used for the second gate layer, a gate electrode can be similarly formed with good controllability. However, in this case, citric acid etching is used when forming the first recess groove (n-GaAs etching), and tartaric acid etching is used when forming the second recess.

FIG. 9 shows a sectional structure of a semiconductor device according to the third embodiment of the present invention. In the figure, 1 is a semi-insulating G
An aAs substrate 2 is a high-resistance i-GaAs buffer layer formed on the GaAs substrate 1, and 3 is an i-GaAs buffer layer.
Undoped i-InGa formed on buffer layer 2
An As channel layer 24 is an electron supply layer made of n-InGaP formed on the i-InGaAs channel layer 3 and having a band gap larger than that of the channel layer 3. A channel 25 is formed on the electron supply layer 24. A gate layer 6 made of n-AlGaAs having a band gap larger than that of the layer 3, and n-GaAs 6 formed on the gate layer 25.
A contact layer 7 consisting of E-FET 100 and DF
This is a high resistance region for electrically separating the ETs 200 from each other, and is a region formed by, for example, hydrogen ion implantation. Reference numerals 101, 102, and 103 denote a source electrode, a drain electrode, and a gate electrode of the E-FET 100, respectively, and reference numerals 201, 202, and 203 denote D-FETs, respectively.
2 shows a source electrode, a drain electrode, and a gate electrode of the FET 200. Table 3 shows an example of the thickness, composition, and doping amount of each crystal layer.

[0067]

[Table 3]

These FETs have a low impurity concentration of i-In.
N-InGaP having a relatively high concentration of n-type impurities having a small electron affinity and disposed on the GaAs channel layer 3
The electrons supplied from the electron supply layer 24 accumulate in the channel layer 3 having a high electron affinity and act as a channel, that is, a so-called HEMT (High Electron Mobility Transistor: HEMT).
A high electron mobility transistor) that changes the electron concentration of the channel layer 3 by changing the bias voltage of the gate electrode to perform the transistor operation.

FIG. 10 shows a method of manufacturing these FETs.
First, an i-GaAs buffer layer (thickness 5000 angstrom, undoped) 2, an i-InGaAs channel layer (thickness 200 angstrom, undoped) 3, n on a semi-insulating GaAs substrate 1 by MOCVD, for example.
-InGaP electron supply layer (thickness 200 Å, doping amount 1 × 10 ¹⁸ cm ⁻³ ) 24, n-AlG
aAs gate layer (thickness 220 Å, doping amount 2 × 10 ¹⁸ cm ⁻³ ) 25, n-GaAs contact layer (thickness 1000 Å, doping amount 3)
× 10 ¹⁸ cm ⁻³ ) 6 are sequentially epitaxially grown (see FIG. 10A). Next, in order to electrically isolate each FET unit, for example, hydrogen is ion-implanted to form a high-resistance region 7 between the FETs (see FIG. 10B). Next, in a region including a region where a gate is to be formed, the n-GaAs contact layer 6 is etched by normal photolithography and a citric acid-based etchant to form a first recess groove 8, and n-AlGaAs is formed.
The gate layer 25 is exposed (see FIG. 10C). Since the citric acid-based etchant does not etch the n-AlGaAs gate layer 25, the n-AlGaAs is well controlled.
The surface of the gate layer 25 can be exposed.

Next, an insulating film 9 made of, for example, SiO
Is deposited on the entire surface of the n-GaAs contact layer 6 including the inside of the recess groove 8 (see FIG. 10D), and an opening 10 for forming a gate is formed in the insulating film 9 by ordinary photolithography and dry etching. (See FIG. 10 (e)).

Next, the opening 10 of the D-FET part is covered with a resist 11 or the like, and the n-AlGaAs gate layer 25 in the gate opening of the E-FET is etched with a tartaric acid-based etchant using the insulating film 9 as a mask. Shi n-I
The nGaP electron supply layer 24 is exposed (see FIG. 10 (f)). Tartaric acid-based etching does not etch the n-InGaP electron supply layer 24, so that n-InGa has good controllability.
The surface of the P electron supply layer 24 can be exposed.

After removing the resist, a gate metal made of, for example, WSi13 is deposited on the entire surface by sputtering (see FIG. 10 (g)), and then the WSi is processed using the resist patterned by photolithography as a mask. A gate electrode of each FET is formed (see FIG. 10 (h)). Thereafter, an opening portion of the insulating film is provided in the ohmic electrode forming portion by photolithography, and an ohmic electrode (for example, a source and drain electrode of each FET) made of, for example, AuGe / Ni / Au14 is provided in the opening portion. It is completed (see FIG. 10 (i)).

As described above, according to the semiconductor device and the method for fabricating the same according to the third embodiment, as described above, the i-InGaAs channel layer is used as the channel layer and the E-FE
An n-InGaP electron supply layer was formed as a T gate layer,
Since the FET has a crystal structure using an AlGaAs gate layer as a gate layer and an n-GaAs contact layer as a contact layer, n-AlGa is used.
The As gate layer serves as an etching stopper layer for the n-GaAs contact layer, and the n-InGaP electron supply layer serves as an n-GaAs contact layer.
-Since it serves as an etching stopper layer for the AlGaAs gate layer, each recess etch can be performed with good controllability, and since only one layer is interposed between the bottom surfaces of the two gate electrodes, the two gate electrodes are connected to the channel layer. Can be formed at different positions with good controllability and without complicating the process.
(E-FET, D-FET)
The controllability of th is remarkably improved, and a D-FET with a high gain can be realized without impairing the controllability of the threshold value Vth of the E-FET.

Further, since both the electron supply layer and the gate layer are made of a material having a band gap larger than that of the channel layer, two channel layers are not formed and the gain is large and the operation is preferable. Two FETs
And a method for producing the same.

Embodiment 4 In the second embodiment, n-AlGaAs is used for the first gate layer and n-InGaP is used for the second gate layer, as in the first embodiment. Similarly, even if n-InGaP is used for the second gate layer and n-AlGaAs is used for the second gate layer, the gate electrode can be formed with good controllability. In this case, as in the third embodiment, when forming the first recess groove (n−
Citric acid-based etching is used for GaAs etching, and tartaric acid-based etching is used for forming the second recess.

FIG. 11 is a sectional structural view of a dual gate FET according to the fourth embodiment of the present invention. In the figure,
1 is a semi-insulating GaAs substrate, 2 is this GaAs substrate 1
The high-resistance i-GaAs buffer layer 3 formed on the undoped i-InGaAs channel layer 3 formed on the i-GaAs buffer layer 2 and the i-In GaAs buffer layer 24 formed on the i-GaAs buffer layer 2
An electron supply layer 25 formed on the GaAs channel layer 3 and made of n-InGaP having a larger band gap than the channel layer 3 is an n- layer formed on the electron supply layer 24 and having a larger band gap than the channel layer 3. AlGaAs
a gate layer 6 made of n-GaAs formed on the gate layer 25;
2 is a source electrode and a drain electrode formed on the contact layer 6, and 303 and 333 are first and second electrodes, respectively.
3 shows a gate electrode.

This FET has an HE similar to that of the third embodiment.
MT, in which electrons accumulated in the channel layer 3 become carriers and perform transistor operation. However, since this FET is a dual gate and used as a variable gain amplifier, its operation is different from that of the third embodiment. That is, the first gate electrode 303 is biased to a desired voltage to operate as an amplifier, and the gain can be controlled by changing the bias voltage of the second gate electrode 333.

FIG. 12 shows a method of manufacturing this dual gate FET. First, an i-GaAs buffer layer 2 and an i-I buffer layer 2 are formed on a semi-insulating GaAs substrate 1 by MOCVD, for example.
nGaAs channel layer 3, n-InGaP electron supply layer 2
4. The n-AlGaAs gate layer 25 and the n-GaAs contact layer 6 are sequentially epitaxially grown (FIG. 12A).
reference). Next, n-GaAs is formed in a region including a region for forming a gate by ordinary photolithography and a citric acid-based etchant.
The s-contact layer 6 is etched to form a first recess groove 88.
Is formed to expose the n-AlGaAs gate layer 25 (see FIG. 12B). Citric acid etchant is n-
Since the AlGaAs gate layer 25 is not etched, the surface of the n-AlGaAs gate layer 25 can be exposed with good controllability.

Next, an insulating film 9 of, for example, SiO
Is deposited on the entire surface of the n-GaAs contact layer 6 including the inside of the recess groove 88 (see FIG. 12C), the insulating film 9 is etched by ordinary photolithography and dry etching, and an opening for forming a gate is formed. 10 are formed (see FIG. 12D).

Next, the gate opening for forming the second gate electrode is covered with a resist 11 or the like, and the gate opening for forming the first gate electrode is covered with, for example, a tartaric acid-based etchant using the insulating film as a mask. The n-AlGaAs gate layer 25 is etched to form the n-InGaP electron supply layer 24.
Is exposed (see FIG. 12 (e)). Since the tartaric acid-based etchant does not etch the n-InGaP electron supply layer 24, the surface of the n-InGaP electron supply layer 24 can be exposed with good controllability.

After removing the resist, a gate metal 13 made of, for example, WSi is deposited on the entire surface by sputtering (see FIG. 12F), and then the WSi is processed using the resist patterned by photolithography as a mask. Then, respective gate electrodes are formed (see FIG. 12 (g)). Thereafter, an opening portion of the insulating film is provided in the ohmic electrode forming portion, and an ohmic electrode (which becomes a source and drain electrode) made of, for example, AuGe / Ni / Au14 is provided, whereby the dual gate FET is completed (FIG. 12 (h)).
reference).

As described above, according to the semiconductor device and the method of manufacturing the same according to the fourth embodiment, as described above, the i-InGaAs channel layer is used as the channel layer and the n-type n-type channel layer is used as the gate layer corresponding to the first gate electrode. The InGaP electron supply layer is formed as an n- layer as a gate layer corresponding to the second gate electrode.
An AlGaAs gate layer is formed as n-Ga as a contact layer.
Since each of the As contact layers has a crystal structure used, the n-AlGaAs gate layer has an n-Ga
Since the etching stopper layer of the As contact layer and the n-InGaP electron supply layer serve as the etching stopper layer of the n-AlGaAs gate layer, each recess etch can be performed with good controllability and without complicating the process. Layer intervening between the bottom surfaces of the two gate electrodes
Since only two layers are provided, the two gate electrodes can be formed at positions having different distances from the channel layer with good controllability, so that controllability of the threshold value Vth is remarkably improved.

Further, since both the electron supply layer and the gate layer are made of a material having a bandgap larger than that of the channel layer, two channel layers are not formed, the gain is large, and operation is preferable. A dual gate FET and a method for manufacturing the same can be obtained.

In the first, second, third and fourth embodiments, InGaAs is used for the channel layer. However, the present invention can be applied to a structure using GaAs. This is because, when each layer is sequentially grown on a semi-insulating GaAs substrate by using the epitaxial growth technique, instead of forming an InGaAs channel layer, Ga is used.
What is necessary is just to form an As channel layer, and with this structure, the same effects as those of the first, second, third, and fourth embodiments can be obtained.

In the above description, the channel layer is undoped. However, the channel layer need not be undoped, and the present invention can be applied to a doped structure. This is because, when each layer is sequentially grown on a semi-insulating GaAs substrate by using the epitaxial growth technique, an InGaAs channel layer or a GaAs channel layer may be formed as a doped channel layer. The same effects as in the first, second, third, and fourth embodiments can be obtained.

Further, in the above description, n-type layers are used for the first and second gate layers. However, as described above, the structure in which the channel layer is doped can be applied to the structure using the undoped layer. . This is because, when each layer is sequentially grown on a semi-insulating GaAs substrate using an epitaxial growth technique, an i-AlGaAs electron supply layer is formed instead of forming an n-AlGaAs electron supply layer and an n-InGaP gate layer.
forming an i-InGaP gate layer or n-I
Instead of forming an nGaP electron supply layer and an n-AlGaAs gate layer, an i-InGaP electron supply layer and an i-AlGa
What is necessary is just to form an As gate layer. With this structure,
The same effects as in the first, second, third, and fourth embodiments are obtained.

[0087]

As described above, according to the semiconductor device of the first aspect of the present invention, the channel layer formed on the GaAs substrate and the band gap formed on the channel layer with respect to the channel gap are formed. A first gate layer having a larger size, and a second gate layer formed on the first gate layer with a material different from that of the first gate layer and having a larger band gap than the channel layer.
, A first gate electrode formed to be in contact with the first gate layer, and a second gate electrode formed to be in contact with the second gate layer Thus, there is an effect that a semiconductor device having two gate electrodes formed with good controllability and having different distances from the channel layer can be obtained.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, ohmic electrodes are arranged on both sides of the first gate electrode,
Enhancement type FET with positive threshold voltage
(E-FET) is formed, ohmic electrodes are disposed on both sides of the second gate electrode, and a depletion type FET (DF) having a negative threshold voltage is provided.
ET), two FEs with different distances to the channel layer, two gate electrodes formed with good controllability, different thresholds, and high gains.
There is an effect that a semiconductor device having T can be obtained.

According to a third aspect of the present invention, in the semiconductor device of the first aspect, the first gate electrode and the second gate electrode are formed between two ohmic electrodes. Since a dual-gate FET is formed, the effect of obtaining a semiconductor device having a high-gain dual-gate FET having two gate electrodes formed with good controllability and having different distances from the channel layer is obtained. is there.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the channel layer is made of GaAs or InGaAs.
Therefore, it has two gate electrodes formed with good controllability and having different distances from the channel layer, and GaAs or InGa as the channel layer.
There is an effect that a semiconductor device having As is obtained.

According to a fifth aspect of the present invention, in the semiconductor device of any one of the first to fourth aspects, the first gate layer is made of AlGaAs, and the second gate layer is made of InGaP. , The distance from the channel layer is different, and
The first and the first layers formed of As and InGaP with good controllability.
There is an effect that a semiconductor device having the second gate layer can be obtained.

According to a sixth aspect of the present invention, in the semiconductor device of any one of the first to fourth aspects, the first gate layer is made of InGaP, and the second gate layer is made of AlGaAs. , The distance from the channel layer is different, and InGa
The first and the first, which are formed of P and AlGaAs and have good controllability.
There is an effect that a semiconductor device having the second gate layer can be obtained.

According to the method of manufacturing a semiconductor device of the seventh aspect of the present invention, a step of forming a channel layer on a GaAs substrate and a step of forming a first layer having a larger band gap than the channel layer on the channel layer. Forming a gate layer;
Forming a second gate layer having a larger band gap than the channel layer on the first gate layer using a material different from that of the first gate layer; and forming a second gate layer on the first gate layer so as to be in contact with the first gate layer. The step of forming the first gate electrode and the step of forming the second gate electrode so as to be in contact with the above-mentioned second gate layer. There is an effect that a method for manufacturing a semiconductor device in which two gate electrodes are formed with good controllability can be obtained.

According to the method of manufacturing a semiconductor device of claim 8 of the present invention, in the method of manufacturing a semiconductor device of claim 7, ohmic electrodes are arranged on both sides of the first gate electrode. Forming an enhancement type FET (E-FET) having a positive threshold voltage, and arranging ohmic electrodes on both sides of the second gate electrode so that the threshold voltage has a negative value. Depletion type F
Forming an ET (D-FET), two gate electrodes having different distances from the channel layer are formed with good controllability, and two FETs having different thresholds and high gain are formed. There is an effect that a method of manufacturing a semiconductor device that can obtain the above is obtained.

According to a ninth aspect of the present invention, in the method of the seventh aspect, the first gate electrode and the second gate electrode are located therebetween. The method further includes the step of forming a dual gate FET by arranging two ohmic electrodes as described above, so that the distance from the channel layer differs.
There is an effect that a method of manufacturing a semiconductor device in which two gate electrodes are formed with good controllability and a high gain dual gate FET having different thresholds can be obtained.

According to the method of manufacturing a semiconductor device of claim 10 of the present invention, in the method of manufacturing a semiconductor device of any one of claims 7 to 9, the channel layer is formed of GaAs.
Since the gate electrode is formed of s or InGaAs, two gate electrodes having different distances from the channel layer can be formed with good controllability, and a method of manufacturing a semiconductor device having GaAs or InGaAs as the channel layer can be obtained. Has the effect.

According to the method of manufacturing a semiconductor device of claim 11 of the present invention, in the method of manufacturing a semiconductor device of any of claims 7 to 10, the first gate layer is formed of AlGaAs. The second gate layer is made of In
Since they were formed by GaP, each of them was made of AlG
This has the effect of providing a method of manufacturing a semiconductor device that can form first and second gate layers made of aAs and InGaP with different distances from the channel layer with good controllability.

According to the method of manufacturing a semiconductor device of the twelfth aspect of the present invention, in the method of manufacturing a semiconductor device of any one of the seventh to tenth aspects, the first gate layer is formed of InGaP. AlG for the second gate layer
Since it was formed by aAs, each of InG
There is an effect that a method of manufacturing a semiconductor device in which first and second gate layers made of aP and AlGaAs and having different distances from the channel layer can be formed with good controllability can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional structural view of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a sectional structural view of a conventional semiconductor device of this type.

FIG. 6 is a diagram showing a conventional method for manufacturing this type of semiconductor device.

FIG. 7 is a sectional structural view of another conventional semiconductor device of this type.

FIG. 8 is a view showing another conventional method of manufacturing this type of semiconductor device.

FIG. 9 is a sectional structural view of a semiconductor device according to a third embodiment of the present invention;

FIG. 10 is a diagram illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 11 is a sectional structural view of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 12 is a view illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention;

[Explanation of symbols]

1 semi-insulating GaAs substrate, 2 i-GaAs buffer layer, 3 i-InGaAs channel layer, 4 n-AlG
aAs electron supply layer, 5 n-InGaP gate layer, 6
n-GaAs contact layer, 7 hydrogen implantation region, 8 first recess groove, 9 SiO film, 10 gate opening, 1
1 resist, 12 second recess groove, 13 WSi,
14 AuGe / Ni / Au, 24 n-InGaP electron supply layer, 25 n-AlGaAs gate layer, 100
E-FET, 200 D-FET, 101, 201, 3
01 source electrode, 102, 202, 302 drain electrode, 103, 203 gate electrode, 303 first gate electrode, 333 second gate electrode.

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/812 29/80

Claims (12)

[Claims] 1. A channel layer formed on a GaAs substrate, a first gate layer formed on the channel layer and having a larger band gap than the channel layer, and a first gate layer formed on the first gate layer. A second gate layer formed of a material different from that of the first gate layer and having a larger band gap than the channel layer; and a first gate layer formed so as to be in contact with the first gate layer.
And a second gate electrode formed so as to be in contact with the second gate layer.
And a gate electrode. 2. The semiconductor device according to claim 1, wherein ohmic electrodes are arranged on both sides of said first gate electrode, and an enhancement-type FET (E-FET) having a positive threshold voltage. Ohmic electrodes are arranged on both sides of the second gate electrode to form a depletion type FET (D-FET) having a negative threshold voltage. Semiconductor device. 3. The semiconductor device according to claim 1, wherein said first gate electrode and said second gate electrode are formed between two ohmic electrodes to form a dual gate electrode.
A semiconductor device, wherein an ET is formed. 4. The semiconductor device according to claim 1, wherein said channel layer is made of GaAs or InGaAs. 5. The semiconductor device according to claim 1, wherein said first gate layer is made of AlGaAs, and said second gate layer is made of InGaP. 6. The semiconductor device according to claim 1, wherein said first gate layer is made of InGaP, and said second gate layer is made of AlGaAs. 7. A step of forming a channel layer on a GaAs substrate; a step of forming a first gate layer having a larger band gap than the channel layer on the channel layer; Forming a second gate layer having a band gap larger than that of the channel layer using a material different from that of the first gate layer; forming a first gate electrode so as to be in contact with the first gate layer; And a step of forming a second gate electrode so as to be in contact with the second gate layer. 8. The method of manufacturing a semiconductor device according to claim 7, wherein ohmic electrodes are arranged on both sides of said first gate electrode, and an enhancement type FET (E-type) having a positive threshold voltage is provided. Forming a depletion type FET (D-FET) having a negative threshold voltage by arranging ohmic electrodes on both sides of the second gate electrode. A method for manufacturing a semiconductor device, comprising: 9. The method for manufacturing a semiconductor device according to claim 7, wherein two ohmic electrodes are arranged such that the first gate electrode and the second gate electrode are located therebetween.
A method for manufacturing a semiconductor device, further comprising a step of forming a dual gate FET. 10. The method of manufacturing a semiconductor device according to claim 7, wherein the channel layer is formed of GaAs or InGaAs. 11. The method of manufacturing a semiconductor device according to claim 7, wherein the first gate layer is formed of AlGaAs, and the second gate layer is formed of InGaP. Semiconductor device manufacturing method. 12. The method of manufacturing a semiconductor device according to claim 7, wherein the first gate layer is formed of InGaP, and the second gate layer is formed of AlGaAs. Semiconductor device manufacturing method.