JPH10189618A - Field effect transistor and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide a conventional offset two-stage recess type FET,
It was difficult to reduce the source parasitic resistance. In the conventional method of manufacturing a two-stage offset recessed FET, the photolithography process has to be performed twice, and the manufacturing process is complicated and long. SOLUTION: The FET according to the present invention has a structure in which an offset recess type FET has a recess end on the source electrode 3 side coinciding with or inside the source electrode end. In the method of manufacturing an FET of the present invention, after forming source / drain electrodes 3 and 4 on the active layer 2 and forming a spacer film on the entire surface thereof, an etching groove is provided in the active layer 2 from the source electrode 3 side. Next, the spacer film is selectively etched until the end of the source electrode is exposed, the active layer 2 is again etched to form a two-step offset recess, and then the gate electrode 7 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET) having a gate electrode in a recess having a multistage recess, and a method of manufacturing the same.
In particular, the present invention relates to a field-effect transistor according to an improved multi-stage recess structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art A field effect transistor has a source electrode,
An amplifying element having three electrodes, a drain electrode and a gate electrode. An electric field effect that widens or narrows the flow path of the signal current flowing between the source and drain electrodes depending on the magnitude of the voltage applied to the intermediate gate electrode. It is a thing using. This field effect transistor is characterized by using only the effect of an electric field without passing a current to an intermediate gate electrode for controlling a signal current as compared with an ordinary transistor.

A high-frequency field-effect transistor, particularly a Schottky barrier field-effect transistor (GaAs MESFET) using GaAs, is a Si-type transistor.
It has already been put into practical use as a microwave transistor that overcomes the characteristic limits of bipolar transistors, and has achieved many achievements. In order to obtain a GaAs MESFET with high gain, high efficiency and high reliability in such a microwave region, it is important to reduce the source resistance and increase the drain breakdown voltage. In order to respond to such demands, GaAs MESFETs for high output are usually
The purpose of reducing the source parasitic resistance and increasing the drain withstand voltage has been achieved by forming the active layer of the gate electrode portion into a multi-stage recess structure.

FIG. 7 is a sectional view showing a first example of a conventional two-stage recess type field effect transistor. In the figure, 1 is a semi-insulating substrate such as GaAs, and 2 is an n-type Ga
An active layer 3 of As or the like, a source electrode 3 of AuGe alloy or the like,
4 is a drain electrode of AuGe alloy or the like, 7 is a gate electrode of Al or the like, and 8 is a two-step recess having a narrow recess at the bottom.

The field effect transistor of the first example is
A two-step recess 8 having two steps of recesses provided in the active layer 2 on the semi-insulating substrate 1, a gate electrode 7 formed in the two-step recess 8, and the active layers 2 on both sides of the gate electrode 7 It has a source electrode 3 and a drain electrode 4 formed thereon. In the two-stage recess 8, the length Ws from the end of the recess 8 on the source electrode 3 side to the end of the gate electrode 7, and the end of the gate electrode 7 from the end of the recess 8 on the drain electrode 4 side. (Wd = Ws).

According to the field effect transistor of the first example, in the two-stage recess 8, the active layer 2 between the gate electrode 7 and the drain electrode 4 is formed in two stages and is thin. Of the active layer 2 (the integral value of the product of the impurity concentration in the active layer and the thickness of the active layer) is reduced, and as a result, the drain withstand voltage can be improved.

The above-mentioned field effect transistor is manufactured as follows. First, after the source electrode 3 and the drain electrode 4 are formed on the active layer 2 on the semi-insulating substrate 1, a spacer film such as an insulating film is formed on the entire surface. Then, a resist pattern for forming a gate electrode is formed thereon,
An opening is formed by etching the spacer film using the resist pattern for forming a gate electrode as a mask, and then the active layer 2 is etched using the spacer film as a mask to form an etching groove in a part of the active layer 2. Next, the spacer film is selectively etched to widen the opening of the spacer film, and the active layer 2 provided with the etching groove is further etched using the spacer film as a mask to form a two-step recess 8. . Thereafter, the gate electrode 7 is formed at the deepest portion (in the lower narrow recess) of the two-step recess 8 using the gate electrode forming resist pattern as a mask.
By removing all of the spacer film, FIG.
The field effect transistor having the two-stage recess structure shown in FIG.

FIG. 8 is a sectional view showing a second example of a conventional two-stage recess type field effect transistor. 7, the same reference numerals as those in FIG. 7 denote the same or corresponding parts as those in FIG.

The field effect transistor of the second example is
Similar to the first example, it has a two-stage recess 8, a gate electrode 7, a source electrode 3, and a drain electrode 4. The gate electrode extends from the end of the recess 8 on the drain electrode 4 side. The length Wd to the end of the gate electrode 7 is longer than the length Ws from the end of the recess 8 on the source electrode 3 side to the end of the gate electrode 7 (Wd> Ws). It has.

According to the field effect transistor of the second example, the charge amount of the active layer 2 between the gate electrode 7 and the drain electrode 4 is reduced, as in the first example, so that the drain withstand voltage is reduced. Can be improved and W
Since d> Ws, the thick active layer 2 exists on the source electrode 3 side, and the amount of charge in this active layer 2 increases, so that the source parasitic resistance can be reduced.

The above-mentioned field effect transistor is manufactured by the following two methods. First, the first manufacturing method will be described. In the first manufacturing method, first, after a source electrode 3 and a drain electrode 4 are formed on an active layer 2 on a semi-insulating substrate 1, as a first photoengraving process, a wide upper portion of a two-step recess is formed. A resist pattern for forming a recess for forming a concave portion having a width is formed, and etching is performed using the resist pattern for forming a recess as a mask to form a wide concave portion which is biased toward the drain electrode 4 side. Then, after removing the recess-forming resist pattern, the source electrode 3 is formed as a second photolithography process in order to form a narrow recess (a recess for arranging the gate electrode 7) at the lower stage of the two-stage recess. Then, a gate electrode forming resist pattern having an opening at an intermediate position of the drain electrode 4 is formed, and then the active layer 2 is etched to form a two-step recess 8. Then, a gate electrode is formed at the deepest portion (in the narrow recess at the lower stage) of the two-step recess by using the gate electrode forming resist pattern as a mask, and then the gate electrode forming resist pattern is removed. The field effect transistor having the offset two-stage recess structure shown in FIG.

Next, a second manufacturing method will be described. The second manufacturing method is disclosed in Japanese Patent Application Laid-Open No. 4-336432. First, as shown in FIG. 9A, the surface of the active layer 2 formed on the semi-insulating substrate 1 is The source electrode 3 and the drain electrode 4 are formed at predetermined intervals. After this, FIG.
As shown in (b), over the entire surface, for example, Si ₃ N ₄
A spacer film 5 such as a film is formed. Next, as shown in FIG. 9C, a photoresist layer 6 having an opening having a predetermined width at an intermediate position between the source electrode 3 and the drain electrode 4 and covering other portions is formed. Subsequently, as shown in FIG. 10A, using the photoresist layer 6 as a mask, the spacer film 5 is removed in the same shape as the opening of the photoresist layer 6 by RIE or the like. Next, as shown in FIG. 10B, the active layer 2 is etched using the photoresist layer 6 and the spacer film 5 as a mask to form a first recess region (etching groove) 9.
To form Thereafter, as shown in FIG. 10 (c), a coating layer 8 made of Ti and having a thickness of several hundred angstroms is formed on the entire surface.
0 is formed. In this case, the covering layer 80 is formed only on the photoresist layer 6 and on the opening of the photoresist layer 6, the opening of the spacer film 5, and the side surface of the first recess region 9 on the side of the source electrode 3. So that it is obliquely attached. Subsequently, as shown in FIG. 11A, the spacer film 5 under the photoresist layer 6 is removed to a predetermined position by wet etching. In this case, the spacer film 5 on the side of the source electrode 3 on which the coating layer 80 is attached is not removed, and the etching proceeds only on the side of the drain electrode 4. Thereafter, as shown in FIG. 11B, only the coating layer 80 is selectively removed. Thereafter, as shown in FIG. 11C, the spacer film 5 is again removed by a predetermined width by wet etching using the photoresist layer 6 as a mask. As a result, the spacer film 5 is removed from the recess region 9 in an asymmetric shape that is narrower on the source electrode 3 side and wider on the drain electrode 4 side. Thereafter, as shown in FIG. 12A, the active layer 2 is dug by etching using the spacer film 5 as a mask. As a result, an offset type two-step recess 8 having different shapes on the source electrode 3 side and the drain electrode 4 side is obtained. Next, as shown in FIG. 12B, a gate electrode 7 and a gate electrode material 7 'are deposited. And FIG.
As shown in (c), the photoresist layer 6 and the gate electrode material 7 'on the photoresist layer 6 are removed.
When the spacer film 5 is completely removed, a field effect transistor in which the gate electrode 7 is disposed in the offset type two-stage recess 8 shown in FIG. 8 is completed.

[0013]

In the first conventional example shown in FIG. 7, the length (Ws) from the end of the two-step recess 8 on the source electrode 3 side to the end of the gate electrode 7 is shown. And the length (Wd) from the end of the two-stage recess 8 on the drain electrode 4 side to the end of the gate electrode 7 is equal (Wd = Ws). Therefore, there is a problem that the active layer 2 between the gate electrode 7 and the source electrode 3 is thinned, the charge amount is reduced, and the distance between the gate electrode 7 and the source electrode 3 is long, so that the source parasitic resistance is increased. .

In the second conventional example shown in FIG.
Since the offset recess structure of Wd> Ws is provided, the charge amount of the active layer 2 between the source electrode 3 and the gate electrode 7 is increased and the source parasitic resistance can be reduced as compared with the first embodiment. Since the distance between the source electrode 3 and the gate electrode 7 is large, there is a problem that it is difficult to further reduce the source parasitic resistance.

In the method of manufacturing a field-effect transistor according to the second example, the first manufacturing method may include the step of forming an upper-stage wide-width concave portion for forming the offset two-step recess 8. Since two photoengraving steps are required for the step of forming the lower narrow concavity, a mask corresponding to each of these steps is required.
There is a problem that the manufacturing process becomes long. Furthermore, since the gate electrode forming resist pattern 6 is formed on the active layer 2 in which the etching groove (the upper wide recess) is formed, it is difficult to form the resist pattern 6 at a predetermined position with high accuracy. Was.

In the second manufacturing method, the photolithography process for forming the offset two-step recess 8 is performed only once, but the coating film 8 is formed to form the offset recess structure.
Therefore, there is a problem that the manufacturing process is long and complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has an object to provide a field effect transistor having a small source parasitic resistance and capable of simplifying a manufacturing process, and a method of manufacturing the same. The purpose is to gain.

[0018]

SUMMARY OF THE INVENTION A field effect transistor according to the present invention comprises a multistage recess formed of a multistage recess provided in an active layer on a semiconductor substrate or an insulating substrate, and a gate formed in the multistage recess. An electrode, a source electrode formed on the active layer on both sides of the gate electrode, and a drain electrode, wherein the length from the drain electrode side recess end to the gate electrode end is the source electrode side recess end. An offset recess structure longer than the length from the gate electrode end to the gate electrode end, and the recess end on the source electrode side coincides with the source electrode end or enters the inside of the source electrode end. Is what you do.

According to the method of manufacturing a field effect transistor of the present invention, after forming a source electrode and a drain electrode on an active layer formed on a semiconductor substrate or an insulating substrate,
Forming a spacer film on the entire surface thereof; and forming a gate electrode forming resist pattern having an opening near the source electrode side between the source electrode and the drain electrode on the spacer film. Anisotropically etching the spacer film using a pattern as a mask, etching the active layer using the spacer film as a mask to form an etching groove in the active layer; Selectively etching the film to remove the spacer film on the source electrode side until the end of the source electrode is exposed, and selectively etching the spacer film, and then using the source electrode as a mask on the source electrode side. On the drain electrode side, using the spacer film as a mask, the active layer in which the etching groove is already formed is further etched. Forming a two-step recess of an offset type in which a lower recess is formed closer to the source electrode side, and forming a gate electrode at the deepest portion of the two-step recess using the resist pattern for forming a gate electrode as a mask. And characterized in that:

In the method of manufacturing a field-effect transistor according to the present invention, in the method of manufacturing a field-effect transistor, the selective etching of the spacer film is performed in several steps, and the selective etching of the spacer film is performed. After each step, the active layer is etched using the spacer film as a mask to form an offset-type multi-stage recess including a multi-stage recess.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. A field effect transistor according to a first embodiment of the present invention will be described. FIG. 1 shows Embodiment 1
1 is a sectional view showing a field-effect transistor according to the first embodiment. In the figure, 1 is a semi-insulating substrate made of GaAs or the like, 2
Is an active layer composed of an n-type GaAs semiconductor layer or the like;
A source electrode 4 made of a metal such as a uGe alloy
A drain electrode 7 made of a metal such as an e-alloy, 7 is a gate electrode made of a metal such as Al, and 8 is a two-step recess having a narrow recess at the bottom.

The field effect transistor according to the first embodiment has a two-stage recess 8 formed in a two-stage recess provided in an active layer 2 on a semi-insulating substrate 1, and a gate formed in the two-stage recess 8. An electrode 7 and an active layer 2 on both sides of the gate electrode 7
It has a source electrode 3 and a drain electrode 4 respectively formed thereon. The length Wd from the end of the recess 8 on the drain electrode 4 side to the end of the gate electrode 7 is the length Ws from the end of the recess 8 on the source electrode 3 side to the end of the gate electrode 7. It has a longer offset recess structure. In addition, the end of the recess 8 on the side of the source electrode 3 has a structure that enters inside the end of the source electrode 3. That is, the field effect transistor of the first embodiment and the conventional field effect transistor shown in FIG. 8 are different from the field effect transistor of FIG. 8 in the length Wd from the end of the recess 8 on the drain electrode 4 side to the end of the gate electrode 7. Offset recess structure longer than the length Ws from the end of the recess 8 on the electrode 3 side to the end of the gate electrode 7 (Wd> Ws)
In the first embodiment, the gate electrode 7 is formed closer to the source electrode 3 side with respect to the center between the source electrode 3 and the drain electrode 4, and This is greatly different in that the distance between the gate electrodes 7 is shorter than the distance between the drain electrode 4 and the gate electrode 7.

As described above, since the field effect transistor according to the first embodiment has the offset recess structure in which Wd> Ws, the gate electrode 7 and the drain electrode 4
Since the active layer 2 between them is thin, the amount of charge in the active layer 2 is reduced, and there is an effect that the drain breakdown voltage can be improved. In addition, since the end of the recess 8 on the side of the source electrode 3 has a structure in which the end enters the inside of the end of the source electrode 3, the distance between the source electrode 3 and the gate electrode 7 is short. Has the effect that the source parasitic resistance can be further reduced as compared with the conventional field effect transistor shown in FIG.

Although the semi-insulating substrate 1 is used in the first embodiment, a semiconductor substrate such as GaAs may be used instead. The recess 8 may be formed in multiple stages of two or more stages.

Embodiment 2 A method for manufacturing a field-effect transistor according to a second embodiment of the present invention will be described. 2 to 6 are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the second embodiment. In the figure, FIG.
1 are the same as or correspond to those in FIG.

The second embodiment is a method of manufacturing the field-effect transistor of the first embodiment shown in FIG. 1, and is specifically performed as follows.

First, as shown in FIG. 2, on a semi-insulating substrate 1 made of GaAs or the like, an active layer 2 made of an n-type GaAs semiconductor or the like is formed by crystal growth by MOCVD or the like. It is to be noted that the active layer 2 may be formed by forming an active layer 2 on the semi-insulating substrate 1 by ion-implanting impurities into the semi-insulating substrate 1 instead of crystal growth by MOCVD or the like. Good. Then, on the surface of the active layer 2, for example, a source electrode 3 and a drain electrode 4 composed of three layers of AuGe (alloy), Ni and Au are formed at predetermined intervals. Thereafter, over the entire surface, a spacer film 5 is formed by growing SiN or the like to a thickness of about 500 to 2000 Å. Then, a gate electrode forming resist pattern 6 having an opening 6a near the source electrode 3 side between the source / drain electrodes 3 and 4 and covering other portions is formed. Next, using the resist pattern 6 for forming a gate electrode as a mask, anisotropic etching is performed by, for example, RIE or the like to remove the spacer film 5 in the same shape as the opening 6a of the resist pattern 6 for forming a gate electrode.

Next, as shown in FIG. 3, using the spacer film 5 as a mask, the active layer 2
An etching groove 9 is formed in the active layer 2 by etching about 000 angstroms. At this time, the etching grooves 9
Is slightly larger than the opening of the spacer film 5, but may be formed so as to coincide with the opening of the spacer film 5.

Then, as shown in FIG. 4, the spacer film 5 is selectively etched with, for example, hydrofluoric acid to widen the opening of the spacer film 5. At this time, the spacer film 5 is etched on the source electrode 3 side until it exceeds the end of the source electrode. As described above, even if the spacer film 5 is etched until the end of the spacer film 5 is exceeded on the source electrode 3 side, the drain electrode end is not exposed on the drain electrode 4 side. This is because the opening of the spacer film 5 is formed closer to the source electrode 3 side by forming the gate electrode forming resist pattern 6 closer to the source electrode 3 side. The length of
It is shorter than the length from the opening to the drain electrode end. Therefore, the etching rate of the spacer film 5 depends on the rate at which the spacer film 5 advances toward the source electrode 3 from the opening and the rate at which the drain electrode 4
Since the speed of the spacer film 5 is equal to that of the spacer film 5, even if the spacer film 5 is
Is longer on the drain electrode 4 side, so that the drain electrode end is not exposed on the drain electrode 4 side.

Next, as shown in FIG.
Etch 0 to 3000 angstroms. Then, the portion where the etching groove 9 is formed is deeply etched, and as a result, a two-step recess 8 composed of two steps of recesses is formed. At this time, the source electrode 3 is etched using the source electrode 3 as a mask, and the drain electrode 4 is etched using the spacer film 5 as a mask. Therefore, in the lower narrow concave portion, an offset-type two-stage recess 8 formed near the source electrode 3 is obtained.

Finally, as shown in FIG. 6, the resist pattern 6 for forming a gate electrode is used as a mask to form, for example, Al
A gate electrode material such as is deposited to a predetermined thickness to form a gate electrode 7, and then the gate electrode forming resist pattern 6 is removed by a lift-off method.

After that, the source / drain electrodes 3 and 4
When the entire spacer film 5 is removed, the field effect transistor shown in FIG. 1 is completed.

As described above, according to the method of manufacturing the field effect transistor of the second embodiment, the length (Wd) from the recess end on the drain electrode 4 side to the end of the gate electrode 7 is:
The source electrode 3 is determined by the etching amount of the spacer film 5.
(W) from the recess end on the side to the end of the gate electrode 7
Since s) is determined by the source electrode 3, a field effect transistor having an offset recess structure satisfying Wd> Ws can be manufactured, and such an offset recess structure can be realized in one photolithography process. There is an effect that can be.

As a method of manufacturing a field-effect transistor according to the present invention, in the above-described manufacturing method, selective etching of the spacer film 5 is performed in several steps.
In addition, each time the selective etching of the spacer film 5 is completed, the active layer 2 is etched using the spacer film 5 as a mask to form an offset-type multi-stage recess including a plurality of recesses. Good.

[0035]

According to the field effect transistor of the present invention, a multi-stage recess comprising a multi-stage recess provided in an active layer on a semiconductor substrate or an insulating substrate, and a gate electrode formed in the multi-stage recess are formed. A source electrode and a drain electrode formed on the active layer on both sides of the gate electrode, wherein the length (Wd) from the drain electrode side recess end to the gate electrode end is the source electrode side recess. It has an offset recess structure longer than the length (Ws) from the end to the gate electrode end, and the recess end on the source electrode side coincides with the source electrode end or enters the inside of the source electrode end. , And thus, Wd>
Because of the Ws offset recess structure, the active layer between the gate electrode and the drain electrode is thin, so that the amount of charge in this active layer can be reduced and the drain withstand voltage can be improved. The end of the recess on the side has a structure that matches the end of the source electrode or enters inside the end of the source electrode, so that the distance between the source electrode and the gate electrode is reduced, and the conventional offset-type field effect There is an effect that source parasitic resistance can be reduced as compared with a transistor.

According to the method of manufacturing a field effect transistor of the present invention, after forming a source electrode and a drain electrode on an active layer formed on a semiconductor substrate or an insulating substrate, a spacer film is formed on the entire surface thereof. Forming a gate electrode forming resist pattern having an opening near the source electrode side between the source electrode and the drain electrode on the spacer film, and using the gate electrode forming resist pattern as a mask to form the anisotropic spacer film; Forming the etching groove in the active layer by etching the active layer using the spacer film as a mask, and forming the etching groove in the active layer so that the drain electrode end is not exposed on the drain electrode side. And selectively etch the spacer film so that the end of the source electrode is exposed on the source electrode side. After the step of removing the spacer film and selectively etching the spacer film, an etching groove was already formed using the source electrode as a mask on the source electrode side and the spacer film as a mask on the drain electrode side. Etching the active layer to form an offset-type two-step recess in which a lower recess is formed closer to the source electrode; and forming a gate at the deepest part of the two-step recess using the gate electrode forming resist pattern as a mask. Forming the electrode, wherein the length (Wd) from the drain electrode side recess end to the gate electrode end is determined by the etching amount of the spacer film, and the source electrode side recess end is formed. Since the length from the gate electrode to the gate electrode end (Ws) is determined by the source electrode, Wd> W
In addition, it is possible to manufacture a field-effect transistor having an offset recess structure that is s, and to realize such an offset recess structure in one photomechanical process, thereby shortening the FET manufacturing process. There is.

According to the method of manufacturing a field-effect transistor of the present invention, in the above-described method of manufacturing a field-effect transistor, the selective etching of the spacer film is performed in several steps. Each time the selective etching is completed, the active layer is etched using the spacer film as a mask, thereby forming an offset-type multi-stage recess including a large number of recesses,
Accordingly, there is an effect that an offset multistage recess type field effect transistor can be manufactured with the same effect as the above method.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step in a method for manufacturing a field-effect transistor according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing step following FIG. 2;

FIG. 4 is a cross-sectional view showing a manufacturing step following FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing step following FIG. 4;

FIG. 6 is a cross-sectional view showing a manufacturing step following FIG. 5;

FIG. 7 is a sectional view showing a first example of a conventional field-effect transistor.

FIG. 8 is a sectional view showing a second example of a conventional field-effect transistor.

FIG. 9 is a cross-sectional view showing a manufacturing step in a method for manufacturing a field-effect transistor according to a second conventional example.

FIG. 10 is a cross-sectional view showing a manufacturing step following FIG. 9;

FIG. 11 is a cross-sectional view showing a manufacturing step following FIG. 10;

FIG. 12 is a sectional view showing a manufacturing step following FIG. 11;

[Explanation of symbols]

1 semi-insulating substrate, 2 active layer, 3 source electrode, 4
Drain electrode, 5 spacer film, 6 gate electrode forming resist pattern, 6a opening, 7 gate electrode,
7 ′ gate electrode material, 8 two-step recess, 9 etching groove, 80 insulating film.

Claims (3)

[Claims] 1. A multistage recess comprising a multistage recess provided in an active layer on a semiconductor substrate or an insulating substrate, a gate electrode formed in the multistage recess, and an active layer on both sides of the gate electrode. An offset recess structure comprising a source electrode and a drain electrode formed on the substrate, wherein a length from the drain electrode side recess end to the gate electrode end is longer than a length from the source electrode side recess end to the gate electrode end. A field effect transistor, wherein the recessed end on the source electrode side coincides with the source electrode end or enters the inside of the source electrode end. 2. A step of forming a source electrode and a drain electrode on an active layer formed on a semiconductor substrate or an insulating substrate, and thereafter forming a spacer film on the entire surface thereof; A gate electrode forming resist pattern having an opening near the source electrode side between the drain electrodes is formed, and after the spacer film is anisotropically etched using the gate electrode forming resist pattern as a mask, the spacer film is used as a mask. Etching the active layer to form an etching groove in the active layer; and, after forming the etching groove, selectively etching the spacer film so that the source electrode side is exposed until the source electrode end is exposed. Removing the spacer film; and selectively etching the spacer film, and then masking the source electrode on the source electrode side. Forming a two-step offset type recess in which the lower recess is formed closer to the source electrode side by further etching the active layer in which the etching groove has been formed, using the spacer film as a mask on the drain electrode side. And a step of forming a gate electrode at the deepest part of the two-step recess using the gate electrode forming resist pattern as a mask. 3. The method for manufacturing a field-effect transistor according to claim 2, wherein the selective etching of the spacer film is performed several times, and each time the selective etching of the spacer film is completed, the spacer film is formed. A method for manufacturing a field effect transistor, characterized in that the active layer is etched using the film as a mask to form an offset-type multi-stage recess including a multi-stage recess.