JPH10190412A - Oscillation stop detection circuit - Google Patents

Abstract

(57) [Problem] To provide an oscillation stop detection circuit which does not require a clock pulse not to be detected and which can be constituted by an extremely small circuit. SOLUTION: A first inverter 1 in which an output inversion voltage to which an output signal of an oscillator 10 is input is closer to a power supply voltage.
1 and two inverters of a second inverter 12 on the side closer to the reference voltage, an exclusive OR circuit 13 to which the output signals of the two inverters 11 and 12 are input, and an exclusive OR An integrating circuit that receives a circuit output signal; and a comparator that receives an output voltage of the integrating circuit and determines whether the level is higher or lower than a predetermined comparison voltage. Is held at a level higher than the predetermined comparison voltage, it is detected that the oscillation amplitude of the oscillator has become small and is no longer transmitted to the subsequent circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation stop state of an oscillator for driving a device or generating a clock pulse for supplying data to the device (oscillation amplitude becomes small and clock pulses are not transmitted to a subsequent circuit). (A state in which the switch is turned on).

For example, in the case of an oscillator having a configuration in which an external oscillating unit including a crystal oscillator and a feedback resistor is connected between input and output terminals of an LSI, moisture is applied between the input and output terminals and the feedback resistor has When the value becomes apparently small, the oscillation amplitude becomes small, causing a malfunction. The present invention relates to a detection circuit in such a case.

[0003]

2. Description of the Related Art Various methods have been reported for detecting an oscillation stop when a clock pulse independent of a clock pulse to be detected can be used. As an example,
There is one disclosed in JP-A-5-122032.
However, there are many devices in the world in which a clock pulse unrelated to the clock pulse to be detected cannot be used. In many cases, a clock pulse irrelevant to the clock pulse to be detected does not always oscillate normally. JP-A-5-1220
The technique disclosed in Japanese Patent Publication No. 32 presupposes that the oscillation stop does not occur in the clock pulse irrelevant to the clock pulse to be detected.

In view of the above points, an oscillation stop detection circuit which does not require a clock pulse irrelevant to the clock pulse to be detected has been proposed in the past, and various methods for managing the charging time for the integration circuit have been reported. ing. One example is disclosed in Japanese Patent Application Laid-Open No. H2-220513.

[0005]

In the former case, in which a clock pulse irrelevant to a clock pulse to be detected (a clock pulse not to be detected) is used, a plurality of clocks are required, which increases the cost of the system. Instead, when the non-detection target clock pulse stops, there is a problem that its operation cannot be expected at all.

The above-mentioned problem has been solved by the latter oscillation stop detection circuit which does not require a non-detection target clock pulse, but the circuit scale of any of the past detection circuits is increased. Had problems. For example, the oscillation stop detection circuit disclosed in Japanese Patent Application Laid-Open No. H2-220513 requires two integration and comparison circuits and two delay circuits.

SUMMARY OF THE INVENTION The present invention has been made to solve the above technical problem, and does not require a non-detection target clock pulse and can be formed by an extremely small circuit. And a circuit for detecting an oscillation stop state in which the clock pulse is not transmitted to the subsequent circuit.

[0008]

According to a first aspect of the present invention, there is provided an oscillation stop detection circuit comprising: a first inverter having an output inverted voltage having an output signal of an oscillator as an input on a side closer to a power supply voltage; , Two inverters of a second inverter on the side closer to, an exclusive OR circuit that receives the output signals of the two inverters, and an integration comparator that receives the output signal of the exclusive OR circuit as an input It is characterized by having.

According to a second aspect of the present invention, there is provided an oscillation stop detecting circuit according to the present invention, wherein a first inverter having an output inverted voltage having an output signal of an oscillator as an input nearer to a power supply voltage and a second inverter having an inverted output voltage closer to a reference voltage. Two inverters of the two inverters, an exclusive OR circuit receiving the output signals of the two inverters, an integrating circuit receiving the exclusive OR circuit output signal, and an output of the integrating circuit And a comparator for determining whether the level is higher or lower than a predetermined comparison voltage, the input of the comparator being held at a level higher than the predetermined comparison voltage, It is characterized in that it is detected that the oscillation amplitude becomes small and is not transmitted to the subsequent circuit.

According to a third aspect of the present invention, there is provided an oscillation stop detection circuit comprising: a first inverter having an output inverted voltage having an output signal of an oscillator as an input and being closer to a power supply voltage; Two inverters of a certain second inverter, an exclusive OR circuit that receives the output signals of the two inverters, and a two-stage CMOS inverter circuit that receives the output signal of the exclusive OR circuit. A first two-stage CMOS inverter circuit in which the on-resistance of the power-supply-side P-channel MOS transistor of the subsequent-stage inverter is set to be large and the on-resistance of the ground-side N-channel MOS transistor is set to be small; A two-stage CMOS inverter circuit receiving the output voltage of the second stage as the input, wherein the inverted voltage of the preceding stage inverter is set to a predetermined comparison voltage. An inverter circuit, wherein the input of the second two-stage CMOS inverter circuit is held at a level higher than the predetermined comparison voltage, so that the oscillation amplitude of the oscillator is reduced and the oscillation is not transmitted to the subsequent circuit. Is detected.

According to the oscillation stop detection circuit of the present invention, if the oscillation is normally performed, the discharge is started before the output voltage of the integration circuit reaches a predetermined comparison voltage, and the output voltage is reduced to the comparison voltage. Never exceed. On the other hand, when the oscillation amplitude decreases and the output waveform of the oscillator changes between the inverted output voltages of the two inverters, the discharge period is completely eliminated, so that the output voltage of the integrating circuit exceeds the comparison voltage level and the power supply voltage. When the level reaches the level, oscillation stop is detected by the comparator.

According to the oscillation stop detection circuit of the present invention, if oscillation is normally performed, the first two-stage CMOS
The output of the inverter following the inverter circuit is P-channel M
The discharge by the N-channel MOS transistor is started before reaching the predetermined comparison voltage by the charging by the OS transistor, and the potential of the output does not exceed the predetermined comparison voltage. On the other hand, when the oscillation amplitude decreases and the output waveform of the oscillator changes between the inverted output voltages of the two inverters, only the P-channel MOS transistor of the subsequent inverter of the first two-stage CMOS inverter circuit is turned on. Therefore, the output voltage of the rear-stage inverter exceeds the predetermined comparison voltage and reaches the power supply voltage level, and exceeds the inverted voltage of the front-stage inverter of the second two-stage CMOS inverter circuit.
The oscillation stop is detected by the circuit.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a configuration diagram of an oscillation stop detection circuit according to an embodiment of the present invention.

The oscillation stop detecting circuit according to the present embodiment includes a first inverter 11 having an inverted output voltage, which receives an output signal of the oscillator 10 as an input, on the side closer to the power supply voltage and a second inverter 11, which is closer to the reference voltage. Two inverters of inverter 12;
An exclusive OR circuit 13 to which the output signals of the two inverters 11 and 12 are inputted, and an integrating circuit 1 comprising a resistor R and a capacitor C to which the exclusive OR circuit output signal is inputted.
4 and a comparator 15 which receives the output voltage of the integration circuit 14 as input and determines whether the level is higher or lower than a predetermined comparison voltage.

FIG. 2 shows the transfer characteristics of the inverters 11 and 12. As shown in the figure, the output inversion voltage of the inverter 11 is set closer to the power supply voltage V _CC . Further, the output inversion voltage of the inverter 12 is set closer to the reference voltage GND.

FIG. 3 shows points a, b, c, d, e and output O during normal oscillation when the oscillator 10 is oscillating normally.
3 shows a UT timing chart.

FIG. 4 shows points a, b, c, and d when the oscillation of the oscillator 10 stops (when the oscillation amplitude decreases).
4 shows a timing chart of a point, an e point, and an output OUT.

The oscillation signal output from the oscillator 10 is branched by two inverters 11 and 12 having different inversion characteristics. Oscillation signals that have passed through two inverters having different inversion characteristics become the same frequency clocks with different duties and are input to the exclusive OR circuit 13.

The operation during normal oscillation will be described with reference to FIG.

The oscillation waveform output from the oscillator 10 is a
The timing chart of the points is shown. Inverter 11,
As shown in the timing chart at the points b and c, the oscillation waveform branched by the twelve inverted voltages Vth1 and Vth2 is
Two types of rectangular waves having the same frequency and different high-level / low-level time ratios are obtained. When an exclusive OR of the two types of rectangular waves is obtained, a spike waveform shown in a timing chart at point d is obtained. The spike waveform output from the exclusive OR circuit 13 is input to the integration circuit 14.

In the integration circuit 14, when the input output signal of the exclusive OR circuit 13 is at a high level, the capacitor C is charged through the resistor R, and the input output signal of the exclusive OR circuit 13 is at a low level. At this time, all the charges charged in the capacitor C are discharged through the resistor R.

The amount of charge stored in the capacitor C increases or decreases according to the time ratio between the high level and the low level of the output signal of the exclusive OR circuit 13. Since the time ratio is constant when the oscillator 10 is oscillating normally, the maximum charge amount charged in the capacitor C also has a constant value. When the maximum potential (potential based on the maximum charge amount of the capacitor C of the normal oscillation) and V _C when the capacitance C is oscillating the potential of the point e when the full charge V _F, normally, the normal oscillation The relationship of 0 <V ≦ V _C <V _F holds for the potential V at the point e at a certain moment. The comparison voltage V _R of the comparator 15 in the integration comparison circuit is 0 <V _C <V _R
<Is set as V _F, when compared voltage is less than V _R, the comparator 15 outputs "0", if the above V _R,
The comparator 15 outputs “1”.

When the oscillation is normal, 0 <
Since V ≦ V _C <V _R <V _F holds, “0” is output from the comparator 15 (OUT = 0).

Next, the operation when the oscillation amplitude becomes small and the clock pulse is not transmitted to the subsequent circuit will be described with reference to FIG.

When the oscillation amplitude of the oscillator 10 becomes small and the oscillation waveform changes between the inverted voltages Vth1 and Vth2 of the two inverters 11 and 12, as shown in the timing chart at point a, the point b becomes high. The level is fixed, and the point c is fixed at a low level. Therefore, the exclusive OR circuit 1
As shown in the timing chart at point d, a high level is always output to the output of the comparator ₃ , so that the capacitance C of the integrating circuit 14 is fully charged, V = V _F > VR, and the comparator 15
Outputs “1” (OUT = 1).

Next, another embodiment of the present invention will be described. In the present embodiment, an integral comparison circuit (integration circuit 14 and comparator 15) in the oscillation stop detection circuit of FIG.
This is a configuration in which the integration and comparison circuit shown in FIG. 5 is replaced.

The integrating comparator circuit shown in Figure 5, electrically connected to the CMOS inverter 51 for inverting an input signal, a CMOS inverter receiving the output of the inverter 51, the on-resistance during conduction is a major P-channel MOS transistor 52 ₁ the first of the two-stage CMOS inverter circuit 50 composed of a CMOS inverter 52 on-resistance when the of small N-channel MOS transistor 52 ₂ which, CMO
Receiving an output of the S inverter 52, a CMOS inverter 54 which sets the inversion voltage to the comparison voltage V _R, the second 2-stage C consists of a phase adjustment CMOS inverter 55
And a MOS inverter circuit 53.

In the case that contains the high level input to the circuit, the signal passing through the inverter 51 goes low, N-channel transistor 52 ₂ is turned off, current flows from the power line via an on-resistance of P-channel transistors 52 ₁ Then, the gate capacitance of the inverter 54 is charged. However, since the on resistance of the P-channel transistor 52 ₁ is large, the normal oscillation mode, the potential of the point f can not reach V _R, the output of the inverter 54 does not invert (output, "0"). At oscillation stop is, as described above, the potential of the point f exceed V _R, the output of inverter 54 is inverted (output "1").

When a low level is input to the circuit, the high level is applied to the transistor 5 by the inverter 51.
2 _1, 52 ₂ is inputted to, P-channel transistors 52 ₁
Is turned off, N-channel transistor 52 ₂ is turned on.
Since the ON resistance of the transistor 52 ₂ is small, the charge accumulated in the gate of the inverter 54 is discharged rapidly.

The present invention can be applied to both cases where the oscillator 10 exists on the same semiconductor chip and where it does not exist.

[0032]

As described above in detail, the oscillation stop detecting circuit of the present invention comprises a first inverter having an inverted output voltage having an output signal of an oscillator as an input, which is closer to a power supply voltage, and a first inverter having an inverted output voltage. Two inverters of a second inverter on the near side, an exclusive-OR circuit receiving the output signals of the two inverters, and an integrating / comparing circuit receiving the output signal of the exclusive-OR circuit. More specifically, a first inverter having an inverted output voltage to which the output signal of the oscillator is input is closer to the power supply voltage and a first inverter closer to the reference voltage. Two inverters of a second inverter, an exclusive OR circuit that receives the output signals of the two inverters, an integration circuit that receives the output signal of the exclusive OR circuit, Input the output voltage A comparator for determining whether the bell is higher or lower than a predetermined comparison voltage, and when the input of the comparator is held at a level higher than the predetermined comparison voltage, the oscillation amplitude of the oscillator becomes small and It is characterized by detecting that transmission to the circuit is stopped. A first inverter having an inverted output voltage having an output signal of the oscillator as an input closer to the power supply voltage; a second inverter having a second inverter closer to the reference voltage; and the two inverters. And a two-stage CMOS inverter circuit having the exclusive OR circuit output signal as an input, wherein the power supply side P-channel MOS transistor of the latter-stage inverter has a large ON resistance. A first two-stage CMOS inverter circuit in which the on-resistance of the ground-side N-channel MOS transistor is set to be small, and a two-stage CMOS inverter circuit to which the output voltage of the first two-stage CMOS inverter circuit is input.
A second two-stage CMOS inverter circuit in which the inverted voltage of the preceding-stage inverter is set to a predetermined comparison voltage;
The input of the two-stage CMOS inverter circuit is held at a level higher than the predetermined comparison voltage, thereby detecting that the oscillation amplitude of the oscillator has become small and is no longer transmitted to the subsequent-stage circuit. It is. According to the present invention, an extremely useful oscillation stop which does not require a non-detection target clock pulse and can be realized with a small circuit scale (the oscillation amplitude of the oscillator becomes small, and the clock pulse is not transmitted to the subsequent circuit) State) detection circuit is provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an oscillation stop detection circuit according to an embodiment of the present invention.

FIG. 2 is a transfer characteristic diagram of inverters 11 and 12 in FIG.

FIG. 3 is a timing chart during normal oscillation in the embodiment.

FIG. 4 is a timing chart when the oscillation is stopped (when the oscillation amplitude is reduced) in the embodiment.

FIG. 5 is a partial configuration diagram of an oscillation stop detection circuit according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 oscillator 11 inverter 12 inverter 13 exclusive OR circuit 14 integration circuit 15 comparator 50 first two-stage CMOS inverter circuit 51 CMOS inverter 52 CMOS inverter 52 ₁ P-channel MOS transistor 52 ₂ N-channel MOS transistor 53 Second 2 -Stage CMOS inverter circuit 54 CMOS inverter 55 CMOS inverter

Claims (3)

[Claims] A first inverter having an inverted output voltage having an output signal of an oscillator as an input, the first inverter being closer to a power supply voltage; a second inverter having a second inverter being closer to a reference voltage; An oscillation stop detection circuit comprising: an exclusive OR circuit that receives output signals of the inverters; and an integration comparator that receives the exclusive OR circuit output signal. 2. An inverter having an output inversion voltage to which an output signal of an oscillator is input, the first inverter being closer to a power supply voltage, and the second inverter being closer to a reference voltage; An exclusive OR circuit that receives the output signals of the inverters, an integrating circuit that receives the exclusive OR circuit output signal, and an output voltage of the integrating circuit,
A comparator for determining whether the level is higher or lower than a predetermined comparison voltage, and the input of the comparator is maintained at a level higher than the predetermined comparison voltage, so that the oscillation amplitude of the oscillator decreases. An oscillation stop detection circuit for detecting that transmission to a subsequent circuit is stopped. 3. An inverter which receives an output signal of an oscillator as an input and has an inverted output voltage closer to a power supply voltage and a second inverter closer to a reference voltage. An exclusive-OR circuit receiving the output signals of the inverters, and a two-stage CMOS inverter circuit receiving the exclusive-OR circuit output signal, wherein the on-resistance of the power-supply-side P-channel MOS transistor of the subsequent inverter is provided. A first two-stage CMOS inverter circuit in which the on-resistance of the ground-side N-channel MOS transistor is set to be small, and a two-stage CMOS inverter circuit to which the output voltage of the first two-stage CMOS inverter circuit is input. And a second two-stage CMOS inverter circuit in which the inverted voltage of the preceding inverter is set to a predetermined comparison voltage. An oscillation stop detection circuit for detecting that the oscillation amplitude of the oscillator becomes small and is no longer transmitted to a subsequent circuit when the input of the inverter circuit is held at a level higher than the predetermined comparison voltage.