JPH10197584A - Transmission delay setting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission delay setting device which can set the amount of transmission delay to any desired value and allows checking the delay time at any time desired. SOLUTION: The data after S/P conversion is written in a memory 10 having a bit width which consists of the sum of the number of data constituting bits and one bit for delay measurement in such a way as synchronously with the timing of S/P conversion. The S/P conversion is made upon reading for a delay time corresponding to the difference (length of ring buffer) between the write address and the read address. The write and read circuits are equipped with functions to prepare the write address based upon the clock and to prepare the read address based upon the write address and the delay setting value. The delay measuring output of the memory 10 is inverted and fed back to the input so that rectangular wave signals to make inversion at each ring buffer length (time) are prepared, and the ring buffer length (time) of the memory 10, i.e., transmission delay time, is measured while the delay measuring output is used as an enable signal for a counter 203.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission delay setting device for setting a delay amount of a transmission line to a desired value during a simulation test of, for example, a power system protection digital relay, and more particularly to a delay time measuring circuit thereof.

[0002]

2. Description of the Related Art In a digital relay, information is exchanged between a self end and a counter end. In that case, a delay occurs in the transmission system (mainly the transmission path). For this reason, it is necessary to set the delay of the transmission line at the time of the simulation test of the digital relay.

The transmission path includes an optical fiber transmission path and a metallic transmission path. In the case of an optical transmission line, the delay of the transmission line may be set by installing real-length optical fiber boxes 111 and 112 between the optical PCM relays 101 and 102 as shown in FIG. The delay of the optical fiber is 5 μS / km, which is very small.

[0004] In the case of a metallic transmission line, a real-length transmission line is prepared even if the waveform is more important than the delay.

[0005]

However, in such a real-length transmission line, the length cannot be easily changed, so that an arbitrary transmission delay amount cannot be set, and transmission with a desired delay amount is not possible. It is not easy to conduct a simulation test at the right time.

For this reason, when using a two-port memory, a general-purpose memory, or a FIFO memory, an input signal is subjected to S / P conversion, stored once in a memory, read out, and subjected to P / S conversion to obtain an output signal. A transmission delay setting device has been proposed in which a delay is generated by using a difference between a write address and a read address or a time difference (delay) between a write timing and a read timing to a memory,
The applicant has previously filed an application (Japanese Patent Application No. 8-34).
No. 6993 "Transmission delay setting device").

As a result, an arbitrary amount of delay can be set without using a real-length optical fiber or the like, and a simulation test can be performed at a transmission timing with a desired amount of delay. FIG. 7 shows a connection relationship when applied to a simulation test of an optical PCM relay. In the figure, 101 and 10
2 is an optical PCM relay, 103 is a transmission delay setting device provided with two delay circuits, and 104 and 105 are both optical PCMs.
The optical-electrical converters 106 and 107 provided between the relays 101 and 102 and the transmission delay setting device 103 are optical PCs.
This is an electro-optical converter provided between the M relays 101 and 102 and the transmission delay setting device 103.

As described above, when the transmission delay setting device 103 capable of arbitrarily setting the transmission delay digitally is installed on the transmission line, as shown in FIG. An arbitrary transmission delay time t can be set with respect to the return station, and a timing simulation test of information transmission delay due to an arbitrary delay amount can be performed.

However, whether or not the output signal is delayed according to the set value cannot be confirmed unless the input and output waveforms are observed and compared. Actually, even when trying to compare the input and output transmission waveforms, the waveforms change greatly and are difficult to compare.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a delay time measuring circuit for adding one bit for delay measurement to a memory IC for transmission delay and measuring a ring buffer length (time) of the memory. By attaching
It is an object of the present invention to provide a transmission delay setting device capable of setting an arbitrary delay amount and constantly checking a delay time.

[0011]

According to the present invention, there is provided a serial / parallel conversion section for serial / parallel conversion of an input signal, and storing the serial / parallel converted data.
A two-port memory having a plurality of bit widths obtained by adding one bit to the number of data constituent bits, a parallel / serial conversion unit for performing parallel / serial conversion of data read from a transmission data part of the two-port memory, and a transmission clock A write and read circuit for generating a write address, a write signal, and a read signal, and generating a read address by adding or subtracting a write address and a delay amount setting value, and inverting an output of a 1-bit additional portion of a 2-port memory. And return to input,
A rectangular wave signal that is inverted every time corresponding to the length of the ring buffer of the port memory is created, and this output is used as an enable signal of the counter for measuring the delay time, and the time corresponding to the length of the ring buffer of the two-port memory, A delay time measuring circuit that counts a count input, latches the count result, and displays the result on a display, generates a delay corresponding to a difference between a write address and a read address, and measures and displays the delay time. It is characterized by having done.

According to the present invention, there is provided a serial / parallel converter for serial / parallel conversion of an input signal, a general-purpose memory for storing serial / parallel-converted data, a plurality of bits having a data configuration bit number added by one bit, A parallel / serial converter for parallel / serial conversion of data read from the transmission data portion of the general-purpose memory, a latch circuit provided on the output side of the serial / parallel converter, and a transmission data input side gate circuit; While generating a write address, a write signal, a read signal, and a gate switching signal based on the transmission clock,
A write and read circuit that generates a read address by adding or subtracting a write address and a delay amount setting value, and performs a time-division bus switch between the write address and the read address based on a gate switch signal; By inverting the output of the one-bit additional portion and returning it to the input, a rectangular wave signal that is inverted every time corresponding to the ring buffer length of the general-purpose memory is created, and this output is used as an enable signal of the delay time measurement counter. A delay time measuring circuit that counts the count input for a time corresponding to the length of the ring buffer of the general-purpose memory, latches the count result, and displays the result on a display device, according to the difference between the write address and the read address. A special feature is that a delay is generated and the delay time is measured and displayed. To.

The present invention also provides a serial / parallel converter for serial / parallel conversion of an input signal;
A FIFO memory having a plurality of bits with one bit added to the number of data constituent bits for storing parallel-converted data, and a parallel-to-serial converter for performing parallel-to-serial conversion of data read from a transmission data portion of the FIFO memory Counts the transmission clock, generates a write signal and an output pulse for each memory width of the transmission data part from the content, and subtracts the number of output pulses for each memory width of the transmission data part from the delay amount setting value and counts up. A write / read circuit for generating a read / P / S load signal at times, and a FIFO memory 1
By inverting the output of the bit addition portion and returning it to the input, a rectangular wave signal that is inverted every time corresponding to the depth of the FIFO memory is created, and this output is used as an enable signal of the delay time measurement counter, A delay time measuring circuit that counts a count input for a time corresponding to the depth of the memory, latches the count result, and displays the result on a display, and generates a delay due to a time difference between a write timing and a read timing; It is characterized in that the time is measured and displayed.

[0014]

FIG. 1 shows a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an S / P converter for performing serial / parallel (S / P) conversion of an input signal (serial data), and reference numeral 2 denotes an output signal of serial data by performing parallel / serial (P / S) conversion. The P / S conversion unit 10 is a two-port memory for storing S / P converted data. If the S / P conversion data has a data configuration of 8 bits, the 2-port memory 10 adds 1 bit to the 9-bit width and converts the 8-bit data parallel to the 8-bit width portion (transmission data portion) to the S / P data. Write in synchronization with the timing of P conversion. That is, the writing process is performed once every eight clocks. The one-bit additional part is used for delay time measurement. Further, the memory capacity is determined based on the maximum value of the delay amount.

Numeral 11 denotes a counter which counts clock pulses to generate a write address, 13 denotes a delay amount setting circuit, and 14 adds (or subtracts) the write address and the set delay amount to generate a read address. Or subtraction) circuit. These, together with a decoder (not shown) for creating a write signal and a read signal from the contents of the counter 11, constitute a write and read circuit of the two-port memory 10. Whether the arithmetic function of the circuit 14 is added or subtracted depends on whether the address is written to the memory while incrementing or decrementing the address. In the case of increment, subtraction is performed, and in the case of decrement, addition is performed. In this case, even if this operation is carried out of the memory space due to carry down and carry over, the memory space can be automatically used as a ring buffer by using only valid address bits. It is. Also, counter 1
1 is a ring counter that automatically circulates and generates a write address to the memory 10.

Reference numeral 201 denotes a NOT circuit (inverter) for inverting the output of the one-bit additional portion of the two-port memory 10;
A D flip-flop 02 receives the output of the NOT circuit 201 as an input. The output of the D flip-flop is used as an input of a 1-bit additional portion of the two-port memory 10. That is, by inverting the output of the one-bit additional portion of the two-port memory 10 and returning it to the input, a rectangular wave signal that is inverted every time corresponding to the ring buffer length of the two-port memory 10 is created. . 203 is a delay time measurement counter, 204
, A latch circuit; and 205, a 7-segment display for displaying the transmission delay time. Delay time counter 203
Uses the output of the one-bit additional portion of the two-port memory 10 as an enable signal and counts a count input (for example, a 10 kHz clock) for a time corresponding to the length of the ring buffer of the two-port memory. Count result is latch circuit 2
At 04, the data is latched and displayed on the display 205. When a 12 kHz counter is used and a 10 kHz clock is used as a count input, the measurement accuracy (resolution) is 0.1 ms, and the measurement range is 3
The digit display becomes 0.1 to 20.0 ms.

Next, the operation will be described. Setting circuit 14
When the delay amount of the difference between the write address and the read address is set and data is input, the input signal is S / P converted every eight clocks, and the 8-bit data is synchronized with the S / P conversion timing. Written to 10. The address is generated as the counter 11 counts the clock. The address bits are finite and have a bit length according to the memory capacity, for example. When writing an address to the memory 10 while incrementing it, the read address is determined by subtracting the delay setting value from the write address.

After writing the data, when the delay set time has elapsed, the read address becomes equal to the write address at the time of writing the data, and the data is read. This data is subjected to P / S conversion by the P / S converter 2 to become an output signal (serial data). As a result, data transmission is delayed by a time proportional to the difference between the write address and the read address. This transmission delay operation is described in the specification of the earlier application listed in the section of the problem to be solved by the invention, and the detailed description is omitted here.

On the other hand, with the writing of the transmission data, the output (eg, H level) of the D flip-flop 202 is sequentially written to the one-bit additional portion of the two-port memory 10. The writing of the H level information (the output of the D flip-flop 202) to the one-bit additional portion of the two-port memory 10 continues for the transmission data. Then, when the set delay amount has elapsed, the data is sequentially read from the corresponding memory address. The output of the one-bit additional portion of the two-port memory 10 is an enable signal for the delay time measurement counter 203, and the counter 203 is cleared at the rise from the L level to the H level. Done. The H level of the output of the one-bit additional portion of the two-port memory 10 continues for a time corresponding to the length of the ring buffer of the two-port memory 10, and the counter 203 counts the count input during that time.
The count result, that is, the count output of the transmission delay time of the transmission data is latched by the latch circuit 204, and the display 20
5 is displayed. The display of the timing is also used in the timing chart (FIG. 3) of the second embodiment described later, and the length (time) of the ring buffer indicates the transmission delay time.

The ring buffer length (time) indicating the transmission delay time corresponds to the L-level time if the input / output level relation of the 1-bit additional portion of the 2-port memory 10 is reversed. I do.

FIG. 2 shows a second embodiment of the present invention. In the figure,
1 is an S / P converter for performing serial / parallel (S / P) conversion of an input signal (serial data), and 2 is a P / S for performing parallel / serial (P / S) conversion to obtain an output signal of serial data. The converter 3, a latch circuit 3 provided on the output side of the S / P converter 1, a transmission data input gate circuit 5, a transmission data output gate circuit 20, and an S / P converter 20
This is a general-purpose memory for storing P-converted data. If the S / P conversion data has an 8-bit data configuration, the general-purpose memory 20 has a 9-bit width obtained by adding 1 bit to the 8-bit data, and the 8-bit data parallel to the 8-bit width portion (transmission data portion). Is written in synchronization with the timing of S / P conversion. That is, the writing process is performed once every eight clocks. The one-bit additional part is used for delay time measurement. Further, the memory capacity is determined based on the maximum value of the delay amount.

Reference numeral 21 denotes a counter that counts clock pulses to generate a write address; 23, a delay amount setting circuit; and 24, an addition (or subtraction) between the write address and the set delay amount to generate a read address. Or a subtraction) circuit 25, which is a multiplexer for switching the address generated by the write-side timing and the address generated by the read-side timing in a time-division manner. A gate switching signal is used as a signal for switching the multiplexer 25. A decoder (not shown) that generates a write signal, a read signal, and a gate switching signal from the contents of the counter 21 and the like,
The write / read circuit of the general-purpose memory 20 is configured. Whether the arithmetic function of the circuit 24 is added or subtracted depends on whether the address is written to the memory while incrementing or decrementing the address. In the case of increment, subtraction is performed, and in the case of decrement, addition is performed. In this case, even if this operation is carried out of the memory space due to carry down and carry over, the memory space can be automatically used as a ring buffer by using only valid address bits. It is. Further, the counter 21 for generating the write address is a ring counter, and is an address generation circuit (circuit for reloading after a time-up) that automatically circulates.

Reference numeral 201 denotes a NOT circuit (inverter) for inverting the output of the one-bit additional portion of the general-purpose memory 20;
Is a D flip-flop which receives the output of the NOT circuit 201 as an input, 206 is a delay measurement input side gate circuit which inputs the output of the D flip-flop 202 to a one-bit additional portion of the general-purpose memory 20, and 207 is a gate of the general-purpose memory 20. 1
This is a delay measurement output side gate circuit that inputs the output of the bit addition part to the NOT circuit 201. That is, by inverting the output of the one-bit additional portion of the general-purpose memory 20 and returning it to the input, a rectangular wave signal that is inverted every time corresponding to the ring buffer length of the general-purpose memory 20 is created. 203 is a delay time measurement counter, 204 is a latch circuit, and 205 is a 7-segment display for displaying the transmission delay time. The delay time measurement counter 203 uses the output of the delay measurement output side gate circuit 207 as an enable signal and counts a count input (for example, a 10 kHz clock) for a time corresponding to the length of the ring buffer of the general-purpose memory 20. The count result is latched by the latch circuit 204 and displayed on the display 205. When a 12-bit counter is used and a 10 kHz clock is used as the count input, the measurement accuracy (resolution) is 0.1 ms, and the measurement range is 3 digits.
２20.0 ms.

Next, the operation will be described. FIG. 3 shows an example of the timing. The setting circuit 24 sets a delay address corresponding to the delay set value in the address of the address generation circuit of the input unit. Input signal is S / P every 8 clocks
The 8-bit data is converted and written into the general-purpose memory 20 in synchronization with the timing of the S / P conversion. The writing process to the memory is performed when the gate switching signal is at L. In other words, when the gate switching signal falls to L, the input signals for eight clocks input before that fall to S.
/ P conversion and latched by the latch circuit 3. The latched data is written to the memory 20 at the rise of the write signal to H. The input side and output side gate circuits 4 and 5 for transmission data are connected to the input side data and the memory 2.
This is for preventing data output from 0 from colliding. When data is output from the memory 20 (during reading), the input side gate circuit 4 is closed to electrically disconnect from the input side. The gate circuits 4 and 5 are open while the gate switching signal is at L.

The write address is generated in accordance with the clock count by the counter 21, and is provided to the general-purpose memory 20 through the multiplexer 25. The address bits are finite and have a bit length according to the memory capacity, for example. When the address is written to the memory 20 while being incremented, the read address is determined by subtracting the delay setting value from the write address.

After writing the data, when the delay set time has elapsed, the read address becomes equal to the write address at the time of writing the data. This is multiplexer 2
5, the data is read out at the timing on the output side. That is, when the gate switching signal becomes H, the reading process is performed. At this time, the input side gate circuit 4 is closed. Data is read from the memory 20 in response to the fall of the read signal to L, and is input to the P / S converter 2 via the output side gate circuit 5. This data is subjected to P / S conversion by the P / S converter 2 to become an output signal (serial data). This read signal is also generated once every eight times.

On the other hand, with the writing of the transmission data, the output (eg, H level) of the D flip-flop 202 is sequentially written to the one-bit additional portion of the general-purpose memory 20. The writing of the H level information (the output of the D flip-flop 202) to the one-bit additional portion of the general-purpose memory 20 continues for the transmission data. Then, when the set delay amount has elapsed, the data is sequentially read from the corresponding memory address. The output of the one-bit additional portion of the general-purpose memory 20 becomes an enable signal of the delay time measurement counter 203 via the delay measurement output side gate circuit 207, and its L signal is output.
At the rise from the level to the H level, the counter 203 is cleared, and then the counting input is counted. The H level of the output of the 1-bit additional portion of the general-purpose memory 20 is
The time corresponding to the length of the ring buffer of the general-purpose memory 20 is continued, during which the counter 203 counts the count input. The count result, that is, the count output of the transmission delay time of the transmission data is output to the latch circuit 204.
And is displayed on the display 205. The timing indicates a ring buffer length (time), that is, a transmission delay time, as shown in FIG.

FIG. 4 shows a third embodiment of the present invention. In the figure,
1 is an S / P converter for performing serial / parallel (S / P) conversion of an input signal (serial data), and 2 is a P / S for performing parallel / serial (P / S) conversion to obtain an output signal of serial data. The conversion unit 30 is a FIFO memory IC (hereinafter, simply referred to as FIFO) for storing S / P converted data. The FIFO 30 stores 8 S / P conversion data.
In the case of a bit data configuration, one bit is added to the data configuration to make it a 9-bit width, and the 8-bit data is written in an 8-bit width portion (transmission data portion) in synchronization with the timing of S / P conversion. That is, the writing process is performed once every eight clocks. The memory depth is set to the maximum value of the delay amount or more.

Reference numeral 31 denotes a counter for counting clock pulses (8-bit counter); 33, a delay amount setting circuit;
Reference numeral 4 denotes a subtraction circuit (down counter) which sets the input delay amount of the delay amount setting circuit 33 and inputs the output (number of cycles) of the counter 31 as a subtraction input. The zero output (count-up output) of the subtraction circuit (down counter) 34 is read and used as a P / S load signal. These and a decoder (not shown) for creating a write signal from the contents of the counter 31 constitute a write / read circuit of the FIFO 30.

Numeral 201 denotes a NOT circuit (inverter) for inverting the output of the one-bit additional part of the FIFO 30, and numeral 202 denotes a D flip-flop which receives the output of the NOT circuit 201 as an input. And In other words, by inverting the output of the 1-bit additional portion of the FIFO 30 and returning it to the input, the FIFO 30
A rectangular wave signal that is inverted every time corresponding to the depth of O30 (the amount of stored data) is created. 2
03 is a delay time measurement counter, 204 is a latch circuit,
Reference numeral 205 denotes a 7-segment display for displaying the transmission delay time. The delay time measurement counter 203 is a FIFO 30
Is used as an enable signal and the FI
A time corresponding to the depth of the FO 30 and a count input (for example, 1
0 kHz clock). The count result is latched by the latch circuit 204 and displayed on the display 205. 1
When a 2-bit counter is used and a 10 kHz clock is used as a count input, the measurement accuracy (resolution) is 0.1 ms, and the measurement range is 0.1 to 20.0 ms in three digits.

Next, the operation will be described. An example of the timing is shown in FIG. In this embodiment, generation of addresses for writing and reading is not required, and a delay occurs due to a time difference between the writing timing to the FIFO 30 and the reading timing. The delay amount setting circuit 33 is configured to be capable of setting a read signal with a delay corresponding to delay data corresponding to a write signal of the input unit. The input signal is subjected to S / P conversion every eight clocks, and 8-bit data is written to an 8-bit width portion (transmission data portion) of the FIFO 30 in synchronization with the S / P conversion timing. This data is
It is immediately transferred to the outlet of the FIFO 30. After the data writing, when the delay set time has elapsed, a zero output (readout and P / S load signal) is generated in the subtraction circuit 34. Along with this, the data is read out and the P / S
It is converted to an output signal (serial data). As a result, data transmission is delayed by the time difference between the write timing and the read timing.

On the other hand, as the transmission data is written,
D flip-flop 2 is also added to the 1-bit additional part of FO30.
02 (for example, H level) is sequentially written.
The writing of the H level information (the output of the D flip-flop 202) to the 1-bit additional portion of the FIFO 30 continues for the transmission data. Then, when the set delay amount has elapsed, the information is sequentially read from the previously written delay measurement information. The output of the 1-bit additional portion of the FIFO 30 is an enable signal for the delay time measurement counter 203. The counter 203 is cleared at the rise from the L level to the H level, and then the count input is performed. The H level of the output of the 1-bit additional portion of the FIFO 30 continues for a time corresponding to the depth of the FIFO 30, and the counter 203 counts the count input during that time. The count result, that is, the count output of the transmission delay time of the transmission data is latched by the latch circuit 204 and displayed on the display 205. The timing is
As shown in FIG. 5, the depth (time) of the FIFO 30, that is, the transmission delay time is shown.

In this case as well, the depth (time) of the FIFO 30, which indicates the transmission delay time, is determined by the FIFO 30
If the input / output level relationship of the 1-bit additional portion is reversed, the L-level time corresponds to this.

As described above, each embodiment uses a memory having a bit width in which one bit for delay measurement is added to the number of bits of parallel data after S / P conversion, and a ring buffer is used in the one-bit addition part. Length (hours) or FIFO
Depth (equivalent to the length of the ring buffer in the case of RAM)
In addition to creating a rectangular wave signal that is inverted every time, the output of the one-bit additional portion is used as a count control as an enable signal of the delay time measurement counter. Can be confirmed accurately.

[0035]

As described above, according to the present invention, a memory IC having a bit width corresponding to the number of bits of a transmission data structure is used for a transmission delay, and a difference between a write address and a read address, or a write timing and a read When an arbitrary delay can be set according to the timing difference (delay), the memory bit width is set to one bit added for measuring the delay time, the output is inverted and returned to the input, and the length of the ring buffer is determined. Alternatively, a rectangular wave signal that is inverted every time corresponding to the depth of the FIFO is created, and the count input is counted, latched, and displayed by using the output of the additional one bit as the enable signal of the delay time measurement counter. Therefore, whether or not the transmission data is delayed as set can always be confirmed by the display. Moreover, there is an advantage that the confirmation can be performed easily and reliably.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a timing chart of the second embodiment.

FIG. 4 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 5 is a timing chart of the third embodiment.

FIG. 6 is a configuration explanatory view showing a conventional example.

FIG. 7 is a connection diagram in a case where a transmission delay setting device (first application) to which a memory IC is applied is applied to a simulation test of an optical PCM relay.

FIG. 8 is a delay characteristic diagram when a transmission delay setting device (first application) applied to a memory IC is applied to a simulation test of an optical PCM relay.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... S / P conversion part 2 ... P / S conversion part 3 ... Latch circuit 4 ... Transmission data input side gate 5 ... Transmission data output side gate 10 ... 2 port memory 11 ... Counter 13 ... Delay amount setting circuit 14 ... Addition or subtraction circuit 20 General-purpose memory 21 Counter 23 Delay amount setting circuit 24 Addition or subtraction circuit 25 Multiplexer 30 FIFO 31 Counter 33 Delay amount setting circuit 34 Subtraction circuit (down counter) 201 NOT circuit 202 ... D flip-flop 203 ... Delay time measurement counter 204 ... Latch circuit 205 ... 7-segment display 207 ... Delay measurement output side gate circuit

Claims (3)

[Claims] 1. A serial / parallel converter for serial / parallel conversion of an input signal, a two-port memory for storing serial / parallel-converted data and having a plurality of bit widths obtained by adding one bit to a data configuration bit number; This 2
A parallel / serial converter for converting data read from the transmission data portion of the port memory into parallel / serial; a write address, a write signal, and a read signal based on a transmission clock; A write and read circuit that generates a read address by addition or subtraction with the above, and by inverting the output of the one-bit additional portion of the two-port memory and returning it to the input, every time corresponding to the ring buffer length of the two-port memory A rectangular wave signal which is inverted to the above is generated, and this output is used as an enable signal of the delay time measurement counter, the count input is counted for a time corresponding to the length of the ring buffer of the 2-port memory, and the count result is latched. A delay time measurement circuit for displaying on the display Transmission delay setting device, characterized in that to generate a delay corresponding to the difference between dress and the read address, and was set to measure display the delay time. 2. A serial / parallel converter for serial / parallel conversion of an input signal, a general-purpose memory for storing serial / parallel-converted data and having a multi-bit width obtained by adding one bit to a data configuration bit number, A parallel / serial converter for converting the data read from the transmission data portion of the memory into parallel / serial; a latch circuit provided on the output side of the serial / parallel converter; a transmission data input side gate circuit; , A write address, a write signal, a read signal, and a gate switching signal are generated, and a read address is generated by adding or subtracting the write address and the delay amount setting value. Time-sharing based on signal By inverting the output of the 1-bit additional portion of the general-purpose memory and returning the input to the input, a rectangular wave signal that is inverted every time corresponding to the ring buffer length of the general-purpose memory is created, A delay time measuring circuit for counting the count input for a time corresponding to the length of the ring buffer of the general-purpose memory, using the output as an enable signal of the delay time measuring counter, latching the count result, and displaying the result on a display. A delay according to a difference between a write address and a read address, and measuring and displaying the delay time. 3. A serial / parallel conversion unit for serial / parallel conversion of an input signal, a FIFO memory for storing serial / parallel-converted data and having a plurality of bit widths obtained by adding one bit to the number of data constituent bits,
A parallel / serial converter for parallel / serial conversion of data read from the transmission data portion of the FO memory, counting a transmission clock, and generating a write signal and an output pulse for each memory width of the transmission data portion from the content; A write and read circuit for subtracting the number of output pulses for each memory width of the transmission data portion from the delay amount setting value and generating a read / P / S load signal when counting up, and a 1-bit additional portion of a FIFO memory Is inverted and returned to the input to generate a rectangular wave signal that is inverted every time corresponding to the depth of the FIFO memory, and this output is used as an enable signal of the delay time measurement counter, and the output of the FIFO memory is Count the count input for the time corresponding to the depth, latch this count result, and display it on the display. And a delay time measuring circuit for generates a delay by the time difference between the write timing and read timing and transmission delay setting device is characterized in that so as to measure display the delay time.