JPH10200023A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To prevent the occurrence of solder bridges when mounting a chip by soldering, and to dissipate heat generated by the chip in a dual element SOP molded semiconductor device assembled using a lead frame. Improve the performance. A resin-sealed semiconductor device in which two power semiconductor elements are mounted on a lead frame and assembled.
In a device in which a chip of the power semiconductor element 2 is solder-mounted on a pair of die pads 1a formed on a lead frame side by side, a side wall portion 1a-1 rising toward the chip mount side along the opposing side edge of the die pad.
To prevent the molten solder from spreading to the side when mounting the chip by soldering to prevent the occurrence of a solder bridge between the die pads, and to integrally connect the die pad and its external lead 1b for each die pad, The external lead is used as a heat transfer path to enhance the heat radiation of the heat generated by the chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a power device for a switching power supply or the like, in which two power semiconductor elements are mounted on a lead frame and the periphery thereof is sealed with a resin. Dual element S
The present invention relates to an OP (Small Outline Package) molded semiconductor device.

[0002]

2. Description of the Related Art First, as a semiconductor device described above, FIG. 2 shows a conventional assembly structure of a dual element SOP mold type semiconductor device using an IGBT (insulated gate bipolar transistor) as a power semiconductor element. In the figure, 1 is a lead frame, 2 is a power semiconductor element mounted on the lead frame 1, 3 is a bonding wire for internal wiring, and 4 is a resin package. Here, the lead frame 1 has a pair of die pads 1a arranged on the left and right with a slight cutting gap therebetween, and external leads 1b (collector terminals) and 1c (emitter terminals) arranged on both sides of the die pads 1a arranged on the left and right. ), 1d (gate terminal). As is well known, the lead frame is formed by stamping the above-described pattern into a band-shaped metal ribbon by press working in combination with a tie bar and a guide rail (not shown).

In order to assemble the semiconductor device, first, the collector electrode surfaces are superimposed on the left and right die pads 1a formed on the lead frame 1, the chips of the power semiconductor elements 2 are sorted and solder mounted one by one. Between the die pad 1a and the external lead 1b of the collector terminal,
A wire 3 is bonded between the power semiconductor element 2 and the external lead 1c of the emitter terminal and the external lead 1d of the gate terminal, and further, a resin package 4 is formed by a transfer molding method. Is completed.

[0004]

By the way, in the above-mentioned conventional power semiconductor device, a lead frame similar to a lead frame for an IC package is employed, and the lead frame has a flat surface over its entire surface and a die pad. And each external lead is separated, and a bonding wire connection is made between the die pad on which the power element chip is mounted and the collector external lead. Therefore, there are the following problems in terms of assemblability and heat dissipation.

1) As shown in FIG. 3, when the power semiconductor element 2 chip is solder-mounted while being distributed to the left and right die pads 1a, the molten solder flows on the surface of the die pad and spreads right and left. Is protruded from the side edge of the die pad 1a, and a defect in which the solder 5 bridges between the die pads 1a arranged on the left and right easily occurs. Therefore, in the past, when soldering a chip, the amount of solder was adjusted to a small amount to prevent the occurrence of solder bridges between the die pads. However, when the amount of solder is reduced, the bonding strength between the die pad and the chip is reduced. When the thermal stress is repeatedly applied in a heat cycle or the like, the reliability of the product is reduced due to the peeling of the solder joint surface of the chip.

2) In the power semiconductor device, it is necessary to efficiently radiate the heat generated from the power chip. In the conventional lead frame 1, the die pad 1a and each external lead 1b are required.
Are separated from each other, only the two are interconnected with the bonding wire 3, and the peripheral area of the die pad 1 a is sealed with the resin package 4. Heat can hardly be expected.

The present invention has been made in view of the above points, and is intended to be applied to a dual element SOP molded semiconductor device described above assembled using a lead frame.
It is an object of the present invention to provide a semiconductor device which solves the above-mentioned problems and improves assemblability and heat dissipation.

[0008]

According to the present invention, there is provided a resin-encapsulated semiconductor device in which two power semiconductor elements are mounted on a lead frame and assembled. A power semiconductor element chip is solder-mounted on a pair of die pads formed on a lead frame, respectively, and has the following configuration.

1) With respect to a pair of die pads arranged on the left and right sides, side walls which stand toward the chip mount side are formed along opposing side edges of each die pad, and the side walls are punched by a lead frame by press working. Simultaneously formed when forming. By adopting the lead frame of the above configuration, when the chip is solder-mounted on the die pad of the lead frame, the side wall portion formed on the side edge of each die pad serves as a partition wall for preventing the spread of the molten solder. In addition, it is possible to reliably prevent the occurrence of a solder bridge between the die pads without having to adjust the amount of solder to a small amount.

2) For each die pad arranged on the left and right, the die pad and its external lead are integrally connected to each other to form a lead frame. With this configuration, the heat generated by the power semiconductor element can be efficiently radiated to the outside by using the die pad and the external lead drawn out of the resin package in connection with the die pad as a heat transfer path.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to FIGS.
Explanation will be made based on (b). In the drawings of the embodiment, the same members corresponding to FIG. 2 are denoted by the same reference numerals. That is, in the embodiment of FIG. 1, the die pad 1a of the lead frame 1 and its external leads 1b (the power semiconductor element 2 is IG
If BT, external lead of collector terminal, MOS
In the case of an FET, an external lead of a drain terminal) is integrally connected, and for each die pad 1a,
Sidewall portions 1a-1 are formed along the side edges facing each other to rise toward the chip mount side. The side wall portion 1a-1 is formed along the opposing side edge of the die pad 1a by shearing and pressing with a press die at the same time when the lead frame 1 is punched from a metal ribbon. The upright angle of the side wall 1a-1 is formed at a right angle or an acute angle close to the right angle in accordance with the punching angle of the press die.

By employing the lead frame 1 having such a configuration, when the chip of the power semiconductor element 2 is mounted on the die pad 1a of the lead frame 1 by solder, the solder 5 is directed laterally at the side wall 1a-1. Spread is prevented. Thereby, the occurrence of the solder bridge between the die pads as described with reference to FIG. 3 can be surely prevented. The heat generated by the semiconductor chip due to the energization of the semiconductor device is controlled by the die pad
a, and the external leads 1b integrated with the die pad 1a are transferred to the outside and heat is efficiently radiated to the outside.

[0013]

As described above, according to the structure of the present invention, the pair of left and right die pads in the lead frame are formed with the side walls standing on the opposite side edges, so that the power semiconductor element is provided in each die pad. When the chip is solder-mounted, unnecessary molten solder is prevented from spreading to the side, so that the occurrence of a solder bridge between the die pads can be surely prevented.

Further, by using a lead frame in which a die pad and an external lead connected to the die pad are integrally connected to each die pad, heat radiation to the heat generated from the chip element can be reduced as compared with the conventional structure in which the die pad and the external lead are separated. Performance can be improved.

[Brief description of the drawings]

1A and 1B are assembly configuration diagrams of a dual-element SOP molded semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line XX of FIG.

FIG. 2 is a plan view of a conventional configuration for a dual-element SOP molded semiconductor device.

FIG. 3 is a diagram showing a state of occurrence of a solder bridge generated when a chip is solder-mounted on a die pad of a lead frame in the configuration of FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lead frame 1a Die pad 1a-1 Side wall part 1b-1d External lead 2 Power semiconductor element 4 Resin package 5 Solder

Claims (3)

[Claims] 1. A resin-sealed semiconductor device in which two power semiconductor elements are mounted on a lead frame and assembled.
In the case where the chip of the power semiconductor element is solder-mounted by distributing it to a pair of die pads formed on the lead frame side by side, the side wall standing up toward the chip mount side is formed along the opposite side edge of the die pad. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the side wall of the die pad is formed simultaneously with the punching of the lead frame by press working. 3. The semiconductor device according to claim 1, wherein a die pad and an external lead are integrally connected to each other for each die pad to form a lead frame.