JPH10200440A - Communication terminal - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a communication terminal capable of suppressing power consumption during standby to a design target value. SOLUTION: In step S6, "t1-A", that is, TC
From time t1 from the start of oscillation of XO to the start of the PLL synthesizer, the TCX stored in A
The time from the start of the oscillation of O to the time when the oscillation is stabilized is subtracted, and the time difference is stored in ΔA (step S).
6). Next, the process waits until the value of the timer 7 reset in step S5 becomes ΔA (step S7), and outputs Psave at the time when the value becomes ΔA to start the PLL synthesizer (step S8). In other words, if the PLL synthesizer is started in the process of step S8 after waiting for the timer 7 to reach ΔA in step S7, even if the TCXO oscillation stabilization end time is earlier than the design target, it depends on this. Instead, the PLL synthesizer is started up at the same time as the design target.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication terminal which repeats a predetermined operation at a constant period during a standby mode.

[0002]

2. Description of the Related Art Conventionally, in a terminal of a time division communication system such as a PHS, for example, at the time shown in FIG. 3 (1) in order to receive a signal (superframe) from a base station during standby within a service area. Controls the RS module (TCXO, frequency synthesizer). In the figure, T is the period of a superframe composed of a plurality of slots, t is the operation time of a TCXO (reference oscillator) in the RS module corresponding to one slot, and both T and t are constant. Accordingly, the TCXO operates with the time t at every predetermined time T, and controls the respective parts of the RS module to perform necessary operations during the standby time within the operation time t of the TCXO. That is, first, the TCXO starts oscillating (time a), and when the oscillation of the TCXO is stabilized (time a ′),
After a predetermined time, the start of the synthesizer is started (time point b). When the started-up synthesizer locks up (time point c '), when a certain soft processing time has elapsed, reception of a signal of a predetermined frequency is started based on a local oscillation signal from the synthesizer (time point c). After the reception state is continued, the reception is terminated (time point d). Further, at the time when the time t has elapsed from the time a, the oscillation of the TCXO is stopped and the RS module is turned off. Therefore, the RS module only consumes power at the level shown at each time point within a time period t corresponding to one slot in a period every T time corresponding to eight slots during standby in the service area. Thus, power consumption is suppressed as much as possible.

[0003]

However, the timings a to d shown in FIG. 3A are timings in the design target, and are actually due to variations in the accuracy of the TCXO or the like. As shown in (2), there is a case where the oscillation stabilization end point (a 'point) is earlier than the design target. Then, when the oscillation stabilization of the TCXO is completed, the time between a′-b and bc from this point is automatically determined, so that the power consumption increases.
The interval between -d becomes relatively long, and the interval between cd, which has the largest power consumption, becomes relatively long, so that the power consumption of the RS module during standby in the service area exceeds the design target.

Further, as shown in FIG. 3 (3), when the time from the start of the synthesizer start (time b) to the lock-up time (time c ') becomes shorter than the design target due to variations in accuracy. Is a soft processing time between c 'and c and is constant as described above, so that a time between cd is relatively long. Since the power consumption is the largest during the reception during the time between cd and cd, the interval between the cds where the power consumption is the largest is relatively long.
The power consumption during the standby mode of the module exceeds the design target.

The present invention has been made in view of such conventional problems, and has as its object to provide a communication terminal capable of suppressing power consumption during standby to a design target value. Things.

[0006]

According to the present invention, there is provided a reference oscillator comprising: a reference oscillator; a frequency synthesizer for receiving a reference oscillation signal from the reference oscillator and performing local oscillation at a predetermined frequency; It operates in a time-division manner, after stabilizing the oscillation operation of the reference oscillator, starting up the frequency synthesizer and locking up the local oscillation to a predetermined frequency, and then in a communication terminal that starts receiving, the communication device starts the oscillation operation of the reference oscillator. A first measuring means for measuring a time until the oscillation operation is stabilized, and a time for delaying the start of the start of the frequency synthesizer according to the time difference when the time measured by the first measuring means is shorter than a predetermined time. A second control means for measuring a time from the start of the start of the frequency synthesizer to the lock-up of the frequency synthesizer. Means and, when the time measured by the second measuring means is shorter than a predetermined time, and a second control means for delaying the reception start in accordance with the time difference.

In such a configuration, the first measuring means includes:
The time from the start of the oscillation operation of the reference oscillator to the stabilization of the oscillation operation is measured. Therefore, when the oscillation operation stabilizes earlier due to the variation in accuracy, the time measured by the first measuring means is longer than the predetermined time. Be shorter. Then, the first control means delays the start of the start of the frequency synthesizer according to the time difference. Further, the second measuring means measures the time from the start of the frequency synthesizer startup to the lock-up, and therefore, if lock-up occurs early due to variation in accuracy, the second measuring means measures the time. The measured time is shorter than the predetermined time. Then, the second control means delays the start of reception according to the time difference. Therefore, even if the time until oscillation stabilizes or the time until the synthesizer locks up due to the variation in accuracy, power consumption within a certain time does not increase.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the present invention
The PHS terminal is provided with an RF module 1 as shown in FIG. The RF module 1 is connected to an antenna 2 and provided with various circuits (not shown) required for performing frequency conversion processing such as an antenna switch for distributing transmission / reception, a TCXO (reference oscillator), a PLL synthesizer, and the like. ing. On the other hand, the BB (Base Bnd) IC 16 has
A modem 3, an ADPCM codec 4, a channel codec 5, an oscillation stability detector (OsD) 6, a timer 7, a CPU 8, and a frequency divider 9 are provided. Here, the oscillation stability detector 6 is a TCX in the RF module 1.
O based on the clock CLK input from the TCXO
A signal is output to the CPU 8 when the oscillation of is stabilized. The frequency divider 9 divides the frequency of the clock from the crystal oscillator 10 and
Input to U8, the timer 7 measures various times shown in the flow described later based on the clock from the crystal oscillator 10.

[0009] The CPU 8 includes RXon, Psav.
e, each signal of the TCXO operation is output to the RF module 1, and a PLLLD is output from the RF module 1 to the CPU 8. RXon is a signal for causing the RF module 1 to start receiving, and Psave is a PL of the RF module 1.
The signal for starting the L synthesizer, the TCXO operation, is a signal for starting the oscillation of the TCXO. PLLLD is a lockup signal of the PLL synthesizer, and is output from the RF module 1 when the PLL synthesizer locks up.

The clock of the crystal oscillator 10 is MMI
(Man-Machine interface) 11
1 designates a key operation signal from the key input unit 12 as a BBIC 16
And outputs a control signal from the BBIC 16 to the display unit 13. The speaker 14 and the microphone 15 are connected to the BBIC 16. Then, the signal received by the antenna 2 is input to the speaker 14 via the RF module 1, the modem 3, the ADPCM codec 4, and the channel codec 5, and is output as sound. Further, the sound detected by the microphone 15 is input to the RF module 1 via the channel codec 5, the ADPCM codec 4, and the modem 3, and
Radiated from the antenna 10.

Next, the operation of the present embodiment according to the above configuration will be described with reference to the flowchart of FIG. In this flowchart, the time values t1, t2, t shown in FIG.
3, the time values t1, t2, and t3 are design target values and are stored in the memory of the CPU 8 in advance.

T1: Time from the start of oscillation of the TCXO in the RF module 1 to the start of the PLL synthesizer t2: Time from the start of the PLL synthesizer to the start of reception t3: Time from the start of reception to the end of reception That is, the CPU 8 executes the processing shown in FIG. 2 at the timing of each time length T of the superframe composed of a plurality of slots shown in FIG. 3, outputs a TCXO operation signal (step S1), and Is reset (step S2). Then, in response to the TCXO operation signal, the TCXO in the RF module 1 starts oscillating from the time point a as shown in FIG. Continue with CP
U8 determines whether or not a signal has been input from the oscillation stability detector (OsD) 6 (step S3), and maintains a standby state until the signal is input. During this time, the timer 7 is set to a
While measuring the time from the point in time, the oscillation of the TCXO stabilizes over time. And TCX
When the oscillation of O is stabilized and the signal from the oscillation stability detector (OsD) 6 is input, the measured value of the timer 7 at that time is stored in the register A (step S4),
The timer 7 is reset (Step S5). Subsequently, from "t1-A", that is, the time t1 from when the TCXO starts oscillating to when the PLL synthesizer is started,
The time from the start of oscillation of the TCXO stored in A to the time when the oscillation is stabilized is subtracted, and the time difference is stored in ΔA (step S6). Next, the aforementioned step S5
The control waits until the value of the timer 7 reset at step A becomes ΔA (step S7), and outputs Psave when the value reaches ΔA to start up the PLL synthesizer (step S8).

At this time, due to the variation of the TCXO oscillation stabilization time, as shown in FIG. 3 (2), the TCXO oscillation stabilization end point (point a ') is changed to the design target (point a' of FIG. 3 (1)). ), The interval between a and a ′ becomes shorter than the design target (between a and a ′ in FIG. 3A), and “t1−
The value of A "becomes large, and a large time value is stored in [Delta] A in step S6. Therefore, in step S7, the CPU 7 waits until the timer 7 becomes [Delta] A, and then starts the PLL synthesizer in step S8. When the PLL synthesizer is started, the PLL synthesizer starts to be started from the same time point b as the design target in FIG. 3A without being influenced by the oscillation stabilization end point of the TCXO earlier than the design target. Therefore, the startup of the PLL synthesizer is not accelerated, and the power consumption of the RS module during standby in the service area does not exceed the design target due to the accelerated startup of the PLL synthesizer.

Also, as described above, in step S8, Psav
e is output and when the PLL synthesizer is started up, the timer 7 is reset (step S9), and the PLL is reset.
It waits until an LD is input (step S10). Then, when the started PLL synthesizer locks up and PLLLD is input from the RF module 1, the measured value of the timer 7 at that time is stored in the register B (step S11), and the timer 7 is reset (step S11). Step S12).

Subsequently, the time from the start of the PLL synthesizer stored in B to the lock-up is subtracted from "t2-B", that is, the time t1 from the start of the PLL synthesizer to the start of reception, and the time difference is obtained. Is stored in ΔB (step S13). Next, the process waits until the value of the timer 7 reset in step S12 becomes ΔB (step S14).
Xon is output to start reception (step S1).
5).

At this time, due to the variation in the accuracy of the TCXO, the time when the PLL synthesizer starts to be started (time b)
If the time from the time t to the lock-up time point (c 'point) is shorter than the design target, the interval between bc' becomes shorter than the design target (between bc 'in FIG. 3A) and "t2- The value of B ″ becomes large, and a large time value is stored in ΔB in step S13 described above. Therefore, in step S14,
After waiting until the timer 7 reaches ΔB, step S
If the reception is started in the process of No. 15, even if the lock-up time of the PLL synthesizer is earlier than the design target, the RF module 1 is not affected by the lock-up time and the time c is the same as the design target of FIG. Start receiving from. Therefore, the start of reception does not start early, and the power consumption of the start of reception during standby in the service area of the RS module does not exceed the design target.

Further, as described above, in step S15, RXo
When n is output and the reception is started, the timer 7 is reset (step S16), and the control waits until the reset value of the timer 7 becomes a time t3 from the start of reception to the end of reception (step S17). ). Then, when the timer 7 measures the time t3, the output of RXon is stopped and the reception is terminated (step S18). Therefore, the time between cd and d from the start of reception to the end of reception with the largest power consumption is t3 as in the case of the design target, and the time between cd and d with the large power consumption is longer than the design target. The inconvenience that the power consumption during the waiting time in the area exceeds the design target is avoided.

In this embodiment, the time t1 from the time point a to the time point b, the time t2 from the time point b to the time point c, and the time t3 from the time point c to the time point d of the design target are stored in the memory in the CPU 8. Although it is stored in advance, a, b, c, and TC with respect to the TCXO operation time t (constant)
Each timing of d is stored, and at the timing of a, T
After starting the oscillation of the CXO, the PLL synthesizer may be forcibly started at the timing of b, the reception may be started at the timing of c, and the reception may be terminated at the timing of d.

[0019]

As described above, according to the present invention, when the time from the start of the oscillation operation of the reference oscillator to the stabilization of the oscillation operation is shorter than a predetermined time, the start of the start of the frequency synthesizer is delayed according to the time difference. In addition, when the time from the start of the frequency synthesizer startup to the lock-up is shorter than a predetermined time, the reception start is delayed according to the time difference. Therefore, due to the variation in accuracy, even if the oscillation operation stabilizes or lock-up occurs quickly, the time accompanied by the increase in power consumption within a certain time does not become relatively long. Therefore, the power consumption during the standby time can be accurately stopped at the design target value without increasing the power consumption within the fixed time.

[0020]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a PHS terminal according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of a CPU according to the embodiment;

3A is a timing chart of a design target of an RF module, FIG. 3B is a timing chart of a case where TCXO oscillation stabilizes early due to variation, and FIG. 3B is a timing chart of a case where lockup of a synthesizer occurs early. It is a timing chart.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 RF module 6 Oscillation stability detector 7 Timer 8 CPU 16 BBIC

Claims (1)

[Claims] 1. A reference oscillator, comprising: a frequency synthesizer for receiving a reference oscillation signal from the reference oscillator and performing local oscillation at a predetermined frequency; operating in a time-division manner; After starting the synthesizer and locking up the local oscillation to a predetermined frequency, in the communication terminal which starts receiving, a first measuring means for measuring a time from the start of the oscillation operation of the reference oscillator to the stabilization of the oscillation operation, When the time measured by the first measuring means is shorter than a predetermined time, a first control means for delaying the start of the frequency synthesizer according to the time difference; and a first control means for delaying the start of the frequency synthesizer from the start of the frequency synthesizer. A second measuring means for measuring a time until lock-up, and a predetermined time measured by the second measuring means. It is shorter than between the communication terminal characterized by comprising a second control means for delaying the reception start in accordance with the time difference.