JPH10200820A - Solid-state imaging device and driving method thereof - Google Patents

Abstract

(57) [Summary] [Problem] Although fixed pattern noise caused by variation in pixel characteristics can be removed, fixed pattern noise in the form of vertical stripes caused by variation in circuit characteristics remains. SOLUTION: In a horizontal blanking period, first,
The sample hold switch 21 and the clamp switch 24s are turned on, the clamp switch 24r is turned off, and the signal level component at the time of light is sampled and held in the capacitor 23s. Then, the sample hold switch 21 and the clamp switch 24r are turned on, and the clamp switch 24s is turned on.
Is turned off and the reference level component in the dark is
Sample hold. Then, during the horizontal effective period, the horizontal selection switches 26s and 26r and the reference switch 22 are sequentially turned on for each column, and the signal components sampled and held by the capacitors 23s and 23r are read out to the horizontal signal lines 15s and 15r.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device and a method of driving the same, and more particularly, to an amplifying solid-state imaging device in which a pixel itself has an amplifying function and outputs a pixel signal as a voltage and a method of driving the same.

[0002]

2. Description of the Related Art As an amplification type solid-state imaging device, BASI is used.
S (Base Stored Image Senser), BCMD (Bulk Charge
Modulation Device), CMOS APS (Active Pixel
l Sensor) is known. In these amplifying solid-state imaging devices, the pixels are configured using active elements such as MOS structures in order to provide the pixels themselves with an amplifying function. Therefore, characteristics of the active elements (threshold voltage Vth, etc.)
The variation of the above comes directly on the image signal. Since this characteristic variation has a fixed value for each pixel, a fixed pattern noise (FPN; Fixed Pater
n Noise).

FIG. 8 shows a conventional example of an amplification type solid-state imaging device for removing fixed pattern noise caused by the characteristic variation of the pixel. In the figure, a large number of pixels 101 arranged in a matrix have output terminals connected to a vertical signal line 102 in column units. Then, each vertical signal line 102
A vertical output circuit 103 for reading out the signal of each pixel 101 is connected to one end of each column. FIG. 8 shows only a specific circuit configuration of the vertical output circuit 103 in a certain column.

In the vertical output circuit 103, one end of a vertical signal line 102 is connected to one end of each of sample-and-hold switches 104s and 104r formed of Nch MOS transistors. Further, a switch 105 composed of an Nch MOS transistor is connected between one end of the vertical signal line 102 and the reference potential VSS. N is connected between the other ends of the sample and hold switches 104s and 104r.
Switch 105s, 1 composed of a chMOS transistor
06, 105r are connected in series.

[0005] The sample and hold switches 104s, 10s
4r between each other end and the reference potential VSS.
07s and 107r are connected. Pc is further connected to the other ends of the sample and hold switches 104s and 104r.
Source follower 108 composed of hMOS transistor
The gates of s and 108r are connected. One end of each of the source followers 108s and 108r is connected to the reference potential VS.
S, the other end thereof and two horizontal signal lines 110
s and 110r are connected to horizontal selection switches 109s and 109r formed of Pch MOS transistors.

Next, a circuit operation for removing fixed pattern noise in the conventional device having the above configuration will be described.

In a horizontal blanking period, when a row is selected by vertical scanning, a signal component (hereinafter, referred to as a signal level component) of the pixels 101 in the selected row at the time of light before the pixel reset is performed and a pixel reset is performed. The later dark signal components (hereinafter referred to as reference level components) are sequentially sampled by the sample and hold switches 104s and 104r, and are held by the capacitors 107s and 107r.

Next, during a horizontal effective period, a certain column is selected by horizontal scanning, and the horizontal selection switches 109s and 109r of the selected column are turned on, thereby turning on the signal levels held by the capacitors 107s and 107r. The component and the reference level component are
s, 110r, and further read out by the horizontal output circuit 111.
Is output to an external circuit via Then, by taking the difference between the two outputs in the external circuit, the noise component that is common to both the outputs is canceled. As a result, a signal from which fixed pattern noise caused by characteristic variations such as the threshold voltage Vth of the pixel 101 is removed can be obtained.

[0009]

However, in the conventional amplification type solid-state imaging device described above, fixed pattern noise caused by variation in characteristics of the pixel 101 can be removed, but the vertical signal line 102 and the horizontal signal line 110s,
Since the signal level component and the reference level component are sampled and held by separate sample and hold switches 104s and 104r in the vertical output circuit 103 between the sample and hold switches 104s and 10r.
The switching noise of 4r causes offset noise, and when this noise component differs between columns due to variations in circuit characteristics, it appears as a vertical streak-shaped fixed pattern noise on the screen.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide not only fixed pattern noise due to variation in pixel characteristics but also vertical streak due to variation in circuit characteristics. An object of the present invention is to provide a solid-state imaging device capable of suppressing fixed pattern noise and a driving method thereof.

[0011]

In the solid-state imaging device according to the present invention, one end is connected to a plurality of pixels arranged in a matrix and a vertical signal line to which each output end of each pixel is connected in a column unit. A first switch, a second switch connected between the other end of the first switch and a reference potential point, and one end commonly connected to the other end of the first switch. First and second power storage means, third and fourth switch means connected between the other end of each of these power storage means and a reference potential point, and each of the first and second power storage means. Fifth and sixth connected between the other end and the first and second horizontal signal lines
And switch means for each column.

In the driving method according to the present invention, in driving the solid-state imaging device having the above-described configuration, first, in the horizontal blanking period, the first switch and the third switch are turned on and the fourth switch is turned off. The signal level component (the signal component at the time of light) is sampled and held by the first power storage means, and then the first switch means and the fourth switch means are turned on, and the third switch means is turned off to set the reference level. The component (signal component at the time of darkness) is sampled and held in the second power storage means, and then, during the horizontal effective period, the fifth and sixth switch means and the second switch means are sequentially turned on for each column, and First, the bright and dark signal components sampled and held by the second power storage means are read out to the first and second horizontal signal lines.

In the solid-state imaging device having the above-described configuration and the driving method thereof, first, in the horizontal blanking period, the first
, The signal level component is sampled, the third switch is turned on, the fourth switch is turned off, and the output end of the first power storage is set to the reference potential, whereby the first power storage is set. Hold on. At this time, a noise component accompanying the switching of the first switch means gets on the first power storage means. Subsequently, in the same manner, the first
Sampling the reference level component, turning on the fourth switch means, turning off the third switch means, and setting the output terminal of the second power storage means to the reference potential, thereby obtaining the second power storage means. Hold on. Again,
A noise component accompanying the switching of the first switch means comes into the second power storage means.

Next, in the horizontal effective period, the fifth and sixth switch means are sequentially turned on for each column to perform horizontal selection, and at the same time, the second switch means is turned on, and the first and second switch means are turned on.
By setting each input terminal of the power storage means as a reference potential,
The signal level component and the reference level component sampled and held by the second power storage means are read out to the first and second horizontal signal lines. At this time, the signal level component and the reference level component share a noise component accompanying the switching of the first switch means. Therefore, the noise component accompanying the switching of the first switch means is canceled by taking the difference between the signal level component and the reference level component in the subsequent circuit. As a result, it is possible to suppress not only the fixed pattern noise due to the variation in the characteristics of the pixels but also the fixed pattern noise in the form of vertical stripes due to the variation in the characteristics of the circuit.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention. In FIG. 1, a large number of pixels (pixels) 11 are arranged in a matrix, and the output terminals of these pixels 11 are connected to vertical signal lines 12-1 to 12-n in column units.
From each of the pixels 11, a signal is applied as a voltage to the vertical signal line 1.
Output to 2-1 to 12-n. Vertical signal lines 12-1 to 12-n
Are connected to vertical output circuits 13-1 to 13-n which output a signal level component and a reference level component for each column.

Each of the vertical output circuits 13-1 to 13-n has:
Column select signals Col (1) to Col (n) from the horizontal shift register 14
And the reference signals Ref (1) to Ref (1)
(n) and clamp signals Clamp S (1) to Clamp S (n), Clamp
R (1) to Clamp R (n) are provided for each column. These timing signals are generated by the horizontal shift register 14 or another timing generation circuit (not shown). The signal level components and the reference level components output from the vertical output circuits 13-1 to 13-n are two horizontal signal lines 15s,
The signal is supplied to the horizontal output circuit 16 via 15r.

FIG. 2 shows a specific circuit configuration of the vertical output circuit 13-i and the horizontal output circuit 16 in the i-th column. First, in the vertical output circuit 13-i, one end of a sample / hold switch 21 composed of an NchMOS transistor is connected to one end of a vertical signal line 12-i. A sample hold signal SH is applied to the gate of the sample hold switch 21. A reference switch 22 composed of an Nch MOS transistor is connected between the other end of the sample hold switch 21 and the reference potential Vref. The reference signal Ref is applied to the gate of the reference switch 22.

The other end of the sample and hold switch 21 is further provided with a capacitor 23 as first and second storage means.
r and 23s are connected at one end. Capacitor 23
r, 23s between each other end and the reference potential Vref.
Clamp switch 24 composed of a chMOS transistor
r and 24s are connected. Each of the gates of the clamp switches 24r and 24s has a clamp signal Clamp R
, Clamp S are applied respectively.

The other ends of the capacitors 23r and 23s are further connected to respective gates of source followers 25r and 25s formed of Pch MOS transistors. The drains of the source followers 25r and 25s are connected to the negative power supply VSS. Source follower 25r, 2
Each source of 5s is connected to each drain of horizontal selection switches 26r and 26s composed of PchMOS transistors. A column selection signal Col is applied to each gate of the horizontal selection switches 26r and 26s. The sources of the horizontal selection switches 26r and 26s are connected to the horizontal signal line 15
r, 15s.

Subsequently, in the horizontal output circuit 15, one end of each of the horizontal signal lines 15r, 15s is connected to a capacitor 27r,
One end of each of the 27s is connected. A switch 28 composed of a PchMOS transistor is provided between one end of each of the capacitors 27r and 27s and the positive power supply VDD.
r and 28s are connected. Also, the capacitor 27
r, 27s between each other end and the reference potential Vref.
Clamp switch 29 composed of a chMOS transistor
r, 29s are connected.

The other ends of the capacitors 27r and 27s are further provided with input terminals of the source follower circuits 30r and 30s, respectively.
That is, the gates of the drive transistors 31r and 31s formed of NchMOS transistors are connected. The drains of the drive transistors 31r and 31s are connected to the positive power supply VD.
D, and each source is connected to the negative power supply VSS via load transistors 32r and 32s composed of Nch MOS transistors. The sources of the driving transistors 31r and 31s are connected to the output terminals 33r and 33s.

Next, the vertical output circuits 13-1 to 13-1 having the above configuration
The circuit operation of the 3-n and horizontal output circuit 16 is shown in FIG.
The operation will be described with reference to the timing chart of FIG.

In FIG. 4, VsigS is a signal level component of the pixel 11, and VsigR is a reference level component of the pixel 11. vsh is the offset noise associated with the switching of the sample and hold switch 21, vclampS is the offset noise associated with the switching of the clamp switch 24s, and vclampR is the offset noise associated with the switching of the clamp switch 24r. g-sfc is the gain of the source followers 25s and 25r of the vertical output circuit 13,
g-sfC is the source follower 30s, 3 of the horizontal output circuit 16.
The gain is 0r. sf-offset-Sc is the vertical output circuit 13
Offset of the source follower 25s for the signal level of
sf-offset-Rc is the offset of the source follower 25r for the reference level of the vertical output circuit 13, sf-offset-SC is the offset of the source follower 30s for the signal level of the horizontal output circuit 16, and sf-offset-RC is the horizontal output. This is the offset of the source follower 30r for the reference level of the circuit 16.

In the horizontal blanking period HBLK,
The sample-and-hold signal SH becomes “H” level, and in synchronization with this, the clamp signals Clamp S (1), Clamp S (2),
...... becomes "H" level, and clamp signals Clamp R (1), Clam
When pR (2),... becomes “L” level (time t1), the sample hold switch 21 and the clamp switch 2
4s is on and the clamp switch 24r is off, so that the signal level component VsigS of the pixel 11 is
s is sampled and held.

At this time, as is apparent from FIG.
The sample hold switch 21 is turned off first, and then the clamp switch 24s is turned off (time t2). With such a phase relationship, noise (hereinafter, referred to as switching noise) accompanying the switching of the sample-and-hold switch 21 rides on the capacitor 23s, but the switching noise of the clamp switch 24s affects the output of the capacitor 23s. Assuming that the parasitic capacitance at the end is Co / the capacitance of the capacitor 23s is C, the parasitic capacitance is Co / C, so that there is almost no effect. The period from time t1 to time t2 is a period during which the signal level component VsigS of the pixel 11 is sampled and held.

Similarly, the sample-and-hold signal SH becomes "H" level, and in synchronization with this, the clamp signals Clamp R (1), Clamp R (2),. When the clamp signals Clamp S (1), Clamp S (2),... Become “L” level (time t3), the sample hold switch 2
1 and the clamp switch 24r are turned on and the clamp switch 24s is turned off, so that the reference level component VsigR of the pixel 11 is sampled and held by the capacitor 23r.

When the sample level of the reference level component VsigR is sampled and held, similarly to the case of sampling and holding the signal level component VsigS (see FIG. 5A), the sample hold switch 21 is turned off first and then clamped. The switch 24r is turned off (time t4). The period from time t3 to time t4 corresponds to the reference level component V of the pixel 11.
This is the period during which sigR is sampled and held.

Subsequently, the vertical output circuits 13-1 to 13 of each column
Shift to operation for reading signal from -n. In the horizontal effective period, first, the column selection signal Col (1) of the first column goes to “L” level, and the vertical output circuit 13-1 of the first column is selected. Horizontal selection switch 2
6s and 26r are turned on (time t5). At this time, 1
The reference signal Ref (1) in the column becomes “H” level,
The reference switch 22 is turned on. As a result, the signal level component VsigS and the reference level component Vsi sampled and held by the capacitors 23s and 23r are obtained.
gR is applied to the horizontal signal lines 15s, 15r via the source followers 25s, 25r and the horizontal selection switches 26s, 26r.
Is output to

Then, the clamp signal Clamp which has been in the "H" level transitions to the "L" level and the clamp switches 29s and 29r are turned off, so that the signal level component VsigS and the reference level component VsigR are changed. The sample is held by the capacitors 27s and 27r. At this time, the PMOSs constituting the source followers 25s and 25r
Offset variations due to Vth variations of the transistors are simultaneously sampled and held by the capacitors 27s and 27r. Then, the clamp signal Clamp S of the first column
(1), Clamp R (1) transitions to the “H” level, and the clamp switches 24 s and 24 r are turned on, thereby outputting offset variations of the source followers 25 s and 25 r (time t 6).

In order to prevent the data sampled and held by the capacitors 23s and 23r from being destroyed before reading, the reference switch 22 and the clamp switches 24s and 24r connected to both ends of the capacitors 23s and 23r are connected. It is necessary not to turn on at the same time. That is, as is apparent from FIG. 5B, after the reference signal Ref (i) is set to “L” level, the clamp signals ClampS (i) and Clamp R (i) are changed to “H” level. Just do it.

As described above, first, the capacitors 23s,
After outputting the signal level component VsigS and the reference level component VsigR sampled and held at 23r, and subsequently outputting the offset variation components of the source followers 25s and 25r, both output terminals 33s and 33s of the horizontal output circuit 16 are output.
The voltage between 33r is g-sfC * g-sfc (VsigS-VsigR) + (sf-offset-SC) + (sf-offset-RC) (1).

That is, the sample hold switch 21
The offset noise vsh due to the switching of the signal level system and the reference level system are offset, and the signal level component V
A vertical output circuit 1 is added to the difference between sigS and the reference level component VsigR.
3, the source followers 25s and 25r gain g-sfc and the horizontal CCD 5 power output circuit 16 source follower 30
Since a signal obtained by multiplying the gain g-sfC of s and 30r is output, it is possible to suppress a fixed pattern noise caused by a variation in offset caused by switching of the sample and hold switch 21. In the expression (1), since (sf-offset-SC) + (sf-offset-RC) is an offset of the horizontal output circuit 16 on which signals of all pixels are taken, it does not become fixed pattern noise. .

FIG. 6 is a schematic configuration diagram showing another embodiment of the present invention. In FIG. 6, a large number of pixels (pixels) 51 are arranged in a matrix, and the output terminals of the pixels 51 are connected to the vertical signal lines 52-1 to 52-n in column units. From each of the pixels 51, a signal is output as a voltage to the vertical signal lines 52-1 to 52-n. Vertical signal lines 52-1 to 5-5
Vertical outputs 53-1 to 53-n that output signal level components and reference level components for each column are connected to each end of 2-n.

Each of the vertical output circuits 53-1 to 53-n has:
Column select signals Col (1) to Col (n) from the horizontal shift register 54
And a reference signal Ref and clamp signals Clamp S and Clamp R generated by, for example, a pulse generation circuit (not shown) are commonly provided to each column. The signal level components and the reference level components output from the vertical output circuits 53-1 to 53-n are two horizontal signal lines 55s,
The signal is supplied to the horizontal output circuit 56 via the line 55r.

The difference between the present embodiment having the above configuration and the previous embodiment is that, in the above embodiment, the reference signals Ref (1) to Ref (1)
Ref (n) and clamp signals Clamp S (1) to Clamp S (n), Cl
While ampR (1) to Clamp R (n) are given independently for each column, in the present embodiment, the reference signal
Ref and clamp signals Clamp S and Clamp R are commonly applied to each column. As the vertical output circuits 53-1 to 53-n and the horizontal output circuit 56, those having the same circuit configurations as those of the previous embodiment shown in FIG. 2 are used.

FIG. 7 shows a timing chart according to this embodiment. Basic circuit operations of the vertical output circuits 53-1 to 53-n and the horizontal output circuit 56 are the same as those in the previous embodiment. However, as described above, since the reference signal Ref and the clamp signals Clamp S and R are common to each column, the capacitors 23 in the non-selected columns are not read.
s, 23r (see FIG. 2) to prevent the data sampled and held from being destroyed.
f and the clamp signals Clamp S and R need to have the phase relationship shown in FIG.

That is, at time t7, after the clamp signal Clamp S, R first transitions to the “L” level, the reference signal Ref transitions to the “H” level, thereby connecting to both ends of the capacitors 23s, 23r. Reference switch 22 and clamp switches 24s, 24r
Are not turned on at the same time, the destruction of the contents held by the capacitors 23s and 23r in the columns not selected for reading can be reliably prevented.

In the first embodiment, the reference signals Ref (1) to Ref (n) and the clamp signal Clamp S (1)
Since Clamp S (n) and Clamp R (1) to Clamp R (n) are independent of each column, and after reading (time t7), the data may be destroyed, the reference signal Ref (1) to Ref (n) and clamp signal Clamp S (1) to Clamp S (n), Clamp R (1) to Clam
The phase relationship of p R (n) is not strict, and as shown in FIG. 5B, the transition of the clamp signal Clamp S, R (i) in the i-th column to the “L” level and the reference signal Ref in the i + 1-th column The transition to the “H” level of (i + 1) may be the same timing.

Also in the case of the present embodiment, similarly to the case of the previous embodiment, it is possible to suppress the fixed pattern noise caused by the offset characteristic variation caused by the switching of the sample and hold switch 21. In addition, since the reference signal Ref and the clamp signals Clamp S and R are common to each column, the wiring system for each of the vertical output circuits 53-1 to 53-n is different from the previous embodiment in which each column is independent. There is an advantage that the configuration can be simplified.

[0041]

As described above, according to the present invention,
In an amplification type solid-state imaging device, a sample-and-hold switch in a vertical output circuit provided for each column is shared by a signal level component at the time of light and a reference level component at the time of darkness, and an offset characteristic accompanying the switching of the sample-hold switch is provided. Since the noise is applied to both the signal level component and the reference level component in the same manner, the noise component can be canceled when a difference between the signal level component and the reference level component is obtained by a subsequent circuit. It is possible to suppress not only the fixed pattern noise due to the characteristic variation but also the vertical streak-shaped fixed pattern noise due to the characteristic variation of the circuit.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of a vertical output circuit and a horizontal output circuit.

FIG. 3 is a timing chart according to one embodiment.

FIG. 4 is an operation explanatory diagram according to one embodiment.

FIG. 5 is a timing chart for supplementary explanation.

FIG. 6 is a schematic configuration diagram showing another embodiment of the present invention.

FIG. 7 is a timing chart according to another embodiment.

FIG. 8 is a circuit diagram showing a conventional example.

[Explanation of symbols]

11, 51 pixels 12-1 to 12-n, 52-1 to 52-n
Vertical signal lines 13-1 to 13-n, 53-1 to 53-n Vertical output circuits 14, 54 Horizontal shift registers 15r, 15s, 55r, 55s Horizontal signal lines 16, 56 Horizontal output circuits

Claims (6)

[Claims] 1. A plurality of pixels arranged in a matrix, a first switch means having one end connected to a vertical signal line connected to each output end of the plurality of pixels in a column unit, and Second switch means connected between the other end of the switch means and a reference potential point; and first and second power storage means each having one end commonly connected to the other end of the first switch means. And third and fourth switch means respectively connected between each other end of the first and second power storage means and a reference potential point; and each other end of the first and second power storage means And a fifth and a sixth switch means connected between the first and second horizontal signal lines for each column. 2. A plurality of pixels arranged in a matrix, a first switch means having one end connected to a vertical signal line to which each output end of the plurality of pixels is connected in column units, and Second switch means connected between the other end of the switch means and the reference potential point; and first and second power storage means each having one end commonly connected to the other end of the first switch means. And third and fourth switch means respectively connected between the other ends of the first and second power storage means and a reference potential point, and the other ends of the first and second power storage means, respectively. A driving method for a solid-state imaging device comprising, for each column, a fifth and a sixth switch means connected between the first and second horizontal signal lines. , The first switch means and the third switch means are turned on, and the fourth switch means is turned on. Then, the signal component at the time of light is sampled and held in the first power storage means, and then the first switch means and the fourth switch means are turned on, and the third switch means is turned off. The signal component is sampled and held in the second power storage means. Next, during the horizontal effective period, the fifth and fifth signals are sequentially output for each column.
The sixth switch means and the second switch means are turned on, and the bright and dark signal components sampled and held by the first and second power storage means are converted into the first and second horizontal signals. A method for driving a solid-state imaging device, comprising: reading data to a line. 3. When the first switch means and the third and fourth switch means are turned off, the third and fourth switch means are turned off after the first switch means is turned off. 3. The driving method for a solid-state imaging device according to claim 2, wherein: 4. The method according to claim 2, wherein the third and fourth switch units are turned on after the second switch unit is turned off. 5. The method of driving a solid-state imaging device according to claim 2, wherein timing signals for driving said second switch means and said third and fourth switch means are given independently for each column. 6. The driving method for a solid-state imaging device according to claim 2, wherein timing signals for driving said second switch means and said third and fourth switch means are applied to each column in common.