JPH10201093A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device capable of simultaneously realizing low power consumption and high speed without changing a power supply voltage, and also suppressing a leakage current during non-operation. To provide. An absolute value of a threshold voltage, which is connected between an externally supplied power supply and a ground and an internal circuit, is a threshold of an N-type MOS transistor and a P-type MOS transistor constituting an internal circuit. An N-type MOS transistor and a P-type MOS transistor larger than the value voltage electrically connect an externally supplied power supply and ground to an internal circuit during normal operation, and provide an externally supplied power supply and ground during standby. The above problem is solved by electrically disconnecting the internal circuit from the internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to low power consumption and high speed operation of a semiconductor device.

[0002]

2. Description of the Related Art For example, in a battery-powered product such as a mobile phone, there is a demand to reduce power consumption in order to extend a driving time. Regardless of battery-driven products, recent advances in semiconductor manufacturing technology have led to the development of highly integrated large-scale semiconductor devices, in which the amount of heat generated increases in accordance with the circuit scale, and expensive packages with good heat dissipation are used. There is a universal demand to reduce power consumption because it is a factor of cost generation, such as the need to use and cool by providing heat radiation fins.

On the other hand, lowering the power supply voltage makes it possible to achieve low power consumption. However, when the power supply voltage is reduced, the operation speed is reduced accordingly. By further reducing the threshold voltage of the transistor, for example, the current 5 V or 3.3 V
V power supply voltage to 1.5V or 1V, for example, 3.
A semiconductor device capable of reducing power consumption and increasing speed by reducing the threshold voltage of an N-type MOS transistor of about 0.7 V to about 0.1 V in the case of a power supply voltage of 3 V has been proposed.

In the above-described technology for reducing power consumption, the power consumption P is calculated by the following formula in the case of a CMOS semiconductor device, for example. Power consumption P = fcV ² Here, f is the operating frequency, c is the load capacity, and V is the power supply voltage. By reducing the power supply voltage, the power consumption can be reduced by the square, which is the most effective. In addition, power consumption of the semiconductor device can be reduced.

Further, there is an advantage that the operation can be performed at a very high speed by reducing the threshold voltage of the transistor. However, in a semiconductor device in which the threshold voltage of a transistor is lowered, the transistor cannot be completely turned off during standby,
Since the leakage current due to the transistor in the off state becomes extremely large, there is a problem that the leakage current at the time of standby increases as compared with a normal CMOS semiconductor device.

[0006] On the other hand, for example, in "Nikkei Micro Device" of August 1996, Vth which makes a threshold voltage of a transistor variable by controlling a substrate voltage is disclosed.
There have been proposed T-CMOS semiconductor devices and MT-CMOS semiconductor devices in which transistors having different threshold voltages are mounted on the same chip depending on the process. Hereinafter, the above-described two semiconductor devices disclosed in “Nikkei Microdevice” will be described.

First, FIG. 3 shows a configuration circuit diagram of an example of a VT-CMOS semiconductor device. This semiconductor device 20 has P
MOS transistor (hereinafter referred to as PMOS) 22 and N-type MOS transistor (hereinafter referred to as NMOS)
24 and a VT circuit 26.

Here, a PMOS 22 and an NMOS 24
Shows an inverter as an example of an internal circuit.
The sources are connected to a power supply (V _DD ) and the ground (GND), respectively. The gates and the drains are short-circuited, respectively, and the substrate (or well) is connected to the VT circuit 26. Also, the VT circuit 26
Controls the substrate voltage (or well voltage) of the PMOS 22 and NMOS 24 of the internal circuit.

In the semiconductor device 20, during normal operation, the substrate voltages of the PMOS 22 and the NMOS 24 are respectively set to the power supply voltage and the ground voltage by the VT circuit 26, for example, 1V of the power supply voltage and 0V of the ground voltage, respectively. . At this time, the threshold voltages (variable V _th ) of the PMOS 22 and the NMOS 24 are, for example, −0.1 V and 0.1 V, respectively, and the power supply voltage is 1 V.
Despite being reduced to V, high-speed operation is possible.

On the other hand, during standby, the VT circuit 2
6, the substrate voltage of the PMOS 22 becomes higher than the power supply voltage, and the substrate voltage of the NMOS 24 becomes lower than the ground voltage. At this time, the absolute values of the threshold voltages of the PMOS 22 and the NMOS 24 increase due to the substrate bias effect, and the PMOS 22 or the NMOS
Since S24 can be completely turned off, leakage current due to the PMOS 22 or NMOS 24 during standby can be reduced.

FIG. 4 is a circuit diagram showing an example of an MT-CMOS semiconductor device. This semiconductor device 28
As in the case of the semiconductor device 20, the PMOS 30 and the NMOS 3 forming an inverter as an example of an internal circuit
2 and an NMOS 34 serving as a switch transistor.

The PMOS 30 and the NMOS 32 have relatively low threshold voltages (low V _th ). The sources are connected to the power supply and the drain of the NMOS 34, respectively, and the gates and the drains are short-circuited. The substrate (or well) is connected to a power supply and a ground, respectively. In addition, NMOS3
Numeral 4 has a relatively high threshold voltage (high V _th ), and its source and substrate are connected to ground.

In the semiconductor device 28, during normal operation, the NMOS 34 is turned on, and the PMOS 30 and the NMOS 32 operate at high speed with the drain of the NMOS 34 as a virtual ground because the threshold voltage is low even under a low power supply voltage. I do. On the other hand, during standby, NM
OS 34 is turned off, and PMOS 30 and NMO
The leakage current flowing through S32 is cut off by the NMOS 34 of the switch transistor, and the leakage current during standby is reduced.

The above-described semiconductor devices 20 and 28 have attracted attention as semiconductor devices using the latest technology capable of simultaneously realizing low power consumption and high speed. However, since it is necessary to supply a low power supply voltage different from the conventional power supply voltage to these semiconductor devices 20 and 28, a plurality of types of power supply voltages are prepared on one board.
There is a problem that a plurality of types of semiconductor devices having different power supply voltages must be mixed and mounted.

For example, a semiconductor device manufactured by a process of 0.6 μm or more uses a power supply voltage of 5 V, and a semiconductor device manufactured by a process of 0.5 μm or less requires a power supply voltage of 3.3 V. I'm using Even now, 1
On a single board, semiconductor devices using these 5 V and 3.3 V power supply voltages are mixed and mounted.
In addition to this, when various types of power supply voltages such as 2.5 V, 1.5 V, and 1 V are used, there is a problem that it is very difficult to use.

[0016]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems based on the above-mentioned prior art, and it is not necessary to change the power supply voltage, so that low power consumption and high speed can be realized at the same time. Another object of the present invention is to provide a semiconductor device capable of suppressing a leakage current during non-operation.

[0017]

In order to achieve the above-mentioned object, the present invention provides a power supply and a ground which are connected between an external circuit and an internal circuit.
An N-type MOS transistor and a P-type transistor for electrically connecting the externally supplied power and ground to the internal circuit, and for electrically disconnecting the externally supplied power and ground from the internal circuit during standby Type MO
An absolute value of a threshold voltage of the N-type MOS transistor and the P-type MOS transistor is larger than threshold voltages of the N-type MOS transistor and the P-type MOS transistor forming the internal circuit. A semiconductor device is provided.

Here, the N-type MOS transistor is
It is preferable that the P-type MOS transistor be connected between the externally supplied power supply and the internal circuit, and that the P-type MOS transistor be connected between the internal circuit and the externally supplied ground.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIGS. 1A and 1B are conceptual diagrams of an embodiment of the semiconductor device according to the present invention during normal operation and during standby, respectively. As shown in these figures, the semiconductor device 10 of the present invention includes, in the illustrated example, an N-type MOS transistor (hereinafter, referred to as NMOS) 12 and a P-type MOS transistor (hereinafter, referred to as PMOS) 14 which are switch transistors. , A PMOS 16 and an NMOS 18 as an example of an internal circuit.

The NMOS 12 and the PMOS 14 electrically connect an externally supplied power supply and ground to the internal circuit of the semiconductor device 10 during normal operation, and conversely, an externally supplied power supply during standby. And a switch transistor for electrically disconnecting the ground and the internal circuit of the semiconductor device 10 from each other.
And has a relatively higher threshold voltage than the NMOS 18.

The PMOS 16 and the NMOS 18
Is an inverter as a typical example of the internal circuit of the semiconductor device 10, and has a relatively lower threshold value than the above-described switch transistors NMOS12 and PMOS14. Here, FIG.
As shown in (c), NM of the switch transistor
OS12 and PMOS 14 and P of internal circuit
The threshold voltages of the MOS 16 and the NMOS 18 are set to about 0.7 V and about -0.7 V, respectively, and
0.1V and about 0.1V.

The switch transistor NMOS1
2 and PMOS 14 have a threshold voltage of NMOS 12
And the PMOS 14 can be completely turned off, as long as the leakage current during standby by the PMOS 16 and the NMOS 18 of the internal circuit can be reduced. Also, the PMOS 16 and N of the internal circuit
The threshold voltage of the MOS 18 is not particularly limited, and is preferably as low as possible within a range in which a logical operation can be performed.

Here, the NMOS 12 and the PMOS 14
Are connected to a power supply and a ground supplied from the outside, respectively, and their sources are supplied to an internal circuit, that is, a source of a PMOS 16 and an NMOS 18 in the illustrated example, as an internal power supply and an internal ground, respectively. The gates of the PMOS 16 and the NMOS 18 are short-circuited to be input to the inverter, and their drains are also short-circuited to be output from the inverter.

The semiconductor device 10 of the present invention is supplied with the same power supply voltage as the conventional one, for example, a power supply voltage of 5 V or 3.3 V which is mainly used at present. This does not necessarily mean that the power supply voltage of 5 V or 3.3 V is used, but does not lower the power supply voltage as compared with the conventional semiconductor device using the power supply voltage of 5 V or 3.3 V. For example, the same power supply voltage as that of the peripheral semiconductor devices used simultaneously on the board is supplied.

Thus, in the semiconductor device 10 of the present invention, there is an advantage that it is not necessary to change the power supply voltage, and the trouble of preparing a special power supply voltage only for the semiconductor device 10 of the present invention can be omitted.

The switch transistor NMOS1
2 and the PMOS 14 are turned on during normal operation and turned off during standby. That is, NM
As shown in FIG. 1A, the gates of the OS 12 and the PMOS 14 are set to the power and ground potentials supplied from outside during normal operation, respectively, and conversely, as shown in FIG. 1B. So, during standby,
These are the ground and power supply potentials supplied from outside.

The switch transistor NMO
The signal for controlling the ON state and the OFF state of S12 and the PMOS 14, that is, the signal for switching the normal operation and the standby state of the semiconductor device 10 may be supplied from outside the semiconductor device 10, for example, or A circuit for detecting the operation state of the semiconductor device 10 may be provided inside the semiconductor device 10, and switching may be performed using a detection signal generated by the detection circuit.

In the illustrated example of the semiconductor device 10, the PM constituting an inverter as an example of an internal circuit is provided.
Although only the OS 16 and the NMOS 18 are shown, the PMOS 12 and the NMO
S14 only needs to have a transistor size capable of supplying a necessary amount of current, and may be provided for each basic gate or macro cell constituting an internal circuit, or may be provided for a plurality of basic gates or It may be provided commonly to the macro cells.

The semiconductor device 10 of the present invention basically has such a configuration. Next, the semiconductor device 10 of the present invention
Will be described.

FIGS. 2A and 2B are a conceptual diagram of an embodiment of the semiconductor device of the present invention in a normal operation and an operation timing chart of the embodiment, respectively. The semiconductor device 10 of FIG. 2A shows an equivalent circuit for logic simulation of the semiconductor device 10 in the normal operation shown in FIG. 1A, and an input signal V _IN is applied to an inverter of an internal circuit. Input and output signal V from the inverter.
_OUT is output, and a load capacity c is added to this output.

First, in the semiconductor device 10 of the present invention,
During normal operation, the switching transistor PMOS
12 and NMOS 14 are turned on.
A power supply and a ground externally supplied via the MOS 12 and the NMOS 14 and a PM of an internal circuit, respectively.
The OS 16 and the source of the NMOS 18 are electrically connected. Thus, the output signal V _OUT of the inverter of the internal circuit changes according to the change of the input signal V _IN .

At this time, the internal power supply voltage V _A supplied to the internal circuit is: Internal power supply voltage V _A = V _DD -V _TN -V _rN where V _DD is the external power supply voltage V _TN. , NMOS 12 is a voltage drop due to the _body effect of the NMOS 12.

Similarly, the internal ground voltage V _B supplied to the internal circuit is: internal ground voltage V _B = GND−V _TP −V _rP where GND is the ground voltage V _TP supplied from the outside and PMOS 14 is threshold voltage V _rP of a voltage rise due to the substrate bias effect of the PMOS 14.

Therefore, in the semiconductor device 10 of the present invention,
Is the power supply voltage V supplied from the outside _DDAnd ground
Switch transistor NMOS based on the voltage GND
12 and the threshold voltage V of the PMOS 14_TN, V_TPAnd
And voltage V due to substrate bias effect_rN, V_rPDepending on the
Unit power supply voltage V_AAnd internal ground voltage V_BOccurs
The inverter in the internal circuit operates according to the timing shown in FIG.
As shown in the chart, this internal power supply voltage V_AWithin
Section ground voltage V_BIt operates within the amplitude range of

Here, in the semiconductor device 10 of the present invention, the power consumption P of the internal circuit is calculated by the following formula in the case of a CMOS semiconductor device, for example. Here the power consumption _{P = fc (V A -V B} ) 2, f is the operating frequency c is load capacitance V _A and V _B are respectively the internal power supply voltage and the internal ground voltage

For example, here, the threshold voltages V _TN and V _TP of the switch transistors NMOS 12 and PMOS 14 are set to 0.7 V and −0.7 V, respectively, and the drop voltage V _rN and the rise voltage V due to the substrate bias effect are set. _Assuming that _rP is 0.5 V and -0.5 V, the power consumption P of the internal circuit is as follows. Power consumption P = fc {(V _DD −V _TN −V _rN ) − (GND−V _TP −V _rN )} ² = fc × 0.9 ²

Actually, the power consumption by the NMOS 12 and the PMOS 14 of the switch transistor is added to the power consumption P of the above-described internal circuit, and the current I = fcV
= If fc (V _A -V _B), the total power consumption P _R (P =
IV) the total power _{P R = fc (V A -V} B) 2 + fc (V A -
V _B ) {(V _DD −V _A ) + (V _B −GND)}.

[0039] Similarly, for example, supplied from an external power supply voltage V _DD and the ground voltage GND to 3.3V and 0V respectively, total power consumption P _R is as follows. Total power consumption P _R = fc × 0.9 ² + fc ( _VA− V _B ) Ｖ (V _DD −V _A ) + (V _B −GND)｝ = fc × 0.9 ² + fc (2.1-1) .2) {(3.3-2.1) + (1.2-0)} = fc × 2.97

Therefore, the power consumption of the internal circuit of the semiconductor device 10 of the present invention is as follows as compared with a conventional semiconductor device using the same power supply voltage of 3.3 V, for example. 0.9 ² /3.3 ² <1/10 The total power consumption of the semiconductor device 10 of the present invention is similarly as follows. 2.97 / 3.3 ² <1 / 3.67 That is, according to the semiconductor device 10 of the present invention, the conventional semiconductor device using the same power supply voltage of 3.3 V can be used without changing the power supply voltage. In comparison, the power consumption of the internal circuit
It can be reduced to less than 1/10, and the total power consumption is 3.6
It can be reduced to 1/7 or less.

As described above, in the semiconductor device 10 of the present invention, the internal power supply voltage _VA and the internal power supply voltage are controlled by the switch transistors NMOS 12 and PMOS 14 without changing the externally supplied power supply voltage V _DD and ground voltage GND. generates a ground voltage V _B, since the internal circuit is operated in the amplitude range of the internal power supply voltage V _a ~ internal ground voltage V _B, it is effective in the square to reduce power consumption, effectively a semiconductor device 10 can be reduced in power consumption.

In the semiconductor device 10 of the present invention,
Since the threshold voltages of the PMOS 16 and NMOS 18 of the internal circuit are relatively lower than those of the switch transistors NMOS 12 and PMOS 14, for example, the threshold voltages of the PMOS 16 and NMOS 18 of the internal circuit are −0.1 V and −0.1 V, respectively. Since the voltage is set to 0.1 V, it is possible to operate at sufficiently high speed even if the amplitude range of the internal power supply voltage V _A to the internal ground voltage V _B is only 0.9 V.

On the contrary, as shown in FIG. 1B, when the semiconductor device 10 of the present invention is on standby, the PMOS transistors 12 and NMOS 1 which are switch transistors
4 is turned off, and these PMOS 12 and NM
The power and ground supplied from outside by the OS 14 and the PMOS 16 and NMOS of the internal circuit, respectively.
The source 18 is electrically disconnected. This makes it possible to reduce the leakage current during standby.

As described above, the semiconductor device of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

[0045]

As described in detail above, the semiconductor device of the present invention has an absolute value of the threshold voltage, which is connected between the externally supplied power supply and the ground and the internal circuit, respectively. NM of switch transistor larger than threshold voltages of NMOS and PMOS constituting the circuit
The OS and the PMOS electrically connect the externally supplied power supply and ground to the internal circuit during normal operation, and electrically disconnect the externally supplied power supply and ground from the internal circuit during standby. It was made. That is, the semiconductor device of the present invention uses the same power supply voltage as the conventional semiconductor device, generates the internal power supply voltage and the internal ground voltage by the switch transistor, and the internal circuit generates the amplitude of the internal power supply voltage to the internal ground voltage. Operate within range. Therefore, according to the semiconductor device of the present invention, it is not necessary to separately prepare a dedicated power supply voltage, and power consumption can be significantly reduced as compared with a conventional semiconductor device using the same power supply voltage. . Further, according to the semiconductor device of the present invention, the PMOS of the internal circuit is provided.
And by lowering the threshold voltage of the NMOS,
Since the internal circuit can operate at high speed and the threshold voltages of the NMOS and PMOS of the switch transistor are increased, the leakage current during standby can be significantly reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are circuit diagrams of a semiconductor device according to an embodiment of the present invention during operation and non-operation, respectively, and FIG. 1C is a circuit diagram of a transistor used in the semiconductor device according to the present invention; FIG. 9 is an explanatory diagram of an example showing a threshold value.

FIGS. 2A and 2B are a conceptual diagram of an embodiment of a semiconductor device of the present invention during operation, respectively, and an operation timing chart of the embodiment.

FIG. 3 is a conceptual diagram of an example of a conventional semiconductor device.

FIG. 4 is a conceptual diagram of another example of a conventional semiconductor device.

[Explanation of symbols]

10, 20, 28 Semiconductor device 12, 18, 24, 32, 34 N-type MOS transistor (NMOS) 14, 16, 22, 30 P-type MOS transistor (P
MOS) 26 VT circuit

Claims (2)

[Claims] An external circuit for connecting a power supply and a ground externally supplied to the internal circuit during a normal operation; Sometimes, an N-type MOS transistor and a P-type MOS electrically disconnect the power supply and ground supplied from outside from the internal circuit.
Transistors, wherein the absolute values of the threshold voltages of the N-type MOS transistor and the P-type MOS transistor are higher than the threshold voltages of the N-type MOS transistor and the P-type MOS transistor constituting the internal circuit. A semiconductor device characterized by the above-mentioned. 2. The N-type MOS transistor is connected between the power supply supplied from the outside and the internal circuit, and the P-type MOS transistor is connected to the internal circuit and the ground supplied from the outside. 2. The semiconductor device according to claim 1, wherein the semiconductor device is connected between the semiconductor device.