JPH10221402A - Power source current measuring circuit for ic tester - Google Patents
Power source current measuring circuit for ic testerInfo
- Publication number
- JPH10221402A JPH10221402A JP9032671A JP3267197A JPH10221402A JP H10221402 A JPH10221402 A JP H10221402A JP 9032671 A JP9032671 A JP 9032671A JP 3267197 A JP3267197 A JP 3267197A JP H10221402 A JPH10221402 A JP H10221402A
- Authority
- JP
- Japan
- Prior art keywords
- dut
- duts
- power supply
- plural
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 abstract description 26
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 101100116283 Arabidopsis thaliana DD11 gene Proteins 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、ICテスタ用電
源電流測定回路についてのものである。特に、ICテス
タで複数のDUT(Device Under Test)の電気的特
性を測定をする場合における電源電流IDDを測定する回
路についてのものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply current measuring circuit for an IC tester. In particular, the present invention relates to a circuit for measuring the power supply current I DD when measuring the electrical characteristics of a plurality of DUTs (Device Under Test) with an IC tester.
【0002】[0002]
【従来の技術】次に、従来技術によるICテスタ用電源
電流測定回路の構成を図4により説明する。図4の11
〜1nはDUTの電源電流IDDを測定する電流計測回路
つきDUT電源(以下、DPS/IDDという)、21
〜2nは開閉器、31〜3nはDUTである。2. Description of the Related Art Next, the configuration of a conventional power supply current measuring circuit for an IC tester will be described with reference to FIG. 11 in FIG.
1 to 1n are DUT power supplies with a current measuring circuit for measuring the power supply current I DD of the DUT (hereinafter referred to as DPS / IDD), 21
22n are switches, and 311〜33n are DUTs.
【0003】図4では、複数のDPS/IDD11〜1
nと複数のDUT31〜3nをそれぞれ一対一に接続し
ている。そして、開閉器21〜2nをそれぞれ直列に接
続している。開閉器21〜2nをオンにすると、複数の
DUT31〜3nにそれぞれ電源電圧を印加し、各DU
T31〜3nの電源電流IDDを測定する。なお、開閉器
21〜2nは図示しないCPUの指令により、オンオフ
する。In FIG. 4, a plurality of DPS / IDDs 11 to 1
n and a plurality of DUTs 31 to 3n are connected one to one. The switches 21 to 2n are connected in series. When the switches 21 to 2n are turned on, a power supply voltage is applied to each of the plurality of DUTs 31 to 3n,
The power supply current I DD of T31 to Tn is measured. The switches 21 to 2n are turned on and off according to a command from a CPU (not shown).
【0004】次に、DPS/IDD11の構成を図5の
回路図に示す。図5の111はD/A変換器、112と
113は抵抗器、114と115は演算増幅器、116
は電流増幅回路、117はIDD測定回路、117Aは抵
抗器、117Bは電流計測回路、117CはA/D変換
器、21Aと21Bは開閉器である。Next, the configuration of the DPS / IDD 11 is shown in a circuit diagram of FIG. 5, 111 is a D / A converter, 112 and 113 are resistors, 114 and 115 are operational amplifiers, 116
The current amplifier circuit, 117 I DD measurement circuit, 117A resistors, 117B are current measuring circuit, 117C is A / D converter, 21A and 21B are switches.
【0005】次に、図4の動作を図6のタイムチャート
により説明する。図6において、TはDUTに電源電圧
を供給している時間、すなわち1個のDUTの測定時間
を示している。また、tは電源電流IDDの測定時間を示
している。Next, the operation of FIG. 4 will be described with reference to a time chart of FIG. In FIG. 6, T indicates the time during which the power supply voltage is supplied to the DUT, that is, the measurement time of one DUT. In addition, t indicates the measurement time of the power supply current I DD .
【0006】図4の構成では、図6に示すように、開閉
器21〜2nは基本的に同時に動作して電源電圧をDU
T31〜3nに供給する。全てのDPS/IDD11〜
1nに電源電流IDDの測定機能が内蔵されているため、
電源電流IDD測定中も全ての開閉器21〜2nはオンし
たままで、複数のDUT31〜3nの電源電流IDDを同
時に測定できる。In the configuration shown in FIG. 4, as shown in FIG. 6, the switches 21 to 2n operate basically simultaneously to reduce the power supply voltage to DU.
Supply to T31 ~ 3n. All DPS / IDD11-
Since 1n has a built-in function of measuring the power supply current I DD ,
All switches 21~2n supply current I DD also during the measurement remains turned on, it measures the power supply current I DD of the plurality of DUT31~3n simultaneously.
【0007】[0007]
【発明が解決しようとする課題】従来は、全てのDPS
/IDD11〜1nに電源電流IDDの測定機能が内蔵さ
れているため、DUTの複数個並列測定数が多くなる
と、電源電流IDDの測定の回路規模が大きくなり、IC
テスタが大型化するという問題がある。また、消費電流
も増大してしまう問題もある。更に、複数のDPS/I
DD11〜1nのばらつきがDUTの電源電流IDD測定
精度に影響を及ぼすという問題もある。Conventionally, all DPS
/ IDDs 11 to 1n have a built-in function of measuring the power supply current I DD , so that when the number of parallel measurement of a plurality of DUTs increases, the circuit scale of the measurement of the power supply current I DD increases,
There is a problem that the tester becomes large. There is also a problem that the current consumption increases. In addition, multiple DPS / I
Variations in DD11~1n there is a problem that affects the supply current I DD measurement accuracy of the DUT.
【0008】この発明は、複数のDUTに複数の第1の
DUT電源を一対一に接続し、前記各DUTに電源電流
IDDを測定する電流計測回路つき第2のDUT電源を分
岐接続し、複数のDUTを並列測定する時間内に、第2
のDUT電源で複数のDUTの電源電流IDDを順次測定
することにより、DUTの並列測定数が増加しても回路
規模の増大を抑えることができ、測定にばらつきの少な
いICテスタ用電源電流測定回路の提供を目的とする。According to the present invention, a plurality of first DUT power supplies are connected one-to-one to a plurality of DUTs, and a second DUT power supply with a current measuring circuit for measuring a power supply current I DD is branch-connected to each of the DUTs. Within the time to measure multiple DUTs in parallel, the second
Of by sequentially measuring the power supply current I DD of the plurality of DUT in DUT power supply, be increased parallel number of measurements of the DUT can suppress an increase in circuit scale, a small variation power supply current measuring IC tester measurement The purpose is to provide a circuit.
【0009】[0009]
【課題を解決するための手段】この目的を達成するた
め、この発明は、複数のDUT31〜3nに直列に接続
し、複数のDUT31〜3nにそれぞれ電源電圧を印加
する複数のDUT電源41〜4nと、前記各DUTに対
応する各DUT電源41〜4nとの接続をオンオフする
複数の開閉器51〜5nと、複数のDUT31〜3nに
分岐接続し、前記各DUTに電源電圧を印加して電源電
流IDDを測定する電流計測回路つきのDUT電源11
と、前記各DUTに対応するDUT電源11の分岐接続
をオンオフする複数の開閉器21〜2nとを備え、複数
の開閉器51〜5nを同時にオンにして複数のDUT3
1〜3nを並列測定する時間内に、複数の開閉器51〜
5nと複数の第2の開閉器21〜2nを順次切り換え、
複数のDUT31〜3nの電源電流IDDを測定する。In order to achieve this object, the present invention provides a plurality of DUT power supplies 41 to 4n connected in series to a plurality of DUTs 31 to 3n and applying a power supply voltage to each of the plurality of DUTs 31 to 3n. A plurality of switches 51 to 5n for turning on and off the connection to each of the DUT power supplies 41 to 4n corresponding to each of the DUTs; and a branch connection to the plurality of DUTs 31 to 3n; DUT power supply 11 with current measurement circuit for measuring current I DD
And a plurality of switches 21 to 2n for turning on and off the branch connection of the DUT power supply 11 corresponding to each of the DUTs.
In the time for measuring 1 to 3n in parallel, a plurality of switches 51 to
5n and the plurality of second switches 21 to 2n are sequentially switched,
The power supply current I DD of the plurality of DUTs 31 to 3n is measured.
【0010】[0010]
【発明の実施の形態】以下、図面を参照して、この発明
による一実施の形態を説明する。図1は、この発明によ
る一実施の形態のICテスタ用電源電流測定回路の構成
図であり、従来技術の図4に対応する。なお、以下、同
符号の構成品はその機能を同じとするので、特に必要の
無い限り、重複する説明は割愛する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a power supply current measuring circuit for an IC tester according to an embodiment of the present invention, and corresponds to FIG. 4 of the related art. In the following, components having the same reference numerals have the same functions, and duplicate descriptions will be omitted unless otherwise required.
【0011】図1の41〜4nはDUT電源(以下、D
PSと略称する)、51〜5nは開閉器であり、その他
は図4と同じものである。In FIG. 1, reference numerals 41 to 4n denote DUT power supplies (hereinafter, DUT power supplies).
The switches 51 to 5n are the same as those in FIG.
【0012】図1では、複数のDPS41〜4nは複数
のDUT31〜3nに直列に接続し、複数のDUT31
〜3nにそれぞれ電源電圧を印加する。複数の開閉器5
1〜5nは前記各DUTに対応する各DUT電源41〜
4nとの接続をオンオフする。DPS/IDD11は複
数のDUT31〜3nに分岐接続する。複数の開閉器2
1〜2nは前記各DUTに対応するDPS/IDD11
の分岐接続をオンオフする。In FIG. 1, a plurality of DPSs 41 to 4n are connected in series to a plurality of DUTs 31 to 3n, and a plurality of DUTs 31
To 3n, respectively. Multiple switches 5
1 to 5n indicate DUT power supplies 41 to 41 corresponding to the respective DUTs.
4n is turned on / off. The DPS / IDD 11 is branched and connected to a plurality of DUTs 31 to 3n. Multiple switches 2
1 to 2n are DPS / IDDs 11 corresponding to the respective DUTs.
Turn on / off the branch connection of
【0013】図2は、図1におけるDPS41の一実施
の形態を示す回路図である。図2の411はD/A変換
器、412と413は抵抗器、414と415は演算増
幅器、416は電流増幅回路、51Aと51Bは開閉器
である。なお、DPS/IDD11は図5に示されたと
おりである。FIG. 2 is a circuit diagram showing one embodiment of the DPS 41 in FIG. In FIG. 2, 411 is a D / A converter, 412 and 413 are resistors, 414 and 415 are operational amplifiers, 416 is a current amplifier circuit, and 51A and 51B are switches. The DPS / IDD 11 is as shown in FIG.
【0014】次に、図1の動作を図3のタイムチャート
により説明する。まず、開閉器51〜5nはIDD測定以
外の測定時にオンして、DPS11〜1nからDUT3
1〜3nに電源電圧を供給する。Next, the operation of FIG. 1 will be described with reference to the time chart of FIG. First, switch 51~5n is turned on during measurement other than I DD measurement, DUT 3 from DPS11~1n
A power supply voltage is supplied to 1 to 3n.
【0015】次に、IDD測定になると、まず、DUT3
1から開始して、開閉器21がオン、開閉器51がオフ
してDPS/IDD11よりDUT31に電源電圧を供
給し、かつIDDを測定する。DUT31のIDD測定が終
了すると開閉器51がオン、開閉器21がオフする。[0015] Then, at the I DD measurement, first, DUT3
Starting from 1, the switch 21 is turned on, the switch 51 is turned off, the power supply voltage is supplied from the DPS / IDD 11 to the DUT 31, and I DD is measured. And I DD measurements DUT31 ends switch 51 is turned on, switch 21 is turned off.
【0016】さらに、開閉器22〜2nと開閉器52〜
5nを同様に順次動作させるにより、DUT31〜3n
までのn個のDUTのIDD測定が完了する。なお、図1
における開閉器の切換は図示しないCPUが制御する。Furthermore, switches 22-2n and switches 52-
5n are sequentially operated in the same manner, so that DUTs 31 to 3n
The ID measurement of n DUTs up to n is completed. FIG.
Is switched by a CPU (not shown).
【0017】図1の回路構成では、DPS/IDDが1
台であるため、n個のDUTのIDD測定時間は、1個
のDUTのIDD測定時間tのn倍の時間が必要となる。
しかし、通常では、図3に示されるように、1個のDU
Tの全体の測定時間に対して、tは極めて短時間である
ため問題とならない。なお、図1では、DPS/IDD
が1つであったが、複数用意してもよい。In the circuit configuration of FIG. 1, DPS / IDD is 1
Therefore, the IDD measurement time of n DUTs requires n times as long as the ID measurement time t of one DUT.
However, usually, as shown in FIG.
Since t is extremely short with respect to the entire measurement time of T, there is no problem. In FIG. 1, DPS / IDD
Is one, but a plurality may be prepared.
【0018】[0018]
【発明の効果】この発明によれば、少なくても1台の電
源電流IDD測定機能を内蔵するDUT電源があれば、他
の複数台のDUT電源には電源電流IDD測定機能が不要
となるので、DUTの並列測定数が増加しても回路規模
の増大を抑えることができ、そのためICテスタの大型
化、及び消費電流の増大を抑えることができる。さら
に、電源電流IDD測定機能を内蔵するDUT電源が1台
の場合は、従来と比べ、複数のDUTに対し、電源電流
IDDの測定にばらつきが少なくなる。According to the present invention, if there is at least one DUT power supply having a built-in power supply current IDD measurement function, the other plurality of DUT power supplies do not need the power supply current IDD measurement function. Therefore, it is possible to suppress an increase in the circuit scale even if the number of parallel measurements of the DUT increases, thereby suppressing an increase in the size of the IC tester and an increase in current consumption. Further, when the number of DUT power supplies having the power supply current I DD measurement function is one, the variation in the measurement of the power supply current I DD for a plurality of DUTs is smaller than in the related art.
【図1】この発明によるICテスタ用電源電圧測定回路
の一実施の形態を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of a power supply voltage measuring circuit for an IC tester according to the present invention.
【図2】図1のDPSの一実施の形を示す回路図であ
る。FIG. 2 is a circuit diagram showing an embodiment of the DPS of FIG. 1;
【図3】図1の動作を示すタイムチャートである。FIG. 3 is a time chart showing the operation of FIG.
【図4】従来技術によるICテスタ用電源電圧測定回路
の回路図である。FIG. 4 is a circuit diagram of a power supply voltage measuring circuit for an IC tester according to the related art.
【図5】図4のDPS/IDD回路図である。FIG. 5 is a DPS / IDD circuit diagram of FIG. 4;
【図6】図4の動作を示すタイムチャートである。FIG. 6 is a time chart illustrating the operation of FIG. 4;
11〜1n IDD測定機能を内蔵するDUT電源(D
PS/IDD) 21〜2n 開閉器 31〜3n 被測定デバイス(DUT) 41〜4n DUT電源(DPS) 51〜5n 開閉器DUT power supply with a built-in 11 to 1n I DD measurement function (D
PS / IDD) 21-2n switch 31-3n Device under test (DUT) 41-4n DUT power supply (DPS) 51-5n switch
Claims (2)
複数のDUT(31〜3n)にそれぞれ電源電圧を印加する複
数の第1のDUT電源(41〜4n)と、 前記各DUTに対応する前記第1の各DUT電源との接
続をオンオフする複数の第1の開閉器(51〜5n)と、 複数のDUT(31〜3n)に分岐接続し、前記各DUTに電
源電圧を印加して電源電流IDDを測定する電流計測回路
つき第2のDUT電源(11)と、 前記各DUTに対応する前記第2のDUT電源(11)の分
岐接続をオンオフする複数の第2の開閉器(21〜2n)とを
備え、 複数の第1の開閉器(51〜5n)を同時にオンにして複数の
DUT(31〜3n)を並列測定する時間内に、複数の第1の
開閉器(51〜5n)と複数の第2の開閉器(21〜2n)を順次切
り換え、複数のDUT(31〜3n)の電源電流IDDを測定す
ることを特徴とするICテスタ用電源電流測定回路。1. A plurality of DUTs (31-3n) connected in series,
A plurality of first DUT power supplies (41 to 4n) for applying a power supply voltage to each of the plurality of DUTs (31 to 3n); and a plurality of on / off connections for connecting the first DUT power supplies corresponding to the respective DUTs. A first switch (51 to 5n) and a second DUT with a current measuring circuit that is branched and connected to a plurality of DUTs (31 to 3n) and applies a power supply voltage to each of the DUTs to measure a power supply current I DD A power supply (11); and a plurality of second switches (21 to 2n) for turning on and off a branch connection of the second DUT power supply (11) corresponding to each of the DUTs. (51-5n) are turned on at the same time and the plurality of first switches (51-5n) and the plurality of second switches (21-2n) are within the time for measuring the plurality of DUTs (31-3n) in parallel. ) Is sequentially switched to measure a power supply current I DD of a plurality of DUTs (31 to 3n).
を特徴とする請求項1記載のICテスタ用電源電流測定
回路2. A power supply current measuring circuit for an IC tester according to claim 1, comprising a plurality of second DUT power supplies.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9032671A JPH10221402A (en) | 1997-01-31 | 1997-01-31 | Power source current measuring circuit for ic tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9032671A JPH10221402A (en) | 1997-01-31 | 1997-01-31 | Power source current measuring circuit for ic tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10221402A true JPH10221402A (en) | 1998-08-21 |
Family
ID=12365346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9032671A Pending JPH10221402A (en) | 1997-01-31 | 1997-01-31 | Power source current measuring circuit for ic tester |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10221402A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100568852B1 (en) * | 1999-03-12 | 2006-04-10 | 삼성전자주식회사 | Parallel test system of semiconductor memory device |
| US7423443B2 (en) | 2005-01-11 | 2008-09-09 | Samsung Electronics Co., Ltd. | Method of performing parallel test on semiconductor devices by dividing voltage supply unit |
| KR20170018180A (en) * | 2015-08-06 | 2017-02-16 | 에스케이하이닉스 주식회사 | Test device and system for testing a plurality of semiconductor apparatus |
| CN115561605A (en) * | 2021-07-02 | 2023-01-03 | 东京毅力科创株式会社 | Inspection apparatus and inspection method |
-
1997
- 1997-01-31 JP JP9032671A patent/JPH10221402A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100568852B1 (en) * | 1999-03-12 | 2006-04-10 | 삼성전자주식회사 | Parallel test system of semiconductor memory device |
| US7423443B2 (en) | 2005-01-11 | 2008-09-09 | Samsung Electronics Co., Ltd. | Method of performing parallel test on semiconductor devices by dividing voltage supply unit |
| US7626413B2 (en) | 2005-01-11 | 2009-12-01 | Samsung Electronics Co., Ltd. | Parallel testing of semiconductor devices using a dividing voltage supply unit |
| KR20170018180A (en) * | 2015-08-06 | 2017-02-16 | 에스케이하이닉스 주식회사 | Test device and system for testing a plurality of semiconductor apparatus |
| CN115561605A (en) * | 2021-07-02 | 2023-01-03 | 东京毅力科创株式会社 | Inspection apparatus and inspection method |
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