JPH1022793A - Flip-flop circuit - Google Patents

Abstract

(57) Abstract: A flip-flop circuit capable of reducing the number of elements and contributing to a reduction in circuit area is provided. SOLUTION: Two latch circuits 16 and 17 in which two stages of inverter circuits 11 are connected in a ring are connected to a plurality of transfer gates 15.
, And each transfer gate 15 is opened and closed by complementary clock signals CLK and XCLK, so that at least the preceding latch circuit 16 alternately performs a signal input operation, a signal latch operation, and an output operation. As a result, the input signal I
A flip-flop circuit that sequentially outputs an output signal OUT based on N is configured. One inverter circuit 11 constituting the preceding latch circuit 16 is connected to the subsequent latch circuit 17.
Are connected to operate as one of the inverter circuits 11. The transfer gate 15 is formed of one of an N-channel MOS transistor and a P-channel MOS transistor, and is opened and closed by one of complementary clock signals CLK and XCLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flip-flop circuit mounted on a semiconductor memory device or various semiconductor integrated circuit devices.

In recent years, semiconductor memory devices and semiconductor integrated circuit devices have required higher integration and larger scale. Therefore, it is necessary to reduce the number of elements and the circuit area of a large number of flip-flop circuits mounted on such semiconductor storage devices and semiconductor integrated circuit devices.

[0003]

2. Description of the Related Art FIG. 18 shows an example of a conventional flip-flop circuit. The input signal IN is input to the inverter circuit 2a via the transfer gate 1a. The output signal of the inverter circuit 2a is input to the inverter circuit 2b, and the output signal of the inverter circuit 2b is input to the inverter circuit 1a via the transfer gate 1b.

The output signal of the inverter circuit 2a is input to the inverter circuit 2c via the transfer gate 1c.
The output signal of the inverter circuit 2c is input to the inverter circuit 2d.

[0005] The output signal of the inverter circuit 2d is input to the inverter circuit 2c via the transfer gate 1d. The output signal of the inverter circuit 2c is output as an output signal OUT via the inverter circuit 2e.

A clock signal CLK is input to the P-channel side gates of the transfer gates 1a and 1d, and a clock signal XCLK which is an inverted signal of the clock signal CLK is input to the N-channel side gates.

A clock signal XCLK is input to the P-channel side gates of the transfer gates 1b and 1c, and the clock signal CLK is input to the N-channel side gates. The clock signals CLK and XCLK are generated by a clock signal generation circuit shown in FIG. That is, the clock signal CK input from the outside is supplied to the inverter circuit 2
f, 2g, as a clock signal CLK,
The clock signal XCLK is output from the inverter circuit 2f.
Is output.

In the flip-flop circuit configured as described above, when the input signal IN is being input, the clock signal CLK is at the L level and the clock signal XCLK is at the H level.
When the level becomes the level, the transfer gates 1a and 1d are turned on, and the transfer gates 1b and 1c are turned off.

Then, the input signal IN is input to the inverter circuit 2a via the transfer gate 1a, and an output signal having the same phase as the input signal IN is output from the inverter circuit 2b based on the output signal of the inverter circuit 2a.

Next, when the clock signal CLK is at the H level,
When the clock signal XCLK goes low, the transfer gates 1a and 1d become non-conductive, and the transfer gates 1b and 1b
1c conducts.

Then, a latch circuit is formed by inverter circuits 2a and 2b, and an inverted signal of input signal IN is input from inverter circuit 2a to inverter circuit 2c via transfer gate 1c. Then, based on the output signal of the inverter circuit 2c, the input signal IN from the inverter circuit 2d is output.
Is output.

Next, when the clock signal CLK is at L level,
When clock signal XCLK attains an H level, transfer gates 1a and 1d are turned on and transfer gates 1b and 1c are turned on.
Becomes non-conductive.

Then, a latch circuit is formed by the inverter circuits 2c and 2d, and an inverted signal of the input signal IN is output from the inverter circuit 2e. Also, a new input signal IN
Is input to the inverter circuit 2a via the transfer gate 1a, and an output signal having the same phase as the input signal IN is output from the inverter circuit 2b.

By repeating such an operation, the input signal IN is sequentially captured, and the output signal OUT based on the input signal IN is sequentially output. If the inverter circuit 2e is omitted, the output signal OUT is inverted.

FIG. 20 shows an example of a conventional flip-flop circuit having a reset function. In other words, this flip-flop circuit includes the inverter circuits 2a and 2c of the flip-flop circuit shown in FIG.
a, 3b, and a reset signal RS is input to one input terminal of the NAND circuits 3a, 3b, and an output signal of the transfer gates 1a, 1c is input to the other input terminal.

With such a configuration, the reset signal RS
When the L-level signal is input, the NAND circuit 3
Output signals a and 3b are reset to H level. If the reset signal RS is at the H level, the circuit operates similarly to the circuit shown in FIG.

[0017]

However, in the flip-flop circuit shown in FIG. 18, five inverter circuits 2 are provided.
a to 2e and four transfer gates 1a to 1d are required. Each of the inverter circuits 2a to 2e has two MOS transistors.
If the transfer gates 1a to 1d are each also formed of two MOS transistors,
A total of 18 transistors are required.

Therefore, there is a problem that the number of elements increases and the circuit area increases. Further, in the flip-flop circuit shown in FIG. 20, since the inverter circuits 2a and 2c are replaced with NAND circuits 3a and 3b to provide a reset function, there is a problem that the number of elements further increases.

An object of the present invention is to provide a flip-flop circuit capable of reducing the number of elements and contributing to a reduction in circuit area.

[0020]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, two latch circuits 16 and 17 in which two stages of inverter circuits 11 are connected in a ring are connected in series via a plurality of transfer gates 15, and the transfer gates 1 and 2 are connected to each other.
5 is opened and closed by the complementary clock signals CLK and XCLK, and at least the preceding latch circuit 16 alternately performs the signal input operation, the signal latch operation, and the output operation, thereby outputting the output signal OUT based on the input signal IN. A flip-flop circuit for sequentially outputting is configured. One inverter circuit 11 constituting the preceding latch circuit 16 is connected so as to operate as one inverter circuit 11 of the subsequent latch circuit 17. The transfer gate 15 is N
It is configured by one of a channel MOS transistor and a P-channel MOS transistor, and is opened and closed by one of the complementary clock signals CLK and XCLK.

According to the present invention, the transfer gate is constituted by an N-channel MOS transistor, and an input terminal of the inverter circuit to which an output signal of the transfer gate is inputted is connected to a high potential side power supply via a P-channel MOS transistor. And the output terminal of the inverter circuit is connected to the P-channel MOS
Connected to the gate of the transistor.

According to a third aspect of the present invention, the transfer gate is constituted by a P-channel MOS transistor, and an input terminal of the inverter circuit to which an output signal of the transfer gate is inputted is connected to a low potential side power supply through an N-channel MOS transistor. The output terminal of the inverter circuit is connected to the N-channel MOS
Connected to the gate of the transistor.

According to the fourth aspect, the inverter circuit and the NAND circuit
Circuits are connected in a ring to form the latch circuit, and a reset signal is input to one input terminal of the NAND circuit.

According to a fifth aspect of the present invention, the latch circuit is formed by connecting an inverter circuit and a NOR circuit in a ring shape, and a reset signal is input to one input terminal of the NOR circuit. (Function) According to the first aspect, since one latch circuit 16 is shared by the preceding latch circuit 16 and the subsequent latch circuit 17, the number of inverter circuits is reduced, and the transfer gate 1
5 is composed of an N-channel MOS transistor or a P-channel MOS transistor, and the number of elements is reduced.

According to a second aspect of the present invention, in an inverter circuit to which a signal is input via a transfer gate formed of an N-channel MOS transistor, the output signal of the inverter circuit is input to the gate by a P-channel MOS transistor, whereby the H level of the transfer gate is set. Of the input level is corrected.

According to a third aspect of the present invention, in an inverter circuit to which a signal is input through a transfer gate formed of a P-channel MOS transistor, the output signal of the inverter circuit is input to the gate of the N-channel MOS transistor so that the L level of the transfer gate is low. Is corrected.

According to the fourth and fifth aspects, the flip-flop circuits according to the first to third aspects are provided with a reset function.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 shows a first embodiment of the present invention. The input signal IN is input to the inverter circuit 11a via an N-channel MOS transistor Tr1 operating as a transfer gate. The clock signal CLK is input to a gate of the transistor Tr1.

The output signal of the inverter circuit 11a is:
The input is input to the gate of the P-channel MOS transistor Tr2. The source of the transistor Tr2 is connected to the power supply VDD, and the drain is connected to the input terminal of the inverter circuit 11a.

The output signal of the inverter circuit 11a is:
The signal is input to the inverter circuit 11b via an N-channel MOS transistor Tr3 operating as a transfer gate. The gate of the transistor Tr3 has the clock signal X
CLK is input.

The output signal of the inverter circuit 11b is
The signal is output as an output signal OUT via the inverter circuit 11c. The output signal of the inverter circuit 11b is input to the gate of a P-channel MOS transistor Tr4, the source of which is connected to the power supply VDD, and the drain of which is connected to the input terminal of the inverter circuit 11b.

The output signal of the inverter circuit 11b is input to the inverter circuit 11a via an N-channel MOS transistor Tr5 operating as a transfer gate. The clock signal XCLK is input to a gate of the transistor Tr5.

The output signal of the inverter circuit 11c is:
The signal is input to the inverter circuit 11b via an N-channel MOS transistor Tr6 operating as a transfer gate. The clock signal CLK is input to a gate of the transistor Tr6.

Next, the operation of the flip-flop circuit configured as described above will be described. When the clock signal CLK goes high and the clock signal XCLK goes low while the input signal IN is being input, the transistor Tr
1, Tr6 is turned on, and the transistors Tr3, Tr5 are turned off.

Then, the input signal IN becomes the transistor Tr1
To the inverter circuit 11a, and an inverted signal of the input signal IN is output from the inverter circuit 11a. When the input signal IN at the H level is input and the output signal of the inverter circuit 11a is at the L level, the transistor Tr2 is turned on, and the input level of the inverter circuit 11a is substantially latched at the power supply VDD level.

Next, when the clock signal CLK is at L level,
When the clock signal XCLK is inverted to the H level, the transistors Tr1 and Tr6 are turned off, and the transistors Tr3 and Tr5 are turned off.
Is turned on.

Then, a latch circuit is formed by a closed loop including the inverter circuits 11a and 11b and the transistors Tr3 and Tr5. The output signal of the inverter circuit 11b is latched by a signal having the same phase as the input signal IN, and the signal is inverted by the inverter circuit 11c. It is output as an output signal OUT.

Next, when the clock signal CLK is at the H level,
When the clock signal XCLK is inverted to the L level, the transistors Tr1 and Tr6 are turned on, and the transistors Tr3 and Tr5 are turned on.
Is turned off.

Then, a latch circuit is formed by a closed loop including the inverter circuits 11b and 11c and the transistor Tr6, and the output signal OUT is latched. At the same time, a new input signal IN is input to the inverter circuit 11a via the transistor Tr1, and an inverted signal of the input signal IN is output from the inverter circuit 11a.

By repeating the above operation, a signal based on the input signal IN is output to the inverter circuits 11a and 11a.
b and a latch circuit composed of transistors Tr3 and Tr5, and inverter circuits 11b and 11c and a transistor Tr.
6 and the latch circuit is alternately latched, and inverted signals of the input signal IN are sequentially output as the output signal OUT.

In the flip-flop circuit configured as described above, the following operation and effect can be obtained. (1) The input signal IN is sequentially latched based on the inversion operation of the clock signals CLK and XCLK, and the inverted signal of the input signal IN is delayed by a half cycle of the clock signal to output the output signal OU.
T can be sequentially output. (2) The first-stage latch circuit is connected to the inverter circuits 11a and 11
b, and the next-stage latch circuit is connected to the inverter circuit 11
b, 11c. Therefore, the inverter circuit 11b
Can be used redundantly, so that the number of inverter circuits used can be reduced and the number of elements can be reduced. (3) Since the four transfer gates are each composed of only the N-channel MOS transistors Tr1, Tr3, Tr5 and Tr6, the number of elements can be reduced by half as compared with the conventional transfer gate. (4) Since the flip-flop circuit having the same function as that of the conventional example shown in FIG. 18 can be constituted by 12 transistors, the number of elements can be greatly reduced. (5) Since each transfer gate is formed of an N-channel MOS transistor, when an H-level signal is transferred at each transfer gate, the signal decreases by the threshold value of the N-channel MOS transistor. 1
The input signal of 1b is raised almost to the power supply Vcc level by the operation of the P-channel MOS transistors Tr2 and Tr4 which are turned on based on the output signals of the inverter circuits 11a and 11b, so that the N-channel MOS transistor is used as a transfer gate. There is no hindrance. (Second Embodiment) FIG. 3 shows a second embodiment.
This embodiment has a configuration in which the transistor Tr6 is omitted from the flip-flop circuit of the first embodiment.

With such a configuration, the transistor Tr
3. When Tr5 is turned on, the inverter circuits 11a, 11
b and the inverter circuits 11b and 11c
Is performed simultaneously with the latch operation. Since the transistor Tr6 is omitted, the number of elements can be further reduced.

In this configuration, in order to improve the rising speed and falling speed of the output signal OUT,
It is necessary to ensure a sufficient load driving capability of the inverter circuit 11a via the transistor Tr3. (Third Embodiment) FIG. 4 shows a third embodiment. This embodiment is different from the transistor Tr3 and the transistor Tr6 of the flip-flop circuit of the first embodiment.
And an output signal OUT is output from the connection point with.

With such a configuration, the output signal OUT
Means that when the transistor Tr3 is turned on, the transistor Tr3 does not go through the inverter circuits 11b and 11c.
Clock signals CLK, XCL
The operation speed from the inversion operation of K to the output of the output signal OUT can be improved.

When the transistor Tr6 is turned on,
Inverter circuits 11b and 11c perform a latch operation of output signal OUT. In order to improve the rising speed and the falling speed of the output signal OUT, it is necessary to sufficiently secure the load driving capability of the inverter circuit 11a via the transistor Tr3. (Fourth Embodiment) FIG. 5 shows a fourth embodiment. This embodiment has a configuration in which an inverter circuit 11d is added to the flip-flop circuit of the third embodiment.

With such a configuration, the output signal OUT is an inverted signal of the output signal OUT of the third embodiment, but it is easy to secure the load driving capability by the operation of the inverter circuit 11d. (Fifth Embodiment) FIG. 6 shows a fifth embodiment. In this embodiment, the output signal OUT is output from the output terminal of the inverter circuit 11b of the flip-flop circuit of the first embodiment.

With such a configuration, the output signal OUT is an inverted signal of the output signal OUT of the first embodiment. (Sixth Embodiment) FIG. 7 shows a sixth embodiment. In this embodiment, the output signal of the inverter circuit 11b of the flip-flop circuit of the fifth embodiment is output as an output signal OUT via an inverter circuit 11e.

With such a configuration, the output signal OUT is an inverted signal of the output signal OUT of the fifth embodiment, and the load driving capability can be sufficiently ensured by the operation of the inverter circuit 11e. (Seventh Embodiment) FIG. 8 shows a seventh embodiment. In this embodiment, the output signal OUT of the flip-flop circuit of the first embodiment is connected to the inverter circuit 1.
It is configured to output as an output signal OUT via 1f.

With such a configuration, the output signal OUT is an inverted signal of the output signal OUT of the first embodiment, and the load driving capability can be sufficiently ensured by the operation of the inverter circuit 11f. (Eighth Embodiment) FIG. 9 shows an eighth embodiment. In this embodiment, the output signal OUT of the flip-flop circuit of the second embodiment is connected to the inverter circuit 1.
It is configured to output as an output signal OUT via 1g.

With such a configuration, the output signal OUT becomes an inverted signal of the output signal OUT of the second embodiment, and the load driving capability can be sufficiently ensured by the operation of the inverter circuit 11g. (Ninth Embodiment) FIG. 10 shows a ninth embodiment. In this embodiment, the transfer gate of the seventh embodiment is constituted by P-channel MOS transistors Tr7 to Tr10, and the input terminals of the inverter circuits 11a and 11b are connected to ground GND via N-channel MOS transistors Tr11 and Tr12, respectively. Connected to.

The clock signal XCLK is input to the gates of the transistors Tr7 and Tr10, and the clock signal CL is input to the gates of the transistors Tr8 and Tr9.
K is input.

With such a configuration, the same operation and effect as those of the seventh embodiment can be obtained. Further, in this embodiment, the L-level signal input to the inverter circuits 11a and 11b via the transistors Tr7 and Tr8 changes from the ground GND level to the transistors Tr7 and Tr8.
However, the input levels of the inverter circuits 11a and 11b are increased by the operation of the transistors Tr11 and Tr12 which are turned on based on the output signals of the inverter circuits 11a and 11b which are at the H level at that time.
It is almost at the ground GND level.

Therefore, there is no problem even if the transfer gate is formed of a P-channel MOS transistor. (Tenth Embodiment) FIG. 11 shows a tenth embodiment. In this embodiment, the inverter circuit 11b of the seventh embodiment is replaced with a NAND circuit 12a, and a reset signal RS is input to one input terminal.

With such a configuration, the reset signal RS
Is high, the NAND circuit 12a operates in the same manner as the inverter circuit, and the output signal OUT operates based on the input signal IN.

When the reset signal RS goes low, the output signal of the NAND circuit 12a is fixed at the high level regardless of the input signal IN, and the output signal OUT is fixed at the high level.

Therefore, in this embodiment, the inverter circuit 11b of the flip-flop circuit of the seventh embodiment
Is replaced by the NAND circuit 12a, it is possible to configure a flip-flop circuit having a reset function while reducing the number of elements. (Eleventh Embodiment) FIG. 12 shows an eleventh embodiment. This embodiment is different from the tenth embodiment in that
The AND circuit 12a is replaced with a NOR circuit 13a, and a reset signal RS is input to one of its input terminals.

With such a configuration, the reset signal RS
Is low, the NOR circuit 13a operates in the same manner as the inverter circuit, and the output signal OUT operates based on the input signal IN.

When the reset signal RS goes high, the output signal of the NOR circuit 13a is fixed at low level regardless of the input signal IN, and the output signal OUT is fixed at low level.

Therefore, in this embodiment, a flip-flop circuit having a reset function while reducing the number of elements is constructed by replacing the NAND circuit 12a of the flip-flop circuit of the tenth embodiment with a NOR circuit 13a. can do. (Twelfth Embodiment) FIG. 13 shows a twelfth embodiment. This embodiment replaces the inverter circuit 11a of the seventh embodiment with a NAND circuit 12b,
The inverter circuit 11c is replaced with a NAND circuit 12c, and a reset signal RS is input to one of the input terminals.

With such a configuration, the reset signal RS
Is high, the NAND circuits 12b and 12c operate in the same manner as the inverter circuit, and the output signal OUT operates based on the input signal IN.

When the reset signal RS goes low, the NAND circuits 12b and 12b
The output signal of c is fixed at H level, and the output signal OUT is fixed at L level.

Therefore, in this embodiment, the inverter circuit 11 of the flip-flop circuit of the seventh embodiment
By replacing a and 11c with NAND circuits 12b and 12c, a flip-flop circuit having a reset function can be configured while reducing the number of elements. (Thirteenth Embodiment) FIG. 14 shows a thirteenth embodiment. In this embodiment, the inverter circuit 11a of the seventh embodiment is replaced with a NOR circuit 13b, the inverter circuit 11c is replaced with a NOR circuit 13c, and a reset signal RS is input to one of the input terminals. .

With such a configuration, the reset signal RS
Is low, the NOR circuits 13b and 13c operate in the same manner as the inverter circuit, and the output signal OUT operates based on the input signal IN.

When the reset signal RS goes high, the NOR circuits 13b and 13c
Is fixed at the L level, and the output signal OUT is at the H level.
Fixed to level.

Therefore, in this embodiment, the inverter circuit 11 of the flip-flop circuit of the seventh embodiment
By replacing a and 11c with NOR circuits 13b and 13c, it is possible to configure a flip-flop circuit having a reset function while reducing the number of elements. (Example of Use of the Flip-Flop Circuit) Examples of use of the flip-flop circuit of each of the above embodiments are shown below. (1) As shown in FIG. 15, by connecting the flip-flop circuits F / F of the above embodiments in series and supplying clock signals CLK and XCLK to each flip-flop circuit F / F, Can be configured. (2) As shown in FIG. 16, by connecting the flip-flop circuits F / F of the above embodiments in a ring shape and supplying clock signals CLK and XCLK to each flip-flop circuit F / F, a counter circuit is formed. Can be configured. (3) As shown in FIG. 17, the flip-flop circuits F / F of the above embodiments are connected in series via the selector circuit 14, and the parallel input signal I
NP can be input, and the scan-in signal INS is input to the selector circuit 14 of the first-stage flip-flop circuit F / F.

With such a configuration, one of the parallel input signal INP and the scan-in signal INS is selected by the selector circuit 14, and the clock signals CLK and XCLK are selected.
, A scan F / F circuit for transferring the data based on the data can be configured. (4) The flip-flop circuit according to each of the above-described embodiments has a function of F
It can be used as a transfer circuit for memory cells of an IFO memory, an address signal and an input signal or output data in a clocked memory.

[0067]

As described above in detail, the present invention can provide a flip-flop circuit which can reduce the number of elements and contribute to a reduction in circuit area.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment.

FIG. 4 is a circuit diagram showing a third embodiment.

FIG. 5 is a circuit diagram showing a fourth embodiment.

FIG. 6 is a circuit diagram showing a fifth embodiment.

FIG. 7 is a circuit diagram showing a sixth embodiment.

FIG. 8 is a circuit diagram showing a seventh embodiment.

FIG. 9 is a circuit diagram showing an eighth embodiment.

FIG. 10 is a circuit diagram showing a ninth embodiment.

FIG. 11 is a circuit diagram showing a tenth embodiment.

FIG. 12 is a circuit diagram showing an eleventh embodiment.

FIG. 13 is a circuit diagram showing a twelfth embodiment.

FIG. 14 is a circuit diagram showing a thirteenth embodiment.

FIG. 15 is a block diagram illustrating a usage example of each embodiment.

FIG. 16 is a block diagram illustrating a usage example of each embodiment.

FIG. 17 is a block diagram illustrating a usage example of each embodiment.

FIG. 18 is a circuit diagram showing a conventional example.

FIG. 19 is a circuit diagram illustrating a clock signal generation circuit.

FIG. 20 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 11 inverter circuit 15 transfer gate 16 preceding latch circuit 17 subsequent latch circuit CLK, XCLK complementary clock signal IN input signal OUT output signal

Claims (5)

[Claims] 1. Two latch circuits each having two stages of inverter circuits connected in a ring are connected in series via a plurality of transfer gates, and each of the transfer gates is opened / closed by a complementary clock signal. A flip-flop circuit that sequentially outputs an output signal based on the input signal by alternately performing a signal input operation, a signal latch operation, and an output operation, wherein one of the inverters constituting the preceding-stage latch circuit Circuit is connected so as to operate as one inverter circuit of a subsequent latch circuit, and the transfer gate is an N-channel M
A flip-flop circuit comprising one of an OS transistor and a P-channel MOS transistor, and opened and closed by one of the complementary clock signals. 2. The transfer gate includes an N-channel MOS transistor, and an input terminal of an inverter circuit to which an output signal of the transfer gate is input is connected to a high-potential power supply via a P-channel MOS transistor. 2. The flip-flop circuit according to claim 1, wherein an output terminal of the inverter circuit is connected to a gate of the P-channel MOS transistor. 3. The transfer gate includes a P-channel MOS transistor, and an input terminal of an inverter circuit to which an output signal of the transfer gate is input is connected to a low-potential-side power supply through an N-channel MOS transistor. 2. The flip-flop circuit according to claim 1, wherein an output terminal of the inverter circuit is connected to a gate of the N-channel MOS transistor. 4. The latch circuit according to claim 1, wherein the latch circuit is formed by connecting an inverter circuit and a NAND circuit in a ring shape, and a reset signal is input to one input terminal of the NAND circuit. A flip-flop circuit according to any one of the above. 5. The latch circuit according to claim 1, wherein the latch circuit is formed by connecting an inverter circuit and a NOR circuit in a ring, and a reset signal is input to one input terminal of the NOR circuit. A flip-flop circuit according to any one of the above.