JPH10229272A - Printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a viahole in connection reliability by a method wherein a pad provided on the surface of a wiring board comprises a region which includes two or more viaholes and is electrically connected to a conductor circuit provided inside the wiring board through the intermediary of the viaholes. SOLUTION: A printed wiring board is provided with two or more viaholes 4 provided in a pad 8 region, and an inner conductor circuit 3 located inside the printed wiring board is electrically connected to the pad 8 through the intermediary of the viaholes 4. It is preferable that two to five viaholes are present in the pad 8 region. It is preferable that the viahole 4 is 80 to 150μm in diameter, and the pad 8 region is 600 to 1000μm in diameter and 10 to 20μm in thickness. Furthermore, it is preferable that a solder resist layer 5 is formed on an upper layer so as to keep the pad region 8 exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board having solder bumps, and more particularly, to a printed wiring board in which the connection reliability of via holes is not reduced even by a heat cycle or the like.

[0002]

2. Description of the Related Art In a conventional printed wiring board, when a conductive circuit is electrically connected to an IC chip using solder bumps, pads for forming solder bumps are newly formed from via holes as shown in FIG. In general, a conductor circuit on the inner layer side is connected to the IC chip. For this reason, there is a disadvantage that the wiring length is increased, the wiring density is reduced, and it is difficult to mount components at high density.

On the other hand, as shown in FIG. 2, there is a printed wiring board in which solder bumps are formed directly in via holes on a mounting surface. According to such a printed wiring board,
It is not necessary to newly wire a pad for forming a solder bump from a via hole, and the wiring length can be shortened, so that the wiring density can be improved.

[0004]

However, in the above-mentioned printed wiring board, one solder bump is connected to a conductor circuit on the inner layer side only through one via hole functioning as a pad. Therefore, when peeling occurs between the via hole and the inner conductor circuit due to a heat cycle or the like, there is a new problem that the wiring is disconnected and connection reliability due to the via hole is deteriorated.

When a via hole opening is formed in an interlayer insulating material layer, resin may remain at the bottom of the opening. Also in this case, if the one via hole causes a conduction failure due to the residual resin, there is a problem that the connection reliability due to the via hole deteriorates.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a printed wiring board having excellent via hole connection reliability.

[0007]

Means for Solving the Problems The inventor of the present invention has intensively studied for realizing the above-mentioned object, and as a result, has completed the invention having the following contents as the gist. That is, the present invention
In a printed wiring board in which solder bumps are formed on pads provided on a surface of a wiring board, the pads are formed of a region including two or more via holes, and the conductor circuit of the wiring board is formed through these via holes. And a printed wiring board electrically connected to the printed circuit board.

In the printed wiring board of the present invention, it is preferable that a nickel-gold layer is formed on the pad surface. In the printed wiring board of the present invention, the pad preferably includes 2 to 5 via holes.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A printed wiring board according to the present invention has two or more via holes provided in one pad area, and a conductor circuit of a wiring board located on an inner layer side through the plurality of via holes. And the pad are electrically connected.

As a result, the printed wiring board of the present invention
Even if one via hole is broken by a heat cycle or the like, the other via hole electrically connects the inner layer side conductive circuit and the pad, so that the connection reliability due to the via hole is reduced by the heat cycle or the like. Never.

When a resin is left at the bottom of the via-hole when the via-hole is formed in the interlayer insulating material layer, the via-hole formed in the opening may cause poor conduction. Also in this regard, if there is a plurality of via holes, even if one of the via holes becomes defective in conduction, the other via holes ensure the electrical connection, so that the connection reliability due to the via holes does not decrease.

In such a printed wiring board of the present invention, it is preferable that two to five via holes exist in one pad region. If more than five via holes exist in the pad area, the diameter of the via hole becomes small, and it becomes difficult to form an opening. A more desirable number of via holes is three in the area of the pad.

Here, the diameter of the via hole is 80 to 15
Desirably, it is 0 μm. The reason is that if it is less than 80 μm, it is difficult to form a via hole, while if it exceeds 150 μm, it becomes difficult to form many via holes in the pad.

In the printed wiring board of the present invention, the pad has a region diameter of 600 to 1000 μm and a thickness of 10 to 1000 μm.
It is desirable to set it to 20 μm.

It is preferable that a solder resist layer is formed on the pad layer so that the pad region is exposed. That is, the solder resist layer is formed so that a part of the pad is exposed or the entire pad is exposed. When a part of the pad is exposed, since the outer peripheral portion of the pad is covered with the solder resist layer, a difference in thermal expansion coefficient generated at the boundary between the pad and the interlayer resin insulating material or at the boundary between the pad and the plating resist is obtained. Cracks caused by the above can be suppressed. On the other hand, when the entire pad is exposed, the allowable range of the opening position of the solder resist becomes large, and furthermore, the solder resist and the solder body become hard to contact with each other, so that the solder body does not become constricted and is caused by the constriction. No cracks occur.

Here, the thickness of the solder resist layer is desirably 5 to 30 μm. The reason for this is
If the thickness is less than 5 μm, it is easy to peel off. On the other hand, if it exceeds 30 μm, the IC chip and the solder resist come into contact with each other, making it difficult to mount.

As the solder resist layer, various resins can be used. For example, bisphenol A-type epoxy resin, acrylate of bisphenol A-type epoxy resin, novolak-type epoxy resin and acrylate of novolak-type epoxy resin can be used as an amine-based curing agent. A resin cured with an imidazole curing agent or the like can be used. In particular, when an opening is provided in the solder resist layer to form a solder bump, a resin component is composed of `` novolak type epoxy resin or acrylate of novolak type epoxy resin '' and contains `` imidazole curing agent '' as a curing agent. preferable.

[0018] In the printed wiring board according to the present invention, the pad and the solder body may be provided via a metal layer having a non-oxidizing metal on at least the surface or a conductive roughened layer provided on the pad. It is desirable that the metal layer be firmly adhered through the metal layer. Thus, even when flip-chip mounting (mounting mode in which an IC chip is directly mounted) is performed, the solder is formed between the surface layer of the wiring board on which the solder is formed and the IC chip mounted via the solder. The pad does not peel off due to the difference in thermal expansion coefficient.

Here, the roughened layer may be formed on the entire surface of the conductive circuit including the pad on the outermost layer of the substrate on which the solder resist layer is formed. As a result, the roughened layer on the surface of the conductor circuit including the pad acts as an anchor, so that not only the pad and the solder body are firmly adhered but also the conductor circuit and the solder resist layer are firmly adhered. Therefore, even when a resin having a rigid skeleton such as a novolak epoxy resin is used as a resin component, delamination hardly occurs in the solder resist layer, and any resin is not limited to the novolak epoxy resin. it can.

The reason why the roughened layer is made conductive is that it is not necessary to remove the solder even if it is formed. Therefore, the process is simple. The roughened layer is desirably formed by etching, polishing, oxidizing, and redox treating the surface of the conductor circuit, or by forming a film by plating.

In particular, the copper-nickel-phosphorus alloy layer formed by the plating process is a needle-like crystal layer and is advantageous in that it has excellent adhesion to the solder resist layer. Moreover,
According to the alloy layer, even when a solder body is formed thereon, a large change in electric conductivity does not occur. The composition of the alloy layer is copper, nickel, and phosphorus in proportions of 90 to 96 wt.
%, 1 to 5% by weight, and 0.5 to 2% by weight.
This is because these compositions have a needle-like structure at these composition ratios.

The oxidation treatment is desirably a treatment using a solution of an oxidizing agent consisting of sodium chlorite, sodium hydroxide and sodium phosphate. Further, the oxidation-reduction treatment is performed by immersing in a solution of sodium hydroxide and sodium borohydride after the oxidation treatment.

The metal layer having a non-oxidizing metal at least on the surface, which is further formed at the interface with the solder body on the roughened layer, includes a noble metal,
Specifically, it is desirable to use gold, silver, platinum, palladium, or the like. This is because these metals are non-oxidizing and have excellent adhesion to the solder body. In particular, the metal layer is preferably a layer formed of “nickel-gold” or “copper-nickel-gold” in order from the side closer to the pad. In particular, a metal layer composed of a nickel layer and a gold layer has a thickness of 1
It is desirable to have a nickel layer having a thickness of 5 to 5 μm and a gold layer having a thickness of 0.01 to 0.5 μm.

In the above-mentioned metal layer composed of a nickel layer and a gold layer, the nickel layer improves adhesion to a roughened layer (for example, a needle-like alloy layer composed of copper-nickel-phosphorus) provided on the pad side, On the other hand, the gold layer improves the adhesion with the solder body. The thickness of the nickel layer is desirably 1 to 7 μm in order to ease the unevenness of the needle-like structure of the roughened layer provided on the pad side and facilitate the formation of a solder body. On the other hand, the thickness of the gold layer is suppressed so that the needle-like structure of the roughened layer is not excessively relaxed.

In the printed wiring board having the above-described structure, a plating resist is formed on a resin insulating material whose surface has been roughened as a wiring board for forming a solder body, and a plating resist is formed on a portion where the plating resist is not formed. A so-called additive printed wiring board on which a conductor circuit including pads is formed,
This is advantageous when a build-up printed wiring board is used. This is because in a printed wiring board in which a solder body is supplied to these wiring boards, peeling of the solder body and peeling of the solder resist layer caused by a heat cycle can be suppressed.

In the printed wiring board of the present invention, it is desirable to use an adhesive for electroless plating as a resin insulating layer constituting the wiring board. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there. In the above-mentioned adhesive for electroless plating, particularly, the heat-resistant resin particles subjected to the curing treatment include: Heat-resistant resin powder having an average particle size of 10 μm or less; Agglomerated particles obtained by aggregating heat-resistant resin powder having an average particle size of 2 μm or less; Average particle size is 10μm
A mixture of the following heat-resistant resin powder and a heat-resistant resin powder having an average particle diameter of 2 μm or less; Pseudo particles obtained by adhering at least one of a heat-resistant resin powder having an average particle diameter of 2 μm or less and an inorganic powder to the surface of a heat-resistant resin powder having an average particle diameter of 2 to 10 μm; It is desirable to use seeds. This is because they can form more complex anchors.

Next, one method of manufacturing a printed wiring board according to the present invention will be described. (1) First, a wiring board having an inner copper pattern formed on the surface of a core board is manufactured. The copper pattern is formed on the core substrate by etching the copper clad laminate, or
An adhesive layer for electroless plating is formed on a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, or a metal substrate, and the surface of the adhesive layer is roughened to a roughened surface, which is then subjected to electroless plating. There is a way. Further, if necessary, an adhesive layer for electroless plating is formed on the wiring substrate, an opening for a via hole is formed in this layer, the surface of the layer is roughened, and electroless plating is performed thereon to form a copper pattern and a via. By repeating the step of forming holes, a multilayer wiring board can be obtained. Note that a through hole is formed in the core substrate, and the wiring layer on the front surface and the back surface can be electrically connected through the through hole.

(2) Next, an interlayer resin insulating material layer is formed on the wiring board prepared in (1). In particular, in the present invention,
It is desirable to use the above-mentioned adhesive for electroless plating as an interlayer resin insulating material.

(3) After the adhesive layer for electroless plating formed in (2) is dried, an opening for forming a via hole is provided. In the case of a photosensitive resin, it is exposed and developed and then thermally cured. In the case of a thermosetting resin, it is thermally cured and then subjected to laser processing, so that an opening for forming a via hole is formed in the adhesive layer. Is provided. The openings for forming via holes are formed densely in the pad formation region, for example, at three locations as shown in FIG.

(4) Next, the epoxy resin particles present on the surface of the cured adhesive layer are dissolved and removed with an acid or an oxidizing agent to roughen the surface of the adhesive layer. Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid, and it is particularly preferable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded. On the other hand, it is desirable to use chromic acid and permanganate (such as potassium permanganate) as the oxidizing agent.

(5) Next, a catalyst nucleus is applied to the wiring board whose surface of the adhesive layer is roughened. It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus, and generally, palladium chloride or a palladium colloid is used. Note that it is desirable to perform a heat treatment to fix the catalyst core. Palladium is preferred as such a catalyst core.

(6) Next, a plating resist is formed on the wiring substrate to which the catalyst nucleus has been applied. At this time, in order to form a solder bump forming pad, a plating resist non-forming portion having a shape corresponding to the metal pad is provided in the plating resist non-forming portion. As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolak or a phenol novolak type epoxy resin and an imidazole curing agent, but other commercially available products can also be used.

(7) Next, electroless plating is applied to the portion where the plating resist is not formed to form a conductor circuit including a pad and a via hole to manufacture a printed wiring board. Here, it is desirable to use copper plating as the electroless plating.

(8) Next, a conductive roughened layer is formed on the surface of the conductor circuit as required. Examples of a method for forming the roughened layer include an etching process, a polishing process, and a plating process. Of these, the roughened layer formed by plating is preferably a needle-like layer made of a copper-nickel-phosphorus alloy deposited by electroless plating. As electroless plating of this alloy, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0
g / l, citric acid 10-20 g / l, hypophosphite 10-100
g / l, boric acid 10-40 g / l, surfactant 0.01-10 g /
It is desirable to use a plating bath having a liquid composition of 1.

(9) Next, a solder resist composition is applied to at least both surfaces of the printed wiring board that has been subjected to the processing up to (7).

(10) Next, the coating film of the solder resist composition is dried, and a photomask film having an opening formed thereon is placed on the coating film and exposed and developed to thereby form a conductive circuit. An opening exposing the pad portion is formed. Here, the opening diameter of the opening may be larger than the diameter of the pad, and the pad may be completely exposed.

(11) Next, a "nickel-gold" metal layer (a metal layer having a non-oxidizing metal at least on its surface) is formed on the pad portion exposed from the opening. Nickel plating and gold plating are described in pages 13-64 and 84-87 of "NP Series Electroless Plating" (published on September 30, 1990) by Tokuzo Kobe, published by Maki Shoten. Various electroless plating solutions can be used. For example, as electroless nickel plating, nickel chloride 20-40 g / l, sodium hypophosphite 5-20 g /
l, sodium hydroxyacetate 40-60 g / l (or sodium citrate 5-20 g / l), temperature 90 ° C, pH = 4
An electroless nickel plating bath adjusted to ~ 6 can be used. As electroless gold plating, potassium cyanide 1 to 3 g / l, ammonium chloride 70 to 80 g / l,
An electroless gold plating bath adjusted to 40 to 60 g / l of sodium citrate, 5 to 20 g / l of sodium hypophosphite, a temperature of 92 to 95 ° C, and a pH of 7 to 7.5 can be used.

In the present invention, when a nickel-plated copper-nickel-phosphorus alloy layer having a thickness of 0.5 to 7 μm is plated with nickel, if the nickel layer has a thickness of 1 to 7 μm, the roughened layer has It is almost filled with a nickel layer and its surface becomes almost flat. Then, it is desirable to apply gold plating to the surface of the flat nickel layer to a thickness of 0.01 to 0.06 μm. The copper-nickel-phosphorus alloy roughened layer having a thickness of 0.5 to 7 μm may be subjected to copper plating, nickel plating and gold plating in this order to form a metal layer having a thickness of 1 to 7 μm.

(12) Next, a solder body is supplied onto the pad portion exposed from the opening. As a method of supplying the solder body, a solder transfer method or a printing method can be used.
Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening portion to form a solder pattern to form a solder carrier film. Is applied to a solder resist opening portion of a substrate, and then laminated such that a solder pattern is in contact with a pad, which is heated and transferred. on the other hand,
The printing method is a method in which a metal mask having a through-hole provided at a position corresponding to a pad is placed on a substrate, and a solder paste is printed and heated.

[0040]

【Example】

Example 1 (1) 18 μm on both sides of a substrate made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.6 mm.
A copper-clad laminate obtained by laminating m copper foils was used as a starting material. The copper foil of the copper-clad laminate was etched in a pattern according to a conventional method to form inner layer copper patterns on both surfaces of the substrate.

(2) The substrate on which the inner layer copper pattern was formed in the above (1) was washed with water and dried, and then the substrate was acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid. Then, after applying a Pd catalyst and activating this catalyst, copper sulfate 8 g / l, nickel sulfate
0.6 g / l, citric acid 15 g / l, sodium hypophosphite 2
9 g / l, boric acid 31 g / l, surfactant 0.1 g / l, p
Plating was performed in an electroless plating bath consisting of H = 9, and a roughened layer (uneven layer) of Cu-Ni-P alloy having a thickness of 2.5 μm was formed on the entire surface of the copper conductor circuit. Further, the substrate was washed with water, immersed in an electroless tin displacement plating bath composed of 0.1 mol / l tin borofluoride-1.0 mol / l thiourea solution at 50 ° C. for 1 hour, and the Cu-Ni-P alloy 0.3μm on the surface of the passivation layer
Was formed.

(3) 35 parts by weight of 25% acrylate of cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether), 12 parts by weight of polyether sulfone (PES), imidazole cured (Shikoku Chemicals, trade name: 2E4M
2 parts by weight of Z-CN), 4 parts by weight of caprolactone-modified tris (acroxyethyl) isocyanurate (trade name: Alonix M325, manufactured by Toagosei Co., Ltd.), benzophenone (manufactured by Kanto Chemical Co., Ltd.) 2 as a photoinitiator Parts by weight, Michler's ketone as a photosensitizer (Kanto Chemical)
2 parts by weight, and the average particle size of epoxy resin particles (manufactured by Sanyo Chemical Industries, trade name: Polymer Pole) based on this mixture
After mixing 10.3 parts by weight of 3.0 μm and 3.09 parts by weight of an average particle size of 0.5 μm, mixing was performed while adding 30 parts by weight of NMP (normal methylpyrrolidone), and the mixture was adjusted to a viscosity of 7 Pa · s with a homodisper stirrer. After adjustment, the mixture was kneaded with three rolls to obtain a photosensitive adhesive solution (interlayer resin insulating material).

(4) The photosensitive adhesive solution obtained in the above (3) is
On both sides of the substrate after the treatment of the above (2), apply using a roll coater, leave it in a horizontal state for 20 minutes, and then
Drying was performed for 30 minutes to form an adhesive layer having a thickness of 60 μm.

(5) On both surfaces of the substrate on which the adhesive layer was formed in the above (4), a photomask film in which three via holes were gathered in a pad formation region was placed and irradiated with ultraviolet rays. Exposed. (6) The exposed substrate was spray-developed with a DMTG (triethylene glycol dimethyl ether) solution to form an opening serving as a 100 μmφ via hole in the adhesive layer. Furthermore, the substrate is 3,000 mJ
/ Cm ² and heat treatment at 100 ° C for 1 hour and then at 150 ° C for 5 hours to assemble openings (openings for forming via holes) with excellent dimensional accuracy equivalent to a photomask film To form an adhesive layer having a thickness of 50 μm. Note that the tin plating layer is partially exposed in the opening serving as the via hole.

(7) The substrate on which the via hole forming opening was formed in (5) and (6) was immersed in chromic acid for 2 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer 4.
The surface of the adhesive layer was roughened and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.

(8) Roughening treatment (roughening depth 20 μm)
By applying a palladium catalyst (manufactured by Atotech) to the substrate subjected to m), catalyst nuclei were provided on the surfaces of the adhesive layer and the openings for via holes.

(9) 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of an epoxy group of a 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, 15.0 g of dissolved 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001), 1.6 g of imidazole hardener (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN), polyvalent acrylic as a photosensitive monomer A mixed solution A was prepared by mixing 3 g of a monomer (manufactured by Nippon Kayaku, trade name: R604) and 1.5 g of a polyvalent acrylic monomer (manufactured by Kyoeisha Chemical, trade name: DPE6A). On the other hand, 3 g of DMD prepared by heating 2 g of benzophenone as a photoinitiator (manufactured by Kanto Kagaku) and 0.2 g of Michler's ketone as a photosensitizer (manufactured by Kanto Kagaku) at 40 ° C.
G to prepare a mixed solution B. The liquid mixture A and the liquid mixture B were mixed and stirred to obtain a liquid resist composition.

(10) The liquid resist composition is applied to both surfaces of the substrate, which has been subjected to the treatment for providing catalyst nuclei in the above (8), using a roll coater, and dried at 60 ° C. for 30 minutes. 30μ
m of resist layers were formed.

(11) A mask having a pattern drawn thereon was laminated on the resist layer, and the resist layer was exposed to ultraviolet rays. (12) After the exposure in the step (11), the resist layer is dissolved and developed with DMTG to form a plating resist 6 from which the conductor circuit pattern portion has been removed on the substrate, and this is further subjected to an ultra-high pressure mercury lamp.
Exposure was performed at 6000 mJ / cm ² . Further, the plating resist is subjected to a heat treatment at 100 ° C. for 1 hour and then at 150 ° C. for 3 hours to obtain a permanent resist formed on the adhesive layer.

(13) The substrate on which the permanent resist has been formed is subjected to plating pretreatment (specifically, sulfuric acid treatment or the like and activation of catalyst nuclei), and thereafter, 8.6 mM of copper sulfate, 0.15 M of triethanolamine, Formaldehyde 0.02M, copper plating by an electroless copper plating bath consisting of a small amount of bipyridyl, depositing about 15μm thick electroless copper plating on the resist non-formed part, forming the outer layer copper pattern, via hole, A conductor layer was formed by an additive method. (14) Then, the substrate on which the conductor layer was formed was coated with copper sulfate 8 g /
1, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l, immersed in an electroless plating solution having a pH of 9 A roughened layer made of copper-nickel-phosphorus was formed on the surface of the conductor layer.

(15) On the other hand, 60% by weight dissolved in DMDG
Cresol novolak epoxy resin (Nippon Kayaku)
46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of the epoxy groups of epoxy resin, 15.0 g of an 80 wt% bisphenol A type epoxy resin (made by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing 1.6 g of an agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN), 3 g of a polyacrylic monomer which is a photosensitive monomer (trade name: R604, manufactured by Nippon Kayaku), and a polyacrylic monomer (manufactured by Kyoeisha Chemical, trade name) : DPE6A) 1.5 g and a dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.71 g were mixed, and 2 g of benzophenone (Kanto Chemical) as a photoinitiator was added to this mixture. Add 0.2 g of Michler's ketone (manufactured by Kanto Chemical Co.) as a sensitizer, and adjust the viscosity to 25 ° C.
Thus, a solder resist composition adjusted to 2.0 Pa · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B
The rotor was No. 4 at 60 rpm and the rotor No. 3 at 6 rpm.

(16) The substrate obtained in the steps up to (14) is sandwiched between a pair of application rolls of a roll coater in an upright state, and the solder resist obtained in (15) is placed on the surface of the substrate. The composition was applied twice to form a resin layer having a thickness of 20 μm. Here, in the first application, drying was performed at 70 ° C. for 20 minutes.
In the first application, a drying treatment was performed at 70 ° C. for 50 minutes. (17) Next, after forming a resin layer on the surface of the substrate, the resin layer was exposed to ultraviolet rays of 1000 mJ / cm ² and subjected to DMTG development treatment. 1 hour at 80 ° C, 1 hour at 100 ° C, 120 ° C
For 1 hour and at 150 ° C. for 3 hours to form a solder resist layer (thickness: 20 μm) having an open pad (opening diameter: 200 μm).

(18) Next, the substrate on which the solder resist layer was formed was treated with 30 g / l of nickel chloride and sodium hypophosphite.
PH consisting of 10 g / l, 10 g / l sodium citrate =
5 was immersed in the electroless nickel plating solution for 20 minutes to form a nickel plating layer 13 having a thickness of 5 μm at the opening. Further, the substrate was placed on an electroless gold plating solution comprising 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride, 50 g / l of sodium citrate, and 10 g / l of sodium hypophosphite at 93 ° C. for 23 seconds. By dipping, a gold plating layer having a thickness of 0.03 μm was formed on the nickel plating layer. (19) Then, a solder paste was printed on the opening of the solder resist layer and reflowed at 200 ° C. to form a solder bump, thereby producing a printed wiring board having the solder bump.

(Comparative Example) Basically the same as in Example 1, except that the connection between the pad and the lower conductor circuit was made with one via hole.

The printed wiring boards manufactured in Examples and Comparative Examples were subjected to a heat cycle test at -55 ° C. to 125 ° C., and the presence or absence of continuity in the via holes was examined using a flying probe. As a result, out of 100 printed wiring boards,
Table 1 shows the quantity of continuity failures, and the results are shown in Table 1.
Shown in As is clear from the results shown in this table, according to the configuration of the printed wiring board according to the present invention, the conduction reliability in the heat cycle test can be improved.

[0056]

[Table 1]

[0057]

As described above, according to the present invention, a printed wiring board having excellent via hole connection reliability can be stably provided even by a heat cycle or the like.

[Brief description of the drawings]

FIG. 1 is a partial sectional view of a printed wiring board showing a pad structure according to a conventional technique.

FIG. 2 is a partial sectional view of a printed wiring board showing another pad structure according to the related art.

FIG. 3 is a partial sectional view of a printed wiring board showing a pad structure according to the present invention.

[Explanation of symbols]

 Reference Signs List 1 interlayer insulating material layer (adhesive layer) 2 plating resist (permanent resist) 3 conductor (circuit) 4 via hole 5 solder resist layer 6 roughened layer 7 nickel-gold layer 8 pad 9 solder body (solder bump)

Claims (3)

[Claims] 1. A printed wiring board in which solder bumps are formed on pads provided on a surface of a wiring board, wherein the pads are formed of a region including two or more via holes, and the pads are formed through these via holes. A printed wiring board electrically connected to a conductor circuit of the wiring board. 2. The printed wiring board according to claim 1, wherein a nickel-gold layer is formed on a surface of the pad. 3. The printed wiring board according to claim 1, wherein the pad includes 2 to 5 via holes.