JPH1023332A - Synthetic signal processing circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To prevent a loss of information due to signal processing from occurring and to make a synthetic boundary clearly visible. SOLUTION: A synthesizing unit 103 for synthesizing a plurality of digital images, and a dividing unit 104 for dividing one screen of the digital image synthesized by the synthesizing unit 103 into a plurality of blocks, are provided. By setting and synthesizing a synthesis boundary line in accordance with the position of the boundary line for each of the blocks, the synthesis boundary line is prevented from coming into the block, and information is lost by signal processing such as thinning processing. Should not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite signal processing circuit, for example, to a synthesizing system for synthesizing two images, and is used for an editing machine, a synthetic video recorder, or a scene change function in a video camera. To a synthesized signal processing circuit.

[0002]

2. Description of the Related Art A conventional video composition system is shown in FIG. In FIG. 5, reference numeral 501 denotes a synthesis device;
Is a video input terminal, 504 and 505 are AD converters, 50
6 is a synthesizing circuit, 507 is a DA converter, 508 is a video output terminal, and 509 is a monitor.

The video input terminals 501 and 502 have
The composite video signal or the luminance signal Y is input. Then, the input signal is supplied to the AD converter 50.
The digital signal is converted into a digital signal by the signals 505 and 505 and sent to the synthesizing circuit 506.

FIG. 6 shows a configuration of the synthesizing circuit 506. 6, reference numerals 601 and 602 denote video input terminals,
603 and 604 are memories, 605 is a switch circuit, 60
6 is a switching control circuit, and 607 is a video output terminal.

[0005] Two video signals output from the AD converters 504 and 505 are input via video input terminals 601 and 602 and stored in memories 603 and 604, respectively. Then, the data is read from these memories 603 and 604 according to the sampling clock, and is sent to the switch circuit 605, respectively.

The switching control circuit 606 switches the switching circuit 605 by counting the sampling clocks, alternately selects two video signals in one frame and combines them into one video signal and outputs it to the video output terminal 607. I do.

[0007] For example, when one screen is composed of left and right halves, the switching circuit 606 connects the switch circuit 605 to the memory 603 for the first half of one horizontal synchronization period.
The latter half is connected to the memory 604 side. In the next line, the image is reconnected to the memory 603 side, and by repeating this, left and right different images are combined into one. Needless to say, the composition can be performed by switching the switch circuit 605 even if the composition is not the right and left halves or the composition is performed vertically.

Returning to FIG. 5, the video signal output from the synthesizing circuit 506 is converted into an analog signal by a DA converter 507 and output from a video output terminal 508. The editor checks the video at that time on the monitor 509. FIG. 7 shows a conceptual diagram at this time.

[0009]

However, in the above-described conventional example, the composite boundary between the two images is at the center of the screen or at an arbitrary position. However, in the digital recording / reproducing system for performing compression processing, the composite boundary is used. If is set at an arbitrary position, a composite boundary line may come within the compressed block.
Since the synthesized boundary becomes a high-frequency component, if the synthesized boundary comes in the compressed block, information is lost due to signal processing such as thinning processing, and the synthesized boundary is blurred.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to prevent a loss of information due to signal processing and to make a synthesized boundary clearly visible.

[0011]

SUMMARY OF THE INVENTION A composite signal processing circuit according to the present invention comprises a synthesizing means for synthesizing a plurality of digital images and a dividing means for dividing one screen of the digital image synthesized by the synthesizing means into a plurality of blocks. Wherein the synthesizing unit sets and synthesizes a synthesis boundary line in accordance with the position of the boundary line for each block divided by the division unit.

Another feature of the present invention is that
Synthesizing means for synthesizing a plurality of digital images; dividing means for dividing one screen of the digital image synthesized by the synthesizing means into a plurality of blocks; and performing predetermined signal processing on the digital images divided by the dividing means. And a signal processing means for performing a predetermined signal processing by the signal processing means by setting a synthesis boundary line in accordance with the position of the boundary line for each block divided by the division means. It is characterized by applying.

According to another feature of the present invention, in the combined signal processing circuit according to claim 2, the combining means includes a memory circuit, a combining circuit, and a control circuit. Is characterized in that the synthesizing operation of the synthesizing circuit is controlled to set a synthesizing boundary line at an arbitrary boundary position for each block.

Another feature of the present invention is that, in the composite signal processing circuit according to the second aspect, the block divided into a plurality by the dividing means is a DCT block.

According to another feature of the present invention, in the composite signal processing circuit according to claim 2, the signal processing means includes a digital VTR compression means and a recording / reproducing means. I have.

According to another feature of the present invention, in the composite signal processing circuit according to claim 2, the signal processing means includes a JPEG compression means and a recording / reproducing means. .

According to another feature of the present invention, in the composite signal processing circuit according to claim 2, the signal processing means includes an MPEG compression means and a recording / reproduction means. .

According to another feature of the present invention, in the composite signal processing circuit according to claim 2, the signal processing means is H.264. 261 is provided with the compression means and the recording / reproduction means.

According to another feature of the present invention, in the composite signal processing circuit according to the third aspect, the synthesizing means is configured to gradually move the boundaries of a plurality of digital images by the control circuit and synthesize the digital video. This is characterized in that it is a wipe synthesizing means.

Since the present invention has the above-mentioned technical means, a composite boundary line is set in accordance with the position of the boundary line for each block divided by the division means, and the digital video is synthesized. , So that loss of information can be prevented from occurring in signal processing such as thinning processing.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a composite signal processing circuit according to the present invention. [First Embodiment] At present, a consumer digital VTR that digitizes an existing television signal and records it on a magnetic tape has appeared. These basic formats are
"NIKKEI ELECTRONICS BOOK
S. (1993.10.1.), "Data compression technology, home digital VTR first establishes current television signal standards." The first embodiment of the composite signal processing circuit of the present invention will be described with reference to this signal processing.

First, the configuration of a block for processing the luminance signal Y in the video signal is shown in the block diagram of FIG. In FIG. 1, reference numerals 101 and 102 denote AD converters, and reference numeral 103 denotes a synthesizing circuit for synthesizing signals output from the AD converters 101 and 102.

Reference numeral 104 denotes a DCT block dividing circuit;
Denotes a compression circuit, 106 denotes an error correction code adding circuit, and 107 denotes a recording coding circuit. 108 is a magnetic tape, 1
09 is a detection circuit, 110 is an error correction circuit, 111 is a decompression and decoding circuit, and 112 is a DA converter.

In the above configuration, when two Y signals (luminance signals) are input to the AD converters 101 and 102,
The signals are converted into digital signals and sent to the synthesis circuit 103. The combining circuit 103 determines a combining boundary line in accordance with the block information S1 sent from the DCT block dividing circuit 104, combines two Y signals sent from each of the AD converters 101 and 102 into one, and performs DCT block dividing. Output to the circuit 104.

Here, DCT block division and block information S1 will be described with reference to the explanatory diagram of DCT block division in FIG. In FIG. 2, the uppermost waveform represents the Y signal. This is sampled at 13.5 MHz in the AD converters 101 and 102, and when one horizontal synchronization period from the synchronization signal to the synchronization signal is an NTSC signal, 8
The data is 58 pixels (864 pixels in PAL).

Of these, effective pixels (used for recording) are 720 pixels, excluding 122 and 16 pixels before and after. Also,
Of the 525 lines in the vertical direction, the effective lines are 480 lines. That is, one frame is 720 × 48
0 pixels. As shown in FIG. 2, the DCT block is
One block is composed of 8 × 8 pixels.

Therefore, in the case of the NTSC signal, one frame is divided into 90 blocks in the horizontal direction and 60 blocks in the vertical direction. Block information S1 from the DCT block dividing circuit 104 to the synthesizing circuit 103 is information indicating that a DCT block is configured for each of the eight pixels.

Next, based on the block information S1,
A method of synthesizing a video will be described. FIG. 3 is a block diagram illustrating a configuration of the synthesis circuit 103. In FIG. 3, reference numerals 301 and 302 denote two video input terminals, 303,
304 is a memory, 305 is a switch circuit, 306 is a switching control circuit, and 307 is a video output terminal. The A / D converted Y signal is supplied to the first and second video input terminals 3.
01, 302 and the first and second memories 3
03 and 304 respectively.

The first and second memories 30
The Y signals stored in 3, 304 are read out by the sampling clock and sent to the switch circuits 305, respectively.

The switching control circuit 306 counts sampling clocks in accordance with the block information S1 sent from the DCT block dividing circuit 104. Here, since the pixel is divided into eight pixels, the switch circuit 30 is adjusted to a multiple of eight.
5, and the two video signals are alternately selected in one frame and transmitted to the video output terminal 307 in a combined form.

For example, when synthesizing the screen half by left and right, the switching circuit 306 sets the 123rd of the synchronization signal in FIG.
The switch circuit 305 is connected to the first memory 303 side up to the 359th of the 45 DCT block, and the switch circuit 305 is connected to the second memory 304 side from the 360th.

Then, in the next line, the image is connected to the first memory 303 again, and by repeating this, images different from right and left are combined into one image. of course,
It is also possible to combine so that it is not half left and right,
In either case, switching is performed with a clock number that is a multiple of eight. When combining vertically, the switch circuit 305 is switched for every multiple of eight lines.

Here, a precondition of the present embodiment is that two images are synchronized. When synchronizing two images, when the signal source is a VTR, the other signal is reproduced in synchronization with one signal. In the case of other signal sources, synchronization is performed using a memory,
These techniques are well known and will not be described in detail.

Returning to FIG. 1, the signal divided into the DCT blocks as described above is subjected to DCT in the compression circuit 106, weighted and quantized for each frequency component, and further compressed by performing variable length coding. .

Next, an error correction code adding circuit 106 adds a code for performing error correction at the time of reproduction, performs a modulation for recording in a recording encoding circuit 107, and records the data on a magnetic tape 108. .

In the reproducing process, the pilot signal in the signal reproduced from the magnetic tape 108 is detected by the detecting circuit 109 and reproduced while performing tracking control. Then, after correcting the error in the error correction circuit 110, the expansion and decoding circuit 111 expands the compressed data to restore the original video signal. Next, the restored video signal is converted into an analog signal by the DA converter 112 and output.

FIG. 4 shows a conceptual diagram of the composite signal processing circuit of the present embodiment. In the present embodiment, only the processing of the luminance signal Y has been described for easy understanding, but the format of the color signal processing is naturally defined, and the color video processing is performed similarly to the present embodiment. It can also be used favorably as a signal processing circuit.

In the format of a consumer digital VTR, an 8 × 8 DCT block is known.
Block information S1 from DCT block dividing circuit 104
The same operation can be obtained even if the switching timing is automatically set by the synthesizing circuit 103 without transmitting the information.

[Second Embodiment] In the first embodiment, the description has been given of the standard of the consumer digital VTR for the current broadcasting.
The present invention can be applied favorably because blocks are performed in the same manner.

Further, other compression methods such as JPEG, M
The PEG also uses a DCT block of 8 × 8 pixels. In H.261, a macroblock of 16 × 16 pixels is used, but the synthesizing method may be the same as that of the first embodiment.

[Third Embodiment] In the first embodiment, the composition of the left and right or top and bottom screens has been described. The ratio gradually changes,
There is a so-called wipe. That is, the synthesis boundary line moves. In this case, similarly, the block information S1
It is only necessary to gradually change the synthesis boundary line in accordance with.

That is, in FIG.
Is the block information S1 from the DCT block dividing circuit 104.
(Blocked every 8 pixels). Synthesis circuit 103
In FIG. 3, first, in the first frame, the switching control circuit 306 switches the switching circuit 305 from the first memory 303 to the second memory 304 with eight pixels.

In the next frame, switching is performed with 16 pixels, and in the next frame, switching is performed with 24 pixels.
The switching timing is shifted one after another, and the switching at 90 frames ends. This is an operation of wiping from left to right in 3 seconds since the number of frames per second is 30.

[0044]

As described above, according to the present invention, according to the present invention, a synthesizing means for synthesizing a plurality of digital images, and a division for dividing one screen of the digital image synthesized by the synthesizing means into a plurality of blocks. Means are provided, and the combining boundary of the combining means is set and combined in accordance with the position of the boundary for each block divided by the dividing means, so that the combining boundary does not come within the block. Thus, loss of information does not occur in signal processing such as thinning processing.

Therefore, according to the synthesized signal processing circuit of the present invention, when a video signal is synthesized to display a multi-screen image, or when a digital effect function or the like is operated by a scene change such as a wipe, No loss of information can occur and the composite border can be clearly visible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a synthesized signal processing circuit that best represents the first embodiment of the present invention.

FIG. 2 is a diagram illustrating an outline of DCT block division.

FIG. 3 is a block diagram illustrating a configuration of a synthesis circuit block.

FIG. 4 is a diagram illustrating the concept of the first embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional system.

FIG. 6 is a block diagram illustrating a configuration of a conventional synthesis circuit.

FIG. 7 is a diagram showing the concept of a conventional system.

[Explanation of symbols]

 101, 102 A / D converter 103 Combining circuit 104 DCT block dividing circuit 105 Compression circuit 106 Error correction code adding circuit 107 Recording / coding circuit 108 Magnetic tape 109 Detection circuit 110 Error correction circuit 111 Decompression and decoding circuit 112 DA converter 301, 302 Two video input terminals 303, 304 Memory 305 Switch circuit 306 Switching control circuit 307 Video output terminal 501 Synthesizer 502, 503 Video input terminal 504, 505 AD converter 506 Synthesis circuit 507 DA converter 508 Video output terminal 509 Monitor 601 602 Video input terminal 603, 604 Memory 605 Switch 606 Switching control circuit 607 Video output terminal

Claims (9)

[Claims] 1. A synthesizing unit for synthesizing a plurality of digital images, and a dividing unit for dividing one screen of the digital image synthesized by the synthesizing unit into a plurality of blocks, wherein the synthesizing unit includes the dividing unit A composite signal processing circuit, wherein a composite boundary line is set in accordance with the position of the boundary line for each of the blocks divided by the step (b) to perform the composition. 2. A synthesizing unit for synthesizing a plurality of digital images, a dividing unit for dividing one screen of the digital image synthesized by the synthesizing unit into a plurality of blocks, and a digital image divided by the dividing unit. Signal processing means for performing predetermined signal processing, wherein the synthesizing means sets and synthesizes a synthesis boundary line in accordance with the position of the boundary line for each block divided by the division means, and synthesizes the signal. A synthesized signal processing circuit for performing predetermined signal processing on the synthesized signal processing circuit. 3. The combined signal processing circuit according to claim 2, wherein said combining means comprises a memory circuit, a combining circuit, and a control circuit, wherein said control circuit controls a combining operation of said combining circuit. A composite signal processing circuit for setting a composite boundary at an arbitrary boundary position for each block. 4. The composite signal processing circuit according to claim 2, wherein the block divided into a plurality of parts by said division means is a DCT block. 5. The composite signal processing circuit according to claim 2, wherein said signal processing means includes a digital VTR compression means and a recording / reproducing means. 6. The composite signal processing circuit according to claim 2, wherein said signal processing means includes JPEG compression means and recording / reproduction means. 7. The composite signal processing circuit according to claim 2, wherein said signal processing means includes MPEG compression means and recording / reproduction means. 8. The combined signal processing circuit according to claim 2, wherein said signal processing means includes an H.264 signal processor. 261. A combined signal processing circuit comprising the compression unit and the recording / reproducing unit. 9. The synthesized signal processing circuit according to claim 3, wherein said synthesizing means is a wipe synthesizing means for gradually moving a boundary line of a plurality of digital images by said control circuit and synthesizing them. Synthetic signal processing circuit.