JPH1024148A - Chip collator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip collator with a simple mechanism which checks the abusing of a chip carried on a control substrate of game machines. SOLUTION: This apparatus comprises a CPU1 for control, chip sockets 3 and 4 to be collated interconnected through an ID circuit 2, a ROM 5 into which is stored a control program for the CPU for control, a work RAM6 which is used for primary memory of collation data and as working area of the control program, a chip 8 for collation connected to the CPU for control through the ID circuit 7 and sockets 9 and 10 for mounting a transcript chip (normal chip) for comparing a built in ROM connected to the CPU for control. The CPU for control performs a collation with an operation switch 11 and the results are shown on a display LED 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a collator for checking the illegality of a microcomputer chip (hereinafter simply referred to as a chip) used for controlling a game machine such as a pachinko machine, a pachislot machine, and the like. .

[0002]

2. Description of the Related Art In the present invention, a pachinko machine, a pachislot machine and the like are controlled by a chip, and the control device of the game machine includes a mounted chip and a control program. It is in a situation where only used items are allowed to be used. However, after installation in a store such as a pachinko hall, unauthorized modification of the control device to illegally operate the payout rate, jackpot probability, and the like are not endless. Therefore, in order to prevent such unauthorized modification of the chip, a method of writing a certification program on a chip having a security check function and mounting the chip on a control board of a game machine is adopted.

[0003]

However, according to such a method, the act of altering the program incorporated in the chip can be prevented, but a method of performing illegal operation by replacing the chip or ROM with a counterfeit product is conceivable. In such a case, it cannot be checked. In addition, a fake ROM product can be compared with a genuine product using a device such as a ROM writer, but a fake chip product can be inspected only by using a large-scale device such as an IC tester. Therefore, the present invention has been made in view of the drawbacks of the prior art,
It is an object of the present invention to enable a chip to be checked by a simple and portable collator.

[0004]

That is, the present invention relates to a socket for inserting a microcomputer chip (hereinafter referred to as a chip) of a game machine to be collated, a control CPU connected to the socket, and a control CPU. A built-in ROM storing a control program of a collator connected to the CPU,
A RAM used as a temporary storage of the collation data of the CPU and a work area of a control program, and a collation chip for verifying a security calculation reference value and a recalculation value of a chip to be collated connected to the CPU. The security information transfer command is transmitted to the chip to be verified of the gaming machine mounted on the socket in accordance with the control program of the collator, and the data decrypted by the chip to be verified is transmitted again to the chip for verification. This is a chip collator having a function of checking whether or not the data value decoded by the chip to be verified is correct based on the data returned from the chip to determine whether the chip to be verified is appropriate. The invention according to claim 2 is further characterized in that the program data in the built-in ROM of the chip to be verified is read in the security mode and the PR
By comparing and reading data read in the OM mode, it is configured to check whether the built-in ROM has been altered. Further, the device according to claim 3 compares the contents of the programs in the built-in ROM mounted on each of the certified chip and the chip to be verified after verifying the security circuit of the chip according to the invention of claim 1, thereby determining whether the built-in ROM is appropriate. It is configured to judge.

[0005]

The security device according to the present invention checks the security function of the chip itself. The chip of the gaming machine which has been originally certified stores an identification circuit equipped with an encryption algorithm for security check. For example, when a security information transfer command, key data, encrypted data, and dummy data are transmitted, the data is encrypted and transmitted such as a decrypted data confirmation command, decrypted data, security operation check, and other information. . Therefore, the control CPU of this device first extracts a security information transfer command, key data, encrypted data, and dummy data information of the collator by transmitting a command to the collation chip, and transmits these to the chip to be collated. I do. Then, the verification target chip performs encryption according to a predetermined algorithm, and returns a decryption data confirmation command, decryption data, and security operation check information to the control CPU. When such information is transmitted to the matching chip again, the matching of the decrypted data is performed in the matching chip, and the determination result is returned to the control CPU. As a result, it is determined whether the security function of the chip to be verified is operating properly or not. Next, in the collator according to the second aspect of the present invention, when it is determined that the data is appropriate in the above function, the data in the internal ROM of the chip to be verified is read in the security mode to confirm the data in the internal ROM of the chip to be verified. Built-in RO of chip to be verified captured by switching to PROM mode
Compare M data. Originally, these data must completely match, but when the program has been modified, it is determined to be inappropriate because the data does not match. According to the third aspect of the present invention, after the security check, the data in the certified ROM and the data in the built-in ROM of the chip to be verified are extracted and compared to check whether the program has been modified.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. FIG. 1 is a block diagram showing an apparatus according to an embodiment of the present invention.
1, a to-be-verified chip socket 3 or 4 connected via an ID circuit 2, a ROM 5 in which a control program of the control CPU 1 is stored, and a work to be used as a temporary storage of verification data and a work area of the control program. RAM6
And a verification chip 8 connected to the control CPU 1 via an ID circuit 7 and sockets 9 and 10 for mounting a copy chip (regular chip) for comparison with a built-in ROM connected to the control CPU 1. The control CPU 1 operates the operation switch 11 to collate the chip to be collated, and displays the collation result on the display LED 12.

FIG. 2 is a front view of the collation device. The collation device has start / end operation buttons 11 at the upper right, and abnormal, normal, collation, running out of battery, and the like from the upper left. Display LEDs 12 for displaying are arranged, and sockets 3 for connecting chips (for verification and certified copy) are provided below the display LEDs 12, respectively.
9 and different types of chips (for verification and transcripts)
Sockets 4 and 10 for connecting the
Reference numeral 13 denotes a slide cover which covers a socket of a chip to be verified and a certified chip not used for verification and has a function of switching connection between a control CPU of the collator and a socket into which a different type of certified chip and a verified chip are inserted. FIG. 3 shows the exchange of data between the chip 3 to be verified and the control CPU 1 and the data exchange between the verification chip 8 and the control CPU 1. According to the control program stored in the ROM 5, the control CPU 1 By transmitting a security function operation check command to the chip 8, a security information transfer command (A), key data (B), encrypted data (C), and dummy data (D) are received from the verification chip 8, and these are received. Through the ID circuit 2 to the socket 3 or 4 on which the chip to be verified is mounted. As a result, the decrypted data confirmation command (E), the decrypted data (F), and the security operation check information (G) are returned from the chip to be verified. By transmitting these data to the matching chip again, a determination result is obtained from the matching chip.

As shown in FIG. 4, the chip performs serial communication from the collator to the chip to be collated, and if no error occurs, enters the security mode (ID mode) and switches to the parallel communication. It is configured. Further, the prerequisite chip has a built-in user ROM in which an application program for controlling a gaming machine is stored, and a predetermined key code and a predetermined encryption algorithm are transmitted when the chip transmits encrypted data. An identification circuit having a function of performing a security check based on the information is mounted, and data encrypted by the circuit is output to the outside.

In the configuration described above, the collator according to the present embodiment inspects the chip to be collated based on the flowchart shown in FIG. At the time of inspection, a genuine chip to be compared (certified by a public organization) is attached to the certified chip sockets 9 and 10 of the collator, and a chip to be collated mounted on the gaming machine to be collated. Is removed, and it is carried out in a state where it is mounted on the to-be-verified chip sockets 3 and 4 of the collator.

When the start switch of the collator is turned on, first, all the LEDs of the display section are turned on, and a self-diagnosis is made as to whether the device operates properly and whether the chip is properly mounted. When an error occurs as a result of the self-diagnosis, the abnormal LED is blinked. When there is no abnormality, only the start LED is turned on, and the control CPU 1 uses the ID terminal of the chip for the chip to be verified and the chip for verification, and performs bidirectional serial communication to determine whether the chip is genuine. Confirmation is made and the chip is shifted to the command phase. If a sequence error occurs, the abnormal LED is turned on and the collation is stopped.

An operation check command of the security function is transmitted to the verification chip 8, and the security information transfer command (A), key data (B), encrypted data (C), dummy data (D) ( The key, encryption, and dummy data are different each time), and the control CPU 1 transmits the data to the chip 3 or 4 to be verified. Then, based on those data, the verification target chip 3 or 4 outputs the decryption data confirmation command (E), the decryption data (F), and the security operation check information (G), and transmits them to the verification chip 8. As a result, the matching chip 8 checks whether or not the value of the decrypted data is correct, determines the security operation check information,
The determination result is output to the control CPU 1. As a result, when an error occurs, the abnormal LED is turned on. When the error is normal, the process proceeds to the next step.

Next, the ROM data to be verified read out in the security mode (ID mode) is compared with the ROM data to be verified read out in the PROM mode. At times, the operation shifts to comparison with a copy ROM.

That is, the above-mentioned check is a so-called CPU
Of the application program itself, and the application program itself has not been fully checked. When a certified chip is mounted in the socket, a software reset signal is issued to the built-in ROM of the chip to be verified and the built-in ROM of the certified chip, and the built-in ROM of each chip is reset to the PROM mode (chip built-in state). Function to read and write the same ROM data as a normal ROM) and change the RO
The data is taken out of each of the predetermined addresses from M, and the control CPU 1 checks whether or not they match. If the data matches, the end LED is turned on. If the data does not match, the end LED is turned on. Turn on the abnormal LED.

In the apparatus of the present embodiment, the CPU
The chip is verified in three stages: (1) security check of the chip built-in ROM, comparison of the data in the security mode of the ROM built in the chip and PROM mode (2), and comparison of the chip ROM to be verified and the built-in ROM of the certified chip (3). However, the present invention is not limited to this. When the process is completed by only the check (1), when the process is completed by the checks (1) and (2), the process is completed by the checks (1) and (3). It may be constituted by any one of the cases where the processing is terminated.

[0015]

As described above, since the collator according to the present invention is configured to perform collation using the already checked regular chip, the contents of the CPU and the built-in ROM can be easily checked. be able to. In addition, it is extremely difficult to forge because it is necessary to mount all of these circuits in the counterfeit to make a counterfeit because most circuits of the chip are used for verification It becomes something.

[Brief description of the drawings]

FIG. 1 is a block diagram of a chip collator according to an embodiment of the present invention.

FIG. 2 is a plan view of a collator according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating communication exchange of a device according to an embodiment of the present invention.

FIG. 4 is a schematic diagram showing a chip to be verified according to an embodiment of the present invention.

FIG. 5 is a flowchart (1) showing the operation of the apparatus according to the embodiment of the present invention.

FIG. 6 is a flowchart (part 2) illustrating an operation of the apparatus according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control CPU 2, 7 ID circuit 3, 4 Chip socket to be verified 5 Built-in ROM 6 RAM 8 Verification chip 9, 10 Copy chip socket 11 Operation switch 12 Display LED

Claims (3)

[Claims] 1. A socket for inserting a microcomputer chip (hereinafter referred to as a chip) of a game machine to be collated, a control CPU connected to the socket, and control of a collator connected to the control CPU. Internal ROM in which a program is stored, and RAM used as a temporary storage of collation data of the CPU and a work area of a control program
And a verifying chip for verifying a reference value and a recalculated value for security calculation of the verified chip connected to the CPU. A security information transfer command is mounted on the socket according to the control program of the verifying device. The data transmitted to the chip to be verified of the gaming machine, the data decoded by the chip to be verified is transmitted again to the chip for verification, and the data value decoded by the chip to be verified based on the data returned from the chip for verification. A chip collator having a function of judging whether or not a chip to be verified is appropriate by checking whether or not is correct. 2. A socket for inserting a chip of a gaming machine to be verified, and a control CPU connected to the socket.
A built-in ROM storing a control program of a collator connected to the control CPU, a RAM used for temporarily storing collation data of the CPU and a work area of the control program, and a memory connected to the CPU. A verification chip for verifying a reference value and a recalculated value for security calculation of the verification chip, and transmits a security information transfer command to the verification target chip of the gaming machine mounted on the socket according to the control program of the verification device. Then, the data decoded by the chip to be verified is transmitted to the chip for verification again, and it is checked whether or not the data value decoded by the chip to be verified is correct based on the data returned from the chip for verification. A function of determining whether or not the chip to be verified is appropriate; and a built-in ROM of the chip to be verified after the determination is made that the chip is appropriate. Chip collator characterized by having a function of on-chip ROM by collating comparing the read data with the read data and PROM mode in the security mode of the program data is checked whether or not modified. 3. A socket for inserting a chip of a game machine to be verified, and a control CPU connected to the socket.
A built-in ROM storing a control program of a collator connected to the control CPU, a RAM used for temporarily storing collation data of the CPU and a work area of the control program, and a memory connected to the CPU. The verification chip comprises a verification chip for verifying a reference value and a recalculated value for security calculation of the verification chip, and a certified chip socket for inserting a certified certified chip connected to the control CPU. A security information transfer command is transmitted to the chip to be verified of the gaming machine mounted on the socket according to the control program of the console, and the data decrypted by the chip to be verified is transmitted again to the chip for verification, and a reply is returned from the chip for verification. Check whether the data value decoded by the chip to be verified is correct based on the data A function of determining whether the program data in the internal ROM of each of the collated chip and copy chip after it is determined that proper in the determination PRO
A chip collator having a function of checking whether or not a built-in ROM has been modified by comparing and collating in an M mode.