JPH10248066A - Image data decoder and image data decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a display image from being disturbed and decoding processing from being failed even when the decoding processing has a delay. SOLUTION: A video controller 15 generates an interrupt signal synchronously with a frame based on a vertical synchronizing signal and a horizontal synchronizing signal from input ports 21, 22. A sequencer 16 uses the interrupt signal to start decoding processing thereby synchronizing the decoding processing with display. Furthermore, an image memory 17 has memory areas 171-174 that respectively store a decoded image, a forward predicted image, a backward predicted image and a display image. The sequencer 16 reads a prescribed image from the image memory 17 to apply deciding processing to the image and stores the decoded image to the prescribed memory area and reads the decoded image as a display image after one frame so as to prevent disturbance in the image due to a delay in the decoding processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image data decoding apparatus and an image data decoding method for decoding image data obtained by encoding and compressing continuous frame images.

[0002]

2. Description of the Related Art MPEG (Moving Picture Coding Experts G)
roup), an I (Intra coded) picture, a P (Predictive coded) picture, and a B (Bidirectional
It compresses image information of a continuous moving image using three types of picture encoding types, namely, (ly predictive coded) pictures. Here, the I picture is an intra-coded screen that is coded independently of other screens, and the P picture is a forward prediction that is predictively coded from an I or P picture located in the past in time. The B picture is a bidirectional predictive coding screen that is predictively coded from I or P pictures that are temporally located before and after.

[0003] In an encoding process using this method, for example,
As shown in FIG. 10, the original images V1, V2, V3, V4, V5, V6, V7
Are associated with each picture type of I, B, B, P, B, B, P (hereinafter represented by I1, B1, B2, P1, B3, B4, P2,...) I1, P1, B1, B
Encoding is performed in the order of 2, P2, B3, B4,... And is output on a medium. On the other hand, in the decoding process, decoding is performed in the order of I1, P1, B1, B2, P2, B3, B4,.
The display images are output in the order of I1, B1, B2, P1, B3, B4, P2,.

The decoding apparatus stores a forward predicted image used for decoding a P picture and a B picture, and an I or P picture as a backward predicted image, and stores three screens for storing an image to be decoded this time. An image memory having a memory area, and registers RP, FP, BP, and DP for storing pointer values indicating a memory area for storing an image to be decoded this time, a forward prediction image, a backward prediction image, and a display image, respectively, for decoding. An image is read from a predetermined memory area and decoded while changing the pointer value according to the picture type order of the image, and the image in the predetermined memory area is read and output as a display image.

[0005]

However, in the above-mentioned conventional decoding apparatus, since the image memory has only a memory area for three screens, a memory area for writing an image to be decoded and a memory area for reading a display image are provided. May be the same. In order to enable the decoded image to be read out as a display image even in such a case, the readout timing of the display image (display timing) is determined by the decoding processing timing (decoding timing).
More generally, it is delayed by almost half.

However, if the decoding process is not completed within one frame, the display timing overtakes the decoding timing if the decoded image has a frame structure.
The screen of the display image is disturbed and dirty, and furthermore, the decoding process is broken. Therefore, there is a problem that the decoding process has to be stopped when the display timing may overtake the decoding timing. To cope with such a problem, it is conceivable to increase the speed of the decoding process so that the display timing does not overtake the decoding timing. However, setting the processing speed of the decoding device to such a high speed results in setting the processing speed to be considerably higher than the average processing speed, and there is a problem that the decoding device becomes expensive.

The present invention solves such a problem of the prior art, and an image data decoding apparatus and an image data decoding method which do not cause the above-mentioned disturbance of the display image or the failure of the decoding processing even with a decoding apparatus having an average decoding processing speed. It is an object to provide a decoding method.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to an image data decoding apparatus for decoding continuous frame images and decoding compressed image data.
This apparatus reads decoded image data, forward predicted image data, backward predicted image data, an image memory having a memory area for storing display image data, and predetermined image data from the image memory, performs decoding processing, and decodes the image data. Decoding processing means for storing the decoded image data in a predetermined memory area of the image memory, reading out the decoded image data as display image data after one frame, and outputting the display image data; Generating means for generating an interrupt signal synchronized with the beginning of the frame based on the interrupt signal, and control means for monitoring the interrupt signal and, when detecting the interrupt signal, controlling the decoding means to start the decoding process. Features.

In this case, when the control means detects an interrupt signal before the decoding processing of one frame by the decoding processing means is completed, the control means includes a first step of checking a picture type of the frame; If the picture type checked in the step is the B type, the second step of forcibly terminating the current decoding processing and starting the decoding processing of the next frame, and the picture type checked in the first step are If the type is the I or P type, the current decoding process is continued in the third step of continuing the current decoding process, and if the interruption signal is detected again before the decoding process in the third step is completed, the current decoding process is terminated. It is preferable to execute a fourth step of forcibly terminating and, when image data of the picture type I is input, waiting for detection of an interrupt signal and starting decoding processing of the image data.

[0010] In this case, when the current decoding process is forcibly terminated and the decoding process of the next frame is performed, the B-type image data obtained by the forcibly terminated decoding process is used. Is not output as display image data.

According to the present invention, there is provided an image data decoding apparatus for decoding image data obtained by encoding and compressing continuous frame images, the apparatus comprising: decoded image data; forward predicted image data; backward predicted image data; An image memory having a memory area for storing data; reading out predetermined image data from the image memory to perform decoding processing; storing the decoded image data in a predetermined memory area of the image memory; Decoding means for reading out and outputting as display image data after one frame, and counting means for generating a pulse synchronized with the head of the frame based on the input vertical synchronization signal and horizontal synchronization signal and counting the pulse The count value in the counting means is monitored, and the count value is incremented. Characterized in that a control means for starting the control to decoding processing decoding means when.

In this case, the control means includes a first step of detecting a difference between the count values at the start and end of the decoding process, and when the difference detected in the first step is 1, A second step of examining the picture type of the frame to be processed, ending the decoding processing of the frame when the picture type is B type, and executing the decoding processing of this frame when the picture type is I or P type; If the difference detected in the first step is 2 or more, when image data of picture type I is input, the decoding process of this image data is started after waiting for the count value to be incremented. Steps 4 and 4 are preferably performed.

According to the present invention, there is provided an image data decoding method for an image data decoding apparatus which decodes image data obtained by encoding a continuous frame image and compressing the image data. An image memory having a memory area capable of storing an image, a first register storing a pointer value indicating a memory area storing image data to be decoded, and a memory area storing image data used as forward prediction image data And a third register for storing a pointer value indicating a memory area in which image data used as backward prediction image data is stored.
And a fourth register for storing a pointer value indicating a memory area in which image data used as a display image is stored, and an image stored in the memory area indicated by the pointer value of the fourth register. A first step of examining the picture type of the data, and a second step which permits updating of the memory area indicated by the pointer value of the fourth register when the picture type examined in the first step is the B type.
And if the picture type checked in the first step is the I or P type and the pointer values of the third and fourth registers are the same, the memory indicated by the pointer value of the fourth register Update of the area is permitted, and if the picture type is I or P type, the third register and the fourth
If the pointer values of the first and second registers are not the same, subsequent to the third step and the second and third steps, the data is stored in the memory area indicated by the pointer value of the first register. A fourth step of checking the picture type of the image data, and when the picture type checked in the fourth step is the B type, the pointer value of the first register is copied to the fourth register and decoded at this time. A fifth step of decoding the picture layer of the image to check the picture type, and if the picture type checked in the fifth step is the B type, the process directly proceeds to the next step, and if the picture type is the I or P type, In some cases, the memory area indicated by the pointer value of the second register is updated, and the pointer value of the third register is copied to the second register. When the picture type checked in the step and the fourth step is the I or P type, the pointer value of the second register is copied to the fourth register, and the picture layer of the image to be decoded this time is decoded. The picture type checked in the seventh step, and if the picture type checked in the seventh step is the B type, the pointer value of the first register is copied to the third register, and the picture type is set to I or P If so, an eighth step of copying the pointer value of the second register to the third register and copying the point value of the first register to the second register; Following the step, a ninth step of writing a pointer value indicating one of the unused memory areas in the first register is sequentially executed, whereby the forward prediction image data is read. And a memory area for storing backward prediction image data and display image data, and a memory area for storing image data to be decoded, and decoding image data of one frame by performing decoding processing of a picture layer or less. It is characterized by the following.

According to the present invention, there is provided an image data decoding method for an image data decoding apparatus which decodes image data obtained by encoding and compressing a continuous frame image. An image memory having a memory area capable of storing an image, a first register storing a pointer value indicating a memory area storing image data to be decoded, and a memory area storing image data used as forward prediction image data A second register for storing a pointer value indicating the same as the pointer value stored in the second register, and a third register for storing a pointer value identical to the pointer value stored in the second register. A fourth register for storing a pointer value indicating the memory area being used, A fifth register for storing a pointer value indicating a memory area for storing image data, and a sixth register for storing the same pointer value and pointer values stored in the first register used to be,
A first step of checking the picture type of the image data stored in the memory area indicated by the pointer value of the first register; and a third step if the picture type checked in the first step is the I or P type. A second step of allowing the memory area indicated by the pointer value of the register to be updated and copying the pointer value of the second register to the third register and the fifth register, and a picture checked in the first step. When the type is the B type, the memory area indicated by the pointer value of the sixth register is allowed to be updated, the pointer value of the first register is copied to the fifth register and the sixth register, and Following the third step of copying the pointer value of the register to the first register, and the second and third steps, the picture layer of the image to be decoded this time is decoded and the picture layer is decoded. When the picture type is I type or P type, the pointer value of the first register is copied to the second register. When the picture type is B type, the pointer value of the first register is copied. Is copied to a fourth register, and, following the fourth step, a fifth step of writing a pointer value indicating a memory area permitted to be updated in the first register is sequentially executed. Thus, the memory area storing the forward predicted image data, the backward predicted image data, the display image data, and the memory area storing the image data to be decoded are determined. Is decoded.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a decoding apparatus according to the present invention; First, a first embodiment of the decoding device according to the present invention will be described. This decoding device generates an interrupt signal synchronized with the frame of the display, starts the decoding process by this interrupt signal, synchronizes the decoding process with the display, and reduces the decoded image data by at least one. By reading as a display image with a frame delay, the occurrence of image disturbance due to a delay in the decoding process is prevented. FIG.
Is a block diagram illustrating a configuration of the decoding device.

In FIG. 1, an input port 19 is a terminal to which compressed image data encoded and compressed according to the MPEG standard is input, and is connected to the FIFO 10. The FIFO 10 sequentially stores the compressed image data from the input port 19 in a built-in memory, and has a variable length decoder (V
LD) 11 is connected. When a predetermined amount of compressed image data is stored in the FIFO 10, the variable-length decoder 11 reads the stored data according to a control instruction sent from the sequencer 16 that controls the entire system through the control bus 18, and performs variable-length decoding. Is to execute. Also, the variable length decoder 11
Detects the header information of the image from the decrypted data,
This is sent to the sequencer 16 through the control bus 18 and the image data (DCT coefficient) is sent to the decoding operation unit (IQ IDCT) 12 connected to the output side.

The decoding arithmetic unit 12 performs a well-known run-level decoding process, an inverse quantization process, and an inverse discrete process on the image data from the variable-length decoder 11 in accordance with a control instruction sent from the sequencer 16 through the control bus 18. The original frame image data is reproduced by performing processing such as cosine conversion processing. A memory controller 13 is connected to the decoding arithmetic unit 12, and an image memory is connected to the memory controller 13.
17 and FIFO 14 are connected. Memory controller
13 controls the input and output of image data to and from the image memory 17 in accordance with control instructions sent from the sequencer 16 through the control bus 18.
Memory area that can store image data for the number of sheets
171 to 174.

When decoding image data encoded by inter-frame prediction or bidirectional prediction, the memory controller 13 controls the image memory in accordance with a control instruction from the sequencer 16.
The image data decoded earlier in time stored in 17 is read as forward predicted image data or backward predicted image data, and is sent to the decoding arithmetic unit 12. The decoding arithmetic unit 12 uses the image data subjected to the processes such as the run-level decoding process, the inverse quantization process, and the inverse discrete cosine transform process, and the forward prediction image data and the backward prediction image data from the memory controller 13 to generate the original image. Play the data. And
The memory controller 13 stores the image data reproduced by the decoding arithmetic unit 12 in a predetermined memory area of the image memory 17.

On the other hand, the input ports 20 and 21 are connected to a vertical synchronization signal VSYNC and a horizontal synchronization signal HS from an external display.
This is a terminal to which YNC is input, and is connected to the video controller 15. Video controller 15 is an input port
An interrupt signal INT is generated at the head of each frame on the basis of the vertical synchronization signal and the horizontal synchronization signal from 20, 20 and transmitted to the sequencer 16 through the control line 23. When receiving the interrupt signal, the sequencer 16 sends an interrupt reception signal to the video controller 15 through the control line 24.

The video controller 15 has a data enable signal EN for requesting output of decoded image data.
V to the memory controller 13 via the control line 25,
The image data written in the FIFO 14 is read out in accordance with the timing of the vertical synchronization signal and the horizontal synchronization signal of the display, and is output from the output port 22 connected to the output side to the display. When the memory controller 13 receives the data enable signal from the video controller 15, the memory controller 13 displays image data for display in a certain unit (for example, image data for one line).
Is read from the image memory 17 and written into the FIFO 14 connected to the output side.

The decoding apparatus shown in FIG. 1 adopts such a configuration, so that the compressed image data of the MPEG standard input from the input port 19 can be decoded by the variable length decoder 11 and the decoding arithmetic unit 12.
And reproduces the original image data, and outputs this from the output port 22 as display image data.

Next, a decoding method in the decoding apparatus will be described in detail with reference to FIGS. Here, FIG.
The decoding method, in particular, the memory area 171-1 of the image memory 17
174 is a flowchart showing a switching algorithm, and processing in each step excluding step processing S27 is executed by the sequencer 16 shown in FIG. FIG.
Is a time chart showing a sequence of image display by this algorithm, in which compressed image data is transmitted from the input port 19 shown in FIG. 1 to the picture types I0, P1, B2, B3, P
4, B5, P6, P7, P8,..., And when the display image data is output from the output port 22 in the order of I0, B2, B3, P1, B5, P4, P6,. It indicates in which memory area in the image memory 17 the predicted image data, the backward predicted image data, and the display image data are stored.

Referring further to FIG. 3, RR, FP, B
P and DP are memory areas 171 of the image memory 17 shown in FIG.
A register for storing pointer values indicating
The pointer values "1", "2", "3", and "4" indicate the memory areas 171, 172, 173, and 174, respectively. In the register RP, a pointer value indicating a memory area for storing decoded image data to be decoded is stored. In the register FP, a pointer value indicating a memory area in which image data serving as forward prediction image data is stored. Is stored in a register BP, and a pointer value indicating a memory area in which image data serving as backward prediction image data is stored.
The DP stores a pointer value indicating a memory area in which image data serving as display image data is stored.

In FIG. 3, the numbers described in angle brackets at the lower right of each cell indicate the pointer values stored in the corresponding registers, and the symbols I0, P1, etc., described in each cell. Indicates the image of the image data stored in the memory area indicated by the pointer value described in the lower right angle bracket, and the symbol (SXX) described in the upper left of each cell
Indicates a step number in the flowchart of FIG. Note that the registers RP, FP, BP, and DP are included in the memory controller 13 in FIG.

In this embodiment, first, as shown in FIG.
A pointer value indicating a memory area for storing decoded image data, a memory area for storing image data serving as forward prediction image data, backward prediction image data, and image data serving as display image data is stored in predetermined registers RP to DP (step
S11 to S26), and then perform decoding processing for the picture layer and below (step S27) to decode one frame of compressed image data.

First, when decoding the compressed image data corresponding to the first image I0, the register FP and the register BP
Since a meaningful value is not set in, in steps S11 to S25 in the flowchart of FIG. 2, each process is executed with the value indicated by the initial value, and the process proceeds to step S26. At this time, since a meaningful value is not set in the register DP, image data of an initial value is output as a display image from the decoding device. In this case, since the processes in steps S11 to S25 do not directly affect the decoding of the next image data P1, the description thereof is omitted.

In step S26, a memory area for storing the decoded image data is determined. At this time, memory area 17
Since 1 to 174 can be used, the memory area 171 having the smaller number is determined as the memory area for storing the decoded image data, and the pointer value "1" is stored in the register RP. Next, in step S27, decoding processing for the picture layer and below is performed, and the decoded image data of I0 is stored in the memory area 171 indicated by the pointer value "1" of the register RP. Since the image data of I0 is of the I type, it is decoded independently of other images.

Next, when the compressed image data corresponding to the second image P1 is decoded, in steps S11 to S13, the processing is performed using the value indicated by the initial value in the same manner as in the case of the compressed image data corresponding to I0 described above. Run. In the next step S14, the picture type of the image decoded one frame before is checked. Since the picture type is the I type, the flow proceeds to step S15. In step S15, the pointer value of the register FP is copied to the register DP. However, since a meaningful value has not yet been set in the register FP, the value of the register DP also remains at the initial value.

In the next step S16, the header information of the picture layer is decoded, and in step S17, the picture type of the image to be decoded this time is checked. Then, since the picture type is the P type, the flow proceeds to step S18. In step S18, the pointer value of the register FP is copied to the register BP. However, since a meaningful value has not yet been set in the register FP, the value of the register BP also remains at the initial value. In the next step S19, the pointer value "1" of the register RP is copied to the register FP. As a result, the previously decoded image data of I0 stored in the memory area 171 is used as the current forward predicted image data (forward reference image data).

In the next step S26, a memory area for storing the decoded image data is determined. At this time, since the memory areas 172 to 174 can be used, the memory area 172 having the smaller number is determined as the memory area for storing the decoded image data, and the pointer value “2” is stored in the register RP. Next, in step S27, decoding processing for the picture layer and below is performed, and the image data of P1 is reproduced using the image data of I0 in the memory area 171 indicated by the pointer value "1" of the register FP as a forward reference image. Is stored in the memory area 172 indicated by the pointer value “2” of the register RP.

Next, when decoding the compressed image data corresponding to the third image B2, in steps S11 to S13, since a meaningful value has not yet been set in the register DP, processing is performed using the value indicated by the initial value. Execute In the next step S14, the picture type of the image decoded one frame before is checked, and the picture type is
Move to S15. In step S15, since the pointer value "1" is stored in the register FP, the pointer value is copied to the register DP. As a result, the image data I0 stored in the memory area 171 is output as a display image.

In the next step S16, the header information of the picture layer is decoded, and in step S17, the picture type of the image to be decoded this time is checked. This picture type is B
Since the type is the type, the process proceeds to step S20, where the pointer value "2" of the register RP is copied to the register BP. As a result, the previously decoded P1 image data stored in the memory area 172 is used as the backward prediction image data (backward reference image data) this time.

In the next step S26, a memory area for storing the decoded image data is determined. At this time, since the memory areas 173 to 174 can be used, the memory area 173 having the smaller number is used as the memory area for storing the decoded image data, and the pointer value “3” is stored in the register RP. Next, in step S27, decoding processing for the picture layer and below is performed, and the image data of I0 in the memory area 171 indicated by the pointer value "1" of the register FP as the forward reference image, and the pointer value of the register BP as the backward reference image. "2"
B2 image data is reproduced using the P1 image data in the memory area 172 indicated by
3 "is stored in the memory area 173.

Next, when decoding the compressed image data corresponding to the fourth image B3, first, in step S11, the picture type of the image in the memory area 171 indicated by the pointer value "1" of the register DP is checked. This time, since the picture type is the I type, the process proceeds to step S12 and the register
It is checked whether the pointer values of DP and register BP are the same. At this time, the pointer value of the register DP is "1",
Since the pointer value of the register BP is "2", step S14 is executed.
Move on to In step S14, the picture type of the image decoded one frame before is checked, and since the picture type is the B type, the flow proceeds to step S21. In step S21, the pointer value "3" of the register RP is copied to the register DP. As a result, it is stored in the memory area 173.
The image data of B2 is output as a display image.

In the next step S22, the header information of the picture layer is decoded, and in step S23, the picture type of the image to be decoded this time is checked. Since the picture type is the B type, the flow proceeds to step S26. Since both the image data to be decoded this time and the image data decoded one frame before are of the B type, the forward and backward reference image data used for the current decoding are the same as those of the previous time, and the pointers of the registers FP and BP are used. No change in value.

In step S26, a memory area for storing the decoded image data is determined. At this time, memory area 17
Since only 4 is available, the pointer value "4" is stored in the register RP. Next, in step S27,
The decoding process is performed for the picture layer and below, the image data of I0 in the memory area 171 indicated by the pointer value "1" of the register FP as the forward reference image, and the memory indicated by the pointer value "2" of the register BP as the backward reference image. The image data of B3 is reproduced using the image data of P1 in the area 172, and this is stored in the memory area 174 indicated by the pointer value "4" of the register RP.

Next, when decoding the compressed image data corresponding to the fifth image P4, first, in step S11, the picture type of the image in the memory area 173 indicated by the pointer value "3" of the register DP is checked. The picture type is B
Since it is a type, the process proceeds to step S13. In step S13, the memory area 17 indicated by the pointer value "3" of the register DP
Since the image data of B2 stored in No. 3 is not used thereafter, a process of allowing the memory area 173 to be updated is performed. As a result, the memory area 173 can be used. In the next step 14, the picture type of the image decoded one frame before is checked. Since the picture type is the B type, the process moves to step S21, where the pointer value "4" of the register RP
To the register DP. This allows the memory area
The image data of B3 stored in 174 is output as a display image.

In the next step S22, the header information of the picture layer is decoded, and in step S23, the picture type of the image to be decoded this time is checked. Since the picture type is the P type, the flow shifts to step S24. Steps
In S24, since the image data of I0 stored in the memory area 171 indicated by the pointer value "1" of the register FP is not used thereafter, a process for allowing the memory area 171 to be updated is performed. As a result, the memory area 171 becomes usable.
In the next step S25, the pointer value "2" of the register BP is copied to the register FP. As a result, the memory area 17
The image data of P1 stored in 2 is used as the reference image ahead this time.

In the next step S26, a memory area for storing the decoded image data is determined. At this time, the available memory areas are the memory areas 173 and 171 that have been allowed to be updated in steps S13 and S24, so that the memory area 171 with the smaller number is used as the memory area for storing the decoded image data. The pointer value "1" is stored in the register RP. Next, in step S27, decoding processing for the picture layer and below is performed, and the
The image data of P4 is reproduced using the image data of P1 in the memory area 172 indicated by the pointer value "2" of the FP, and this is stored in the memory area 171 indicated by the pointer value "1" indicated by the register RP.

Next, when decoding the compressed image data corresponding to the sixth image B5, first, in step S11, the picture type of the image in the memory area 174 indicated by the pointer value "4" of the register DP is checked. This picture type is B
Since the type is the type, the process proceeds to step S13. In step S13, the memory area 17 indicated by the pointer value "4" of the register DP
Perform processing to allow the update of 4. In the next step S14,
The picture type of the image decoded one frame before is checked. Since the picture type is P type, step
The process moves to S15, and in step S15, the pointer value "2" of the register FP is copied to the register DP. As a result, the image data of P1 stored in the memory area 172 is output as a display image.

In the next step S16, the header information of the picture layer is decoded, and in step S17, the picture type of the image to be decoded this time is checked. Since the picture type is the B type, the process proceeds to step S20,
In S20, the pointer value "1" of the register RP is copied to the register BP. As a result, the P4 image data stored in the memory area 171 is used as the reference image at the rear of the current time.

In the next step S26, a memory area for storing the decoded image data is determined. At this time, since the memory areas 173 and 174 can be used, the memory area 173 having the smaller number is used as the memory area for storing the decoded image data, and the pointer value “3” is stored in the register RP. Next, in step S27, decoding processing for the picture layer and below is performed, and the image data P1 in the memory area 172 indicated by the pointer value "2" of the register FP is referred to as a forward reference image.
The image data of B5 is reproduced using the image data P4 of the memory area 171 indicated by the pointer value "1" of the register BP as the rear reference image, and stored in the memory area 173 indicated by the pointer value "3" of the register RP. I do.

Next, when decoding the compressed image data corresponding to the seventh image P6, first, in step S11, the picture type of the image in the memory area 172 indicated by the pointer value "2" of the register DP is checked. Its picture type is P
Since it is the type, the process moves to step S12, and in step S12, it is checked whether or not the pointer values of the registers DP and BP are the same. At this time, the pointer value of the register BP is "1" and the pointer value of the register DP is "2".
Move to S14. In step S14, the picture type of the image decoded one frame before is checked. Since the picture type is the B type, the process proceeds to step S21 and proceeds to step S2.
In step 1, the pointer value "3" of the register RP is copied to the register DP. Thus, the image data of B5 stored in the memory area 173 is output as a display image.

In the next step S22, the header information of the picture layer is decoded, and in step S23, the picture type of the image to be decoded this time is checked. Its picture type is P
Since the type is the type, the process proceeds to step S24. In step S24, a process of allowing the updating of the memory area 172 indicated by the pointer value "2" of the register FP is performed. In the next step S25, the pointer value "1" of the register BP is changed to "1". Copy to register FP. Thus, the data stored in the memory area 171 is stored.
The P4 image data will be used as the forward reference image this time.

In the next step S26, a memory area for storing the decoded image data is determined. At this time, the memory area 174 and the memory area permitted to be updated in step S24
Since 172 can be used, memory area 1 with a lower number
72 is a memory area for storing decoded image data, and the pointer value “2” is stored in the register RP. In the next step S27, decoding processing for the picture layer and below is performed, and the pointer value "1" of the register FP is set as the forward reference image.
The image data of P6 is reproduced using the image data of P4 in the memory area 171 indicated by.
2 "is stored in the memory area 172.

Next, when decoding the compressed image data corresponding to the eighth image P7, first, in step S11, the picture type of the image in the memory area 173 indicated by the pointer value "3" of the register DP is checked. This picture type is B
Since the type is the type, the process proceeds to step S13. In step S13, the memory area 17 indicated by the pointer value "3" of the register DP
Perform the process that allows the update of 3. In the next step S14,
The picture type of the image decoded one frame before is checked. Since this picture type is P type,
In S15, the pointer value "1" of the register FP is copied to the register DP in Step S15. As a result, the P4 image data stored in the memory area 171 is output as a display image.

In the next step S16, the header information of the picture layer is decoded, and in step S17, the picture type of the image to be decoded this time is checked. This picture type is P
Since the type is the type, the process proceeds to step S18. In step S18, the pointer value "1" of the register FP is copied to the register BP. In step S19, the pointer value "2" of the register RP is copied to the register FP. As a result, the memory area 17
The image data of P6 stored in 2 is used as the reference image ahead this time.

In the next step S26, a memory area for storing the decoded image data is determined. At this time, since the memory areas 173 and 174 can be used, the memory area 173 having the smaller number is used as the memory area for storing the decoded image data, and the pointer value “3” is stored in the register RP. In the next step S27, decoding processing for the picture layer and below is performed, and the pointer value of the register FP is set as the forward reference image.
2 ", using the image data of P6 in the memory area 172,
The image data of 7 is reproduced and stored in the memory area 173 indicated by the pointer value "3" of the register RP.

Next, when decoding the compressed image data corresponding to the ninth image P8, first, in step S11, the picture type of the image in the memory area 171 indicated by the pointer value "1" of the register DP is checked. This picture type is P
Since it is the type, the process proceeds to step S12, and in step S12, it is checked whether or not the pointer values of the register DP and the register BP are the same. Since the pointer values are both "1", the process proceeds to step S13. In step S13, the register
A process is performed to allow updating of the memory area 171 indicated by the DP pointer value "1".

In the next step S14, the picture type of the picture decoded one frame before is checked. Since the picture type is the P type, the process proceeds to step S15, where the pointer value "2" of the register FP is stored in the register DP.
Copy to Thus, the image data of P6 stored in the memory area 172 is output as a display image.
Next, in step S16, the header information of the picture layer is decoded, and in step S17, the picture type of the image to be decoded this time is checked. Since the picture type is the P type, the process moves to step S18, where the pointer value "2" of the register FP is copied to the register BP in step S18, and the pointer value "3" of the register RP is copied to the register FP in step S19. I do. As a result, the image data of P6 stored in the memory area 173 is used as a reference image ahead this time.

In the next step S26, a memory area for storing the decoded image data is determined. At this time, since the memory areas 171 and 174 can be used, the memory area 171 having the smaller number is used as the memory area for storing the decoded image data, and the pointer value “1” is stored in the register RP. Next, in step S27, decoding processing for the picture layer and below is performed, and the P8 image data is reproduced using the P7 image data in the memory area 173 indicated by the pointer value "3" of the register FP as a forward reference image. Is stored in the memory area 171 indicated by the pointer value “1” of the register RP.

Similarly, the registers RP to RP are set in accordance with the picture type of the image to be decoded and the output order of the display image.
While changing the DP pointer value, specify the memory area for storing the decoded image data, the front reference image, the rear reference image, and the memory area for storing the image data used as the display image, and execute the decoding process. Is what you do.

Next, a method of synchronizing the decoding processing with the display on the display according to the flowchart shown in FIG. 2 will be described.

Video controller of decoding apparatus shown in FIG.
15 detects the beginning of the frame using the vertical synchronization signal and the horizontal synchronization signal from the external display as described above, and generates an interrupt signal INT generated at the beginning of the frame.
Is generated and output to the sequencer 16. Sequencer
16 starts the decoding process by receiving this interrupt signal. The decoding process starts from reading out the compressed image data from the FIFO 10 shown in FIG. 1 and inputting it to the variable length decoder 11, performs the decoding process for each MPEG layer, and the decoding process for the picture layer is shown in FIG. It ends by performing according to the flow.

However, the sequencer 16 masks the interrupt due to the interrupt signal during the processing between steps S11 and S12 shown in FIG. 2, and accepts the interrupt after entering the processing of step S27. If an interrupt signal has not been sent from the video controller 15 even after completing the processing in step S27, the sequencer 16 waits for the next interrupt signal to start decoding the frame. in this way,
Since the sequencer 16 always receives the interrupt from the video controller 15 after the processing in step S27, the decoding timing and the display timing can be synchronized.

When the sequencer 16 receives the interrupt, the sequencer 16 sends an interrupt acceptance signal ACK notifying the acceptance to the video controller 15 and the video controller 15
Cancels the interrupt signal being output. The decoding process is performed during the blanking period of the vertical synchronizing signal of the display, and the display image is read after the decoding process of the picture layer and the end of the blanking period in step S27 shown in FIG.

Next, the processing in the case where the decoding processing cannot be performed within one frame time will be described with reference to FIG.

Since the decoding device is set so that the decoding process of one frame of image data can be completed within the time of one frame, an interruption is made to match the timing of the decoding process with the display timing. Except for the initial state, it usually occurs after the processing up to step S27 shown in FIG. 2 is completed. However, if a situation occurs where the decoding process does not end within the time of one frame, an interrupt is generated in the process of step S27. In such a case, the sequencer 16 performs subsequent decoding processing according to the flowchart shown in FIG.

First, in step 31, the picture type of the image currently being decoded is checked, and if the picture type is the B type, the flow proceeds to step S32. In step S32, the decoding process for the frame is forcibly terminated in consideration that the lack of the B-type image does not affect the subsequent decoding process. Then, when the head of the next frame is detected in the next step S33, the decoding process is restarted according to the flow of FIG. However, in this case, since the decoding process has been completed in step S32 and there is no display image, the process of step S20 shown in FIG. 2 is not performed.

If it is determined in step S31 that the picture type of the image currently being decoded is the I or P type, the flow advances to step S35. In step S35, the decoding process for the frame is continuously executed in consideration of the fact that the I or P type image data is required as a reference image in the subsequent decoding process. However, if another interruption (two interruptions during the decoding of one frame) occurs during the decoding of the frame, the decoding is forcibly terminated. Then, the decoding process is restarted after detecting the next type I image data. In this way, the synchronization between the decoding timing and the display timing is restored.

As described above, according to the present embodiment, a memory area for four screens is provided in the image memory 17 and the display timing is completely delayed by one frame from the decoding timing, so that the decoding processing time is reduced. Even if the predetermined time is exceeded, no disturbance of the displayed image or failure of the decoding process occurs.

Further, according to the present embodiment, the decoding process is started by the interrupt signal based on the display timing, and the display timing and the decoding timing are synchronized.
It is not necessary to constantly monitor the image display position and the decoded image position, which has been conventionally performed, and the processing efficiency of the sequencer can be increased accordingly. Further, it is not necessary to provide the performance of each processing block more than necessary. simplification,
The size can be reduced.

According to the present embodiment, if the decoding process cannot be completed within one frame time,
Since the decoding process can proceed by a predetermined exception process, even if an error occurs in the compressed image data to be decoded, the decoding process stops or the display image stops as in the related art. It will not be disturbed. As described above, by detecting the frame synchronization of the display by the interrupt signal and changing the processing sequence in accordance with the state of the sequencer 16 at that time, it is possible to perform fine error processing control.

Next, a description will be given of a second embodiment of the decoding apparatus according to the present invention. This decoding device counts pulses synchronized with the frame of the display, and when the count value is incremented, starts the decoding process to synchronize the decoding process with the display. By reading out the display image completely one frame later, it is possible to prevent the image from being disturbed due to the delay of the decoding process.

FIG. 5 is a block diagram showing a configuration of the decoding apparatus. In FIG. 5, the video controller 35
The head of the frame is detected by using the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC of the display input from the input ports 40 and 41, and the number of frames is counted. The sequencer 36 monitors the count value via the control bus 38, and synchronizes the decoding timing with the display timing. The registers RP, FP, B
Includes registers FPD and BIPD in addition to P and DP. The decoding apparatus of the present embodiment differs from the decoding apparatus of the first embodiment shown in FIG. 1 in these points, but is the same in other points.

Next, a decoding method in the decoding apparatus will be described in detail with reference to FIGS. Here, FIG.
The decoding method, in particular, the memory area 371 of the image memory 37
374 is a flowchart showing the switching algorithm, and the processing in each step except for step S54 is executed by the sequencer 36 shown in FIG. FIG. 7 is a time chart showing a sequence of image display according to this algorithm, in which compressed image data is input from the input port 39 of FIG. 5 to picture types I0, P1, B2, B3, P4, B5, P6,
P7, P8 ... are input in this order, and the display image is output from output port 42.
When output in the order of I0, B2, B3, P1, B5, P4, P6,..., Decoded image data, forward predicted image data, backward predicted image data, and display image data are stored in the memory areas 371 to 374 of the image memory 37. Where is stored.

The meaning of each symbol in FIG. 7 is as shown in FIG.
This is the same as the time chart shown in FIG. However, the registers FPD and BIPD are stored in the memory area 371 of the image memory 37.
A register for storing a pointer value indicating ~ 374
The register FPD stores the same pointer value as the pointer value stored in the register FP one frame before, and the register BIPD stores the pointer value indicating the memory area in which the B picture was stored.

First, when decoding the compressed image data corresponding to the first image I0, meaningful values are not set in the registers FP and BP. Therefore, in steps S41 to S52 in the flowchart of FIG. Each process is executed with the value indicated by the value, and the process proceeds to step S53. At this time, register DP
Since no meaningful value is stored in the decoding device, an image having an initial value is output as a display image from the decoding device. In this case, each process in steps S41 to S52
The description is omitted because it does not directly affect the decoding of the next image data.

In step S53, a memory area for storing the decoded image data is determined. At this time, memory area 37
Since 1 to 374 can be used, the memory area 371 having the smaller number is determined as the memory area for storing the decoded image data, and the pointer value "1" is stored in the register RP. Next, in step S54, decoding processing for the picture layer and below is performed, and the decoded image data of I0 is stored in the memory area 371 indicated by the pointer value "1" of the register RP. Since the image data of I0 is of the I type, it is decoded independently of other image data.

Next, when the compressed image data corresponding to the second image P1 is decoded, in steps S41 to S48, the process is executed with the initial value as in the case of the above-described process for the image I0. In the next step S49, the header information of the picture layer is decoded, and in step S50, the picture type of the image data to be decoded this time is checked. Then, since the picture type is the P type, the flow shifts to step S51.
In step S51, the pointer value "1" of the register RP is copied to the register FP. As a result, the image data of I0 stored in the memory area 371 is used as reference image data ahead of the image data to be decoded this time.

In the next step S53, a memory area for storing the decoded image data is determined. At this time, since the memory areas 372 to 374 can be used, the memory area 372 having the smaller number is used as the memory area for storing the decoded image data, and the pointer value “2” is stored in the register RP. Next, in step S54, decoding processing for the picture layer and below is performed, and P1 image data is reproduced using the I0 image data in the memory area 371 indicated by the pointer value "1" of the register FP as a forward reference image. Is stored in the memory area 372 indicated by the pointer value “2” of the register RP.

Next, when decoding the compressed image data corresponding to the third image B2, the picture type of the image decoded one frame before in step S41 is checked. This time, since the picture type is the P type, the flow proceeds to step S42. In step S42, since a meaningful value has not yet been set in the register FPD, the process is performed with the initial value, and the process proceeds to step S43. In step S43, the pointer value "1" of the register FP is copied to the register DP. As a result, the image data of I0 stored in the memory area 371 is output as a display image.

In the next step S44, the pointer value "1" of the register FP is copied to the register FPD, and the routine goes to a step S49. In step S49, the header information of the picture layer is decoded, and in step S50, the picture type of the image to be decoded this time is checked. Since the picture type is the B type, the process proceeds to step S52, where the pointer value "2" of the register RP is copied to the register BP. As a result, the previously decoded P1 image data stored in the memory area 372 is used as reference image data after the currently decoded image data.

In the next step S53, a memory area for storing the decoded image data is determined. At this time, since the memory areas 373 to 374 can be used, the memory area 373 having the smaller number is used as the memory area for storing the decoded image data, and the pointer value “3” is stored in the register RP. Next, in step S54, decoding processing for the picture layer and below is performed, and the image data of I0 in the memory area 371 indicated by the pointer value "1" of the register FP as the forward reference image, and the pointer value of the register BP as the backward reference image. "2"
The image data of B2 is reproduced using the image data of P1 in the memory area 372 indicated by, and this is stored in the pointer value of the register RP.
3 "is stored in the memory area 373.

Next, when decoding the compressed image data corresponding to the fourth image B3, the picture type of the image decoded one frame before is checked in step S41. This time, since the picture type is the B type, the flow proceeds to step S45. However, in step S45, since the value of the register BIPD is still the initial value, the process is executed with the value indicated by the initial value, and the process proceeds to the next step S46. In step S46, the register RP
Is copied to the register DP. Thus, the image data of B2 stored in the memory area 373 is output as a display image.

In the next step S47, the pointer value "3" of the register RP is copied to the register BIPD. This allows
The pointer value of the register BIPD indicates the memory area 373 in which the previously decoded B-type B2 image data is stored. In the next step S48, the pointer value "2" of the register BP is temporarily copied to the register RP. In step S52, if the picture type of the image to be decoded this time is the B type, the pointer value of the register RP is also stored in the register even if the image decoded one frame before is the B type.
This is because it is configured to copy to BP.

In the next step S49, the header information of the picture layer is decoded, and in step S50, the picture type of the image data to be decoded this time is checked. Since the picture type is the B type, the process proceeds to step S52,
In S52, the pointer value "2" of the register RP is copied to the register BP. As a result, the pointer value "2" temporarily copied from the register BP to the register RP in step S48 is copied to the register BP, and the image data of P1 stored in the memory area 372 is changed to the image of B3 to be decoded this time. It will be used as reference image data ahead of the data.

In the next step S53, a memory area for storing the decoded image data is determined. At this time, since only the memory area 374 can be used, the memory area 374 is used as a memory area for storing decoded image data, and the pointer value “4” is stored in the register RP. Then step
In S54, the decoding process for the picture layer and below is performed, and the pointer value "1" of the register FP is set as the forward reference image.
The image data of B2 is reproduced by using the image data of I0 in the memory area 371 indicated by using the image data of P1 in the memory area 372 indicated by the pointer value “2” of the register BP as the subsequent reference image, and this is stored in the register RP Is stored in the memory area 374 indicated by the pointer value "4".

Next, when decoding the compressed image data corresponding to the fifth image B3, in step S41, the picture type of the image decoded one frame before is checked. This time, since the picture type is the B type, the flow proceeds to step S45. In step S45, the pointer value “3” of the register BIPD
Since the image data of the B-type image B2 stored in the memory area 373 indicated by is not used in the future, a process for allowing the memory area 373 to be updated is performed. This allows
The memory area 373 is in a usable state. In the next step S46, the pointer value "4" of the register RP is
Copy to As a result, the image data of B3 stored in the memory area 374 is output as a display image.

In the next step S47, the pointer value "4" of the register RP is copied to the register BIPD. This allows
The pointer value of the register BIPD is stored in the memory area 37 in which the image data of the previously decoded B-type image B3 is stored.
4 will be shown. In step S48, the pointer value "2" of the register BP is temporarily copied to the register RP. Next, in step S49, the header information of the picture layer is decoded, and in step S50, the picture type of the image data to be decoded this time is checked. Since the picture type is the P type, the process moves to step S51, and in step S51,
Copy the pointer value "2" of the register RP to the register FP. As a result, P1 stored in the memory area 372 is
Will be used as reference image data ahead of the P4 image data to be decoded this time.

In the next step S53, a memory area for storing the decoded image data is determined. At this time, step 45
Since only the memory area 373 that is allowed to be updated in step (3) is usable, the memory area 373 is used as a memory area for storing decoded image data, and the pointer value “3” is stored in the register RP. In step S54, decoding processing for the picture layer and below is performed, and P4 image data is reproduced using the P1 image data in the memory area 372 indicated by the pointer value "2" of the register FP as a forward reference image, and this is stored in the register. The data is stored in the memory area 373 indicated by the pointer value "3" of the RP.

Next, when decoding the compressed image data corresponding to the sixth image B5, the picture type of the image decoded one frame before in step S41 is checked. This time, since the picture type is the P type, the flow proceeds to step S42. In step S42, the pointer value "1" of the register FPD
Since the image data of I0 stored in the memory area 371 indicated by is not used thereafter, a process for allowing the memory area 371 to be updated is performed. As a result, the memory area 371 can be used. In step S43,
Copy the value “2” of the register FP to the register DP. As a result, the image data of P1 stored in the memory area 372 is output as a display image.

In the next step S44, the value of the register FP
2 "is copied to the register FPD. Thus, the pointer value of the register FPD indicates the memory area 372 in which the image data of P1 which has become the previous reference image data in the previous frame is stored. In step S49, the header information of the picture layer is decoded, and in step S5
At 0, the picture type of the image data to be decoded this time is checked. Since this picture type is B type, step
The process moves to S52, and in step S52, the pointer value "3" of the register RP is copied to the register BP. As a result, the P4 image data stored in the memory area 373 is used as reference image data after the B5 image data to be decoded this time.

In the next step S53, a memory area for storing the decoded image data is determined. At this time, step 42
Since only the memory area 371 that is allowed to be updated in step (1) can be used, the memory area 371 is used as a memory area for storing decoded image data, and the pointer value “1” is stored in the register RP. In the next step S54, decoding processing for the picture layer and below is performed, and the register FP is used as a forward reference image.
The image data of P1 in the memory area 372 indicated by the pointer value "2" of the register BP is used as the subsequent reference image by using the image data P4 of the memory area 373 indicated by the pointer value "3" of the register BP.
The image data of B5 is reproduced and stored in the memory area 371 indicated by the pointer value "1" of the register RP.

Next, when decoding the compressed image data corresponding to the seventh image P6, the picture type of the image decoded one frame before in step S41 is checked. This time, since the picture type is the B type, the flow proceeds to step S45. In step S45, the pointer value "4" of the register BIPD
Is performed to allow the update of the memory area 374 indicated by. As a result, the memory area 374 becomes usable. In the next step S46, the pointer value "1" of the register RP is copied to the register DP. As a result, the memory area 371
Is output as a display image.

In the next step S47, the pointer value "1" of the register RP is copied to the register BIPD, and the process proceeds to step S48.
Then, the pointer value "3" of the register BP is temporarily copied to the register RP, and the routine goes to Step S49. In step S49, the header information of the picture layer is decoded, and in step S5
At 0, the picture type of the image data to be decoded this time is checked. Since this picture type is P type,
In S51, the pointer value "3" of the register RP is copied to the register FP. As a result, the P4 image data stored in the memory area 373 is used as reference image data ahead of the P6 image data to be decoded this time.

In the next step S53, a memory area for storing the decoded image data is determined. At this time, step 45
Since only the memory area 374 that is allowed to be updated in step (1) is usable, the memory area 374 is used as a memory area for storing decoded image data, and the pointer value “4” is stored in the register RP. In the next step S54, decoding processing for the picture layer and below is performed, and the register FP is used as a forward reference image.
The image data of P6 is reproduced using the image data of P4 in the memory area 373 indicated by the pointer value "3", and this is stored in the register.
It is stored in the memory area 374 indicated by the pointer value "4" of the RP.

Next, when decoding the compressed image data corresponding to the eighth image P7, in step S41, the picture type of the image decoded one frame before is checked. This time, since the picture type is the P type, the flow proceeds to step S42. In step S42, the pointer value "2" of the register BIPD
Is performed to allow the updating of the memory area 372 indicated by. As a result, the memory area 372 can be used. In the next step S43, the value “3” of the register FP is
Copy to As a result, the P4 image data stored in the memory area 373 is output as a display image.

In step S44, the value "3" of the register FP is copied to the register FPD, and the flow advances to the next step S49. In step S49, the header information of the picture layer is decoded, and in step S50, the picture type of the image data P7 to be decoded this time is checked. Since the picture type is the P type, the process moves to step S51, where the pointer value "4" of the register RP is copied to the register FP. As a result, the P6 image data stored in the memory area 374 is used as reference image data ahead of the P7 image data to be decoded this time.

In the next step S53, a memory area for storing the decoded image data is determined. At this time, step 42
Since only the memory area 372 which is allowed to be updated in the above step is usable, the memory area 372 is used as a memory area for storing the decoded image data, and the pointer value “2” is stored in the register RP. Next, in step S54, decoding processing for the picture layer and below is performed, and P6 of the memory area 374 indicated by the pointer value "4" of the register FP as a forward reference image is processed.
The image data of P7 is reproduced by using the image data of (1) and stored in the memory area 372 indicated by the pointer value "2" of the register RP.

Next, when the compressed image data corresponding to the ninth image P8 is decoded, the picture type of the image decoded one frame before in step S41 is checked. This time, since the picture type is the P type, the flow proceeds to step S42. In step S42, the pointer value "3" of the register BIPD
Is performed to allow the updating of the memory area 373 indicated by. As a result, the memory area 373 can be used. In the next step S43, the value “4” of the register FP is
Copy to As a result, the P6 image data stored in the memory area 374 is output as a display image.

In the next step S44, the value of the register FP
4 "is copied to the register FPD, and the process proceeds to the next step S49. In step S49, the header information of the picture layer is decoded, and in step S50, the picture type of the image data to be decoded this time is checked. Therefore, the process proceeds to step S51, where the pointer value "2" of the register RP is copied to the register FP.
Thus, the P7 image data stored in the memory area 372 is used as reference image data ahead of the P8 image data to be decoded this time.

In the next step S53, a memory area for storing the decoded image data is determined. At this time, step 42
Since only the memory area 373 that is allowed to be updated in step (3) is usable, the memory area 373 is used as a memory area for storing decoded image data, and the pointer value “3” is stored in the register RP. In the next step S54, decoding processing for the picture layer and below is performed, and the P8 image data is reproduced using the P7 image data in the memory area 372 indicated by the pointer value "2" of the register FP as a forward reference image. The register RP
Is stored in the memory area 373 indicated by the pointer value "3".

In the same manner, the registers RP and RP are set according to the picture type of the picture to be decoded and the output order of the display picture.
Specify the memory area for storing the decoded image data while changing the pointer values of FP, FPD, BP, DP, and BIPD, and the memory area for storing the image data used as the forward reference image, the backward reference image, and the display image. , And performs a decryption process.

As described above, the decoding algorithm of the first embodiment has the steps shown in the flowchart of FIG.
This method frees up all memory areas that store image data that is not used in subsequent frame decoding processing by the processing in step 26, eliminating the need to use the registers FPD and BIPD. The algorithm becomes complicated. On the other hand, in the decoding algorithm of the second embodiment, as shown in the flowchart of FIG. 6, a pointer value indicating a memory area in which image data not used in a decoding process of a subsequent frame is stored is registered.
This is a method of storing the decoded image data in the FPD or BIPD by updating the memory area indicated by the pointer value at the beginning of the decoding processing of the next frame, and the two registers FPD and BIPD , But the overall algorithm is simplified. It should be noted that the decoding device of the configuration shown in FIG. 5 can also realize the decoding process of the flowchart shown in FIG.

Next, a description will be given of a method of synchronizing the decoding processing with the display on the display according to the flowchart shown in FIG.

Video controller of decoding apparatus shown in FIG.
As described above, 35 detects the head of the frame using the vertical synchronization signal and the horizontal synchronization signal from the external display, generates a pulse generated at the head, and counts the pulse by the internal counter. On the other hand, the sequencer 36 monitors the count value of its internal counter,
The head of the frame is detected by detecting that the count value is incremented, and the decoding process is started. The decoding process starts from reading out the compressed image data from the FIFO 30 shown in FIG. 5 and inputting it to the variable length decoder 31. The decoding process of each layer of MPEG is performed, and the decoding process of the picture layer is shown in FIG. It ends by performing according to the flow.

The sequencer 36 determines in step S54 shown in FIG.
When the processes up to the end are completed, the count value A of the internal counter of the video controller 35 at the end time is compared with the count value B at the time when the decoding process is started. When the count values A and B at the same time are the same, the decoding process has been completed within one frame. Start.
In this way, the decoding timing of the compressed image data is synchronized with the display timing of the display.

Next, the processing in the case where the decoding processing cannot be performed within one frame time will be described with reference to FIG.

Since the decoding apparatus is set so that the decoding of one frame of image data can be completed within the time of one frame, except for the initial state in which the decoding timing and the display timing are matched, Normally, after the processing up to step S54 shown in FIG. 6 is completed, the count value of the internal counter in the video controller 35 is incremented. However, if a situation occurs where the decoding process does not end within the time of one frame, step S5
Since the count value is incremented before the processing of step 4 is completed, the relationship between the decoding processing and the display timing is confused.

In such a case, the sequencer 36 performs the subsequent decoding processing according to the flowchart shown in FIG. First, when the processing up to step S54 shown in FIG. 6 is completed, in step 61 shown in FIG. 8, the difference between the count value A at the time when the decoding processing is completed and the count value B at the time when the decoding processing is started is calculated. Is checked, and if the difference is 1, the process proceeds to step S62. Step S62
Then, the picture type of the image to be decoded next is checked. If the picture type is the B type, the flow proceeds to step S63. If the picture type is the I type or the P type, the flow proceeds to step S64.

In step S63, the decoding process is not performed on the next image (B type), considering that the lack of the B type image does not affect the subsequent decoding process.
In step S64, considering that the I-type or P-type image data is required as a reference image in the subsequent decoding processing, the next image (I-type or P-type image data) is considered.
Type) decryption processing. In step S61,
If the difference between the count values A and B is 2 or more, the process moves to step S65. In step S65, input of an I-type image is monitored, and when an I-type image is detected, the decoding process is restarted. In this way, the synchronization between the decoding timing and the display timing is restored.

As described above, according to the present embodiment, a memory area for four screens is provided in the image memory 37, and the display timing is completely delayed by one frame from the decoding timing. Even if the predetermined time is exceeded, no disturbance of the displayed image or failure of the decoding process occurs.

Further, according to this embodiment, the value of the frame counter which is incremented at the beginning of the frame is monitored, and when the value is incremented, the decoding process is started. Synchronization eliminates the need for constant monitoring of the image display position and the decoded image position, which has conventionally been required, and the processing efficiency of the sequencer can be increased accordingly. Since it is not necessary, the circuit can be simplified and downsized.

According to the present embodiment, if the decoding process cannot be completed within one frame time,
Since the decoding process can proceed by a predetermined exception process, even if an error occurs in the compressed image data to be decoded, the decoding process stops as in the case of the related art, or the displayed image stops or is disturbed. I will not do it.

Further, in this embodiment, since the sequencer 36 is configured to monitor the frame count value, the processing routine for interruption as in the first embodiment is not required, and the entire circuit configuration is simplified. The effect that the sequence of the software for the overall control used in the sequencer 36 is simple and the number of steps is reduced can be expected.

FIG. 9 is a block diagram showing a configuration of a decoding apparatus according to the third embodiment of the present invention. This decryption device
The decoding device of the first embodiment shown in FIG.
U), the variable length decoder 11, the decoding operation unit 12, and the memory controller 13 shown in FIG.
Function is realized by software of the CPU 55, the FIFO 10 and the image memory 17 shown in FIG. 1 are allocated to the memory space of the memory 52 managed by the CPU 55, and when the compressed image data is input to the input port 57, the DMA controller 52 The right to use the CPU bus 56 is acquired, and image data is written directly to the memory space of the memory 52 corresponding to the FIFO 10 shown in FIG.

The video controller 54 operates in substantially the same manner as the video controller 15 shown in FIG. 1, and receives a vertical synchronizing signal and a horizontal synchronizing signal input from an external display via input ports 58 and 59. A signal notifying the beginning of the frame of the display image is generated using the signal, and the signal is transmitted to the CPU 55 through the control line 61 as an interrupt signal INT. When the CPU 55 receives the interrupt signal, it starts the decoding process, and notifies the video controller 54 of an interrupt acceptance signal ACK for notifying the reception via the CPU bus 56. As a result, the video controller 54 releases the interrupt.

When the video controller 54 wants to obtain display image data, it sends a request signal to the DMA controller 51 to acquire the right to use the CPU bus 56, and displays the unit of the unit directly through the CPU bus 56. The image data (for example, data for one line) is temporarily transferred to the FIFO 53, the image data is read out from the FIFO 53 in synchronization with the image display timing, and is output to an external display via the output port 60. .

Note that the decoding apparatus of the second embodiment shown in FIG. 5 can also be realized using a CPU.

[0111]

As described above, according to the present invention, a memory area for four screens is provided in the image memory, and the display timing is completely delayed by one frame from the decoding processing timing. Is longer than a predetermined time, it is possible to expect an effect that the disturbance of the display image and the failure of the decoding process do not occur.

Further, since the decoding timing is synchronized with the display timing by starting the decoding process based on the display timing of the display, it is not necessary to constantly monitor the image display position and the decoded image position which have been conventionally performed. Thus, the processing efficiency of the sequencer can be increased accordingly, and the performance of each processing block does not need to be increased more than necessary, so that the circuit can be simplified and downsized.

Further, since an exception process is provided in advance to deal with the case where the decoding process cannot be completed within the time of one frame, even if an error occurs in the compressed image data to be decoded, the decoding process can be stopped, It is possible to prevent the display image from being stopped or from being disturbed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a decoding device according to a first embodiment.

FIG. 2 is a flowchart illustrating an algorithm of a decoding method according to the first embodiment.

FIG. 3 is a time chart showing a sequence of image display according to the algorithm of FIG. 2;

FIG. 4 is a flowchart illustrating exception processing when decoding processing is not completed within one frame in the decoding method according to the first embodiment.

FIG. 5 is a block diagram illustrating a configuration of a decoding device according to a second embodiment.

FIG. 6 is a flowchart illustrating an algorithm of a decoding method according to the second embodiment.

FIG. 7 is a time chart showing a sequence of image display according to the algorithm of FIG. 6;

FIG. 8 is a flowchart illustrating exception processing when decoding processing is not completed within one frame in the decoding method according to the second embodiment.

FIG. 9 is a block diagram illustrating a configuration of a decoding device according to a third embodiment.

FIG. 10 is an explanatory diagram showing the order of encoding processing, the order on media, the order of decoding processing, and the order of display images in MPEG encoding.

[Explanation of symbols]

 10, 14, 30, 34, 53 FIFO 11, 31 Variable length decoder 12, 32 Decoding arithmetic unit 13, 33 Memory controller 15, 35, 54 Video controller 16, 36 Sequencer 17, 37 Image memory 51 DMA controller 52 Memory 55 CPU

Claims (7)

[Claims] 1. An image data decoding apparatus for decoding image data obtained by encoding and compressing continuous frame images,
The apparatus includes: an image memory having a memory area for storing decoded image data, forward predicted image data, backward predicted image data, and display image data; reading predetermined image data from the image memory to perform decoding processing; Decoding processing means for storing the decoded image data in a predetermined memory area of the image memory, reading and outputting the decoded image data as display image data after one frame, and inputting a vertical synchronizing signal and a horizontal synchronizing signal. Generating means for generating an interrupt signal synchronized with the beginning of a frame based on the signal; control means for monitoring the interrupt signal and controlling the decoding means to start a decoding process when the interrupt signal is detected; An image data decoding device comprising: 2. The apparatus according to claim 1, wherein said control means, when detecting said interrupt signal before the decoding processing of one frame by said decoding processing means is completed, sets a picture type of said frame. A second step of forcibly terminating the current decoding process and starting a decoding process of the next frame when the picture type checked in the first process is the B type. A third step of continuing the current decoding process when the picture type checked in the first step is the I or P type; and a third step before the decoding process of the third step ends. When the interrupt signal is detected, the current decoding process is forcibly terminated, and when image data of the picture type I is input, the decoding process of the image data is performed after the detection of the interrupt signal. Open Image data decoding apparatus and executes a fourth step of. 3. The apparatus according to claim 3, wherein the second step is a step of forcibly terminating the current decoding process and performing the decoding process of the next frame when the decoding process of the next frame is forcibly terminated. An image data decoding device which does not output the obtained B-type image data as display image data. 4. An image data decoding device for decoding image data obtained by encoding and compressing continuous frame images,
The apparatus includes: an image memory having a memory area for storing decoded image data, forward predicted image data, backward predicted image data, and display image data; reading predetermined image data from the image memory to perform decoding processing; Decoding processing means for storing the decoded image data in a predetermined memory area of the image memory, reading and outputting the decoded image data as display image data after one frame, and inputting a vertical synchronizing signal and a horizontal synchronizing signal. Counting means for generating a pulse synchronized with the beginning of the frame based on the signal and counting the pulse, monitoring a count value in the counting means, and controlling the decoding means when the count value is incremented. Control means for starting a decoding process. 5. The apparatus according to claim 4, wherein the control means detects a difference between the count value at the start and the end of the decoding process, and detects the difference at the first step. When the difference is 1, the picture type of the frame to be processed next is checked. When the picture type is the B type, the decoding process of the frame is terminated. When the picture type is the I or P type, the frame is And if the difference detected in the first step is 2 or more, and the picture type is I-type image data, the count value is incremented. And a fourth step of starting the decoding process of the image data after waiting for the image data. 6. An image data decoding method in an image data decoding device for decoding image data obtained by encoding and compressing continuous frame images, the method comprising: storing four frame images provided in the image data decoding device. An image memory having an available memory area, a first register storing a pointer value indicating a memory area storing image data to be decoded, and a pointer indicating a memory area storing image data used as forward prediction image data A second register for storing a value, and a third register for storing a pointer value indicating a memory area in which image data used as backward prediction image data is stored.
And a fourth register for storing a pointer value indicating a memory area in which image data used as a display image is stored, and an image stored in the memory area indicated by the pointer value of the fourth register. A first step of checking the picture type of the data; and a second step of permitting updating of the memory area indicated by the pointer value of the fourth register when the picture type checked in the first step is the B type. When the picture type checked in the first step is the I or P type and the pointer values of the third register and the fourth register are the same, the memory area indicated by the pointer value of the fourth register If the picture type is I or P type but the pointer values of the third register and the fourth register are not the same, the next A third step of checking the picture type of the image data stored in the memory area indicated by the pointer value of the first register, following the second and third steps; If the picture type checked in the fourth step is the B type, the pointer value of the first register is copied to the fourth register, and the picture layer of the image to be decoded this time is decoded to change the picture type. A fifth step of checking; and if the picture type checked in the fifth step is the B type, the process proceeds to the next step. If the picture type is the I or P type, a pointer of the second register is used. The update of the memory area indicated by the value is permitted, and the third
A sixth step of copying the pointer value of the second register to the second register; and if the picture type checked in the fourth step is the I or P type, the pointer value of the second register is changed to the fourth value.
A seventh step of decoding the picture layer of the image to be decoded this time and examining the picture type, and when the picture type examined in the seventh step is the B type, the first step is performed. The pointer value of the register is copied to the third register. When the picture type is I or P type, the pointer value of the second register is copied to the third register, and the point value of the first register is copied. In the first register, and following the sixth and eighth steps, write a pointer value indicating one of the unused memory areas in the first register. By sequentially performing the steps of
The memory area storing the forward predicted image data, the backward predicted image data, the display image data, and the memory area storing the image data to be decoded are determined, and the decoding processing of the picture layer or less is performed, so that the image data of one frame is obtained. And decoding the image data. 7. An image data decoding method in an image data decoding device for decoding image data obtained by encoding and compressing continuous frame images, the method comprising: storing four frame images provided in the image data decoding device. An image memory having an available memory area, a first register storing a pointer value indicating a memory area storing image data to be decoded, and a pointer indicating a memory area storing image data used as forward prediction image data A second register for storing a value, a third register for storing the same pointer value as the pointer value stored in the second register, and image data used as backward prediction image data are stored. A fourth register for storing a pointer value indicating a memory area, and an image used as a display image A fifth register for storing a pointer value indicating a memory area for storing data, and a sixth register for storing the same pointer value as the pointer value stored in the first register. A first step of checking the picture type of the image data stored in the memory area indicated by the pointer value of the register, and a third step when the picture type checked in the first step is the I or P type. A second step of allowing the memory area indicated by the pointer value of the register to be updated and copying the pointer value of the second register to the third register and the fifth register; and checking in the first step. When the picture type is the B type, the memory area indicated by the pointer value of the sixth register is allowed to be updated, and the pointer value of the first register is changed to the fifth register and the sixth register. While copying to the register,
A third step of copying the pointer value of the fourth register to the first register; and following the second and third steps, decoding the picture layer of the image to be decoded this time to check the picture type, When the picture type is I type or P type, the pointer value of the first register is copied to the second register. When the picture type is B type, the pointer value of the first register is copied to the second register. Sequentially executing a fourth step of copying data to a register of No. 4 and a fifth step of writing a pointer value indicating a memory area permitted to be updated in the first register following the fourth step. By the forward prediction image data,
Determining a memory area in which backward prediction image data, display image data is stored, and a memory area in which image data to be decoded is stored, and decoding one frame of image data by performing decoding processing of a picture layer or less. Characteristic image data decoding method.