JPH10253394A - Differential input circuit - Google Patents

Abstract

(57) Abstract: The present invention relates to a differential input circuit that takes in an output appearing at both ends of a sensor as a reverse-phase signal and processes the same, and realizes a function of determining a bias point while reducing an infinite input impedance. The purpose is to generate. A terminal of a sensor is connected to a signal line.
8, 55. The resistor 30 and the first current source 34 are connected to the signal line 28. The resistor 30 is connected to the reference voltage line 32. The resistor 56 and the second current source 58 are connected to the signal line 55. The resistor 56 is grounded to the ground line. The resistance value R3 of the resistor 30 and the resistance value R4 of the resistor 56 are both set to a predetermined value R. The current I1 equal to the current I4 flowing through the resistor 56 flows through the first current source 34.
A current I2 equal to the current I3 flowing through the resistor 30 flows through the second current source 58.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a differential input circuit, and more particularly, to a differential input circuit that receives and processes an output appearing at both ends of a device such as a sensor as an inverted phase signal.

[0002]

2. Description of the Related Art Conventionally, for example, Japanese Patent Application Laid-Open No. 8-2651
As disclosed in Japanese Patent No. 17, a differential input circuit is known which takes in an output appearing at both ends of a sensor as an inverted phase signal and processes it. FIG. 8 shows a circuit diagram of a main part of a conventional differential input circuit. The sensor 10 is connected to the differential input circuit shown in FIG. The sensor 10 includes an output generator 12 and internal resistance generators 14 and 16.

[0005] The output generator 12 generates a potential difference Vi between both ends according to the state of an object to be detected. The internal resistance generators 14 and 16 generate “RS / 2” resistances corresponding to half of the internal resistance RS of the sensor 10 on both sides of the output generator 12. The internal resistance generators 14 and 16 are connected to output terminals 18 and 20 of the sensor 10, respectively.
In the following description, the internal resistance generating units 14 and 1
When it is necessary to distinguish between the resistance values generated by 6, the resistance value of the internal resistance generation unit 14 is referred to as R1 and the resistance value of the internal resistance generation unit 16 is referred to as R2.

When signals output from the output terminals 18 and 20 of the sensor 10 are received by a differential input circuit,
Needs to be determined. Therefore, the conventional differential input circuit includes a bias circuit including resistors 22 and 24 and a reference power supply 26. Resistor 2
2 and one end of the resistor 24 are connected to output terminals 18 and 20 of the sensor 10, respectively. Also,
The other end of the resistor 22 and the other end of the resistor 24 are both connected to a reference power supply 26.

[0005] The resistors 22 and 24 both generate a resistance of a predetermined value R. Further, the reference power supply 26 has a predetermined value Vre.
Generate a reference voltage of f. In the following description, when it is necessary to distinguish the resistance values generated by the resistors 22 and 24, the resistance value of the resistor 22 is referred to as R3 and the resistance value of the resistor 24 is referred to as R4. As shown in FIG.
Assuming that a voltage generated at one end of the output terminal 2 is a generated voltage VS1 and a voltage generated at the other end is a generated voltage VS2,
The relationship expressed by the following equation is established between the potential difference Vi, the reference voltage Vref, and the generated voltages VS1 and VS2 at which the voltage 2 occurs.

Vi = VS1-VS2 (1) VS1-Vref = Vref-VS2 (2) When these are arranged, the generated voltages VS1 and VS2 are
Each can be represented as the following equation. VS1 = Vref + Vi / 2 (3) VS2 = Vref-Vi / 2 (4) In the above equations (3) and (4), both the generated voltages VS1 and VS2 are centered on the reference voltage Vref. Represents that the amplitude is half (Vi / 2) of the potential difference Vi and the phases are opposite to each other. As described above, according to the circuit shown in FIG. 8, the generated voltages VS1 and VS2 generated at both ends of the output generating section 12 can be made to have the opposite phases around the reference voltage Vref. In this case, by detecting the difference between the generated voltages VS1 and VS2, the state of the detected object can be accurately detected.

[0007]

However, the sensor 10 has an internal resistance as described above. For this reason, in the circuit shown in FIG. 8, the generated voltages VS1 and VS2 generated at both ends of the output generation unit 12 cannot be directly taken out as the output voltage of the sensor 10. Hereinafter, the output voltages appearing at the output terminals 18 and 20 of the sensor 10 are referred to as output voltages VIN1 and VIN2, respectively, as shown in FIG.

In the circuit shown in FIG. 8, the output voltage VIN1 appearing at one terminal 18 of the sensor 10 is, specifically, the differential pressure between the generated voltage VS1 and the reference voltage Vref is represented by R3.
And R1 are added to the reference voltage Vref, that is, a value represented by the following equation (5). Also,
Output voltage VIN2 appearing at the other terminal 20 of the sensor 10
Calculates the differential pressure between the generated voltage VS2 and the reference voltage Vref as R4
And R2 are subtracted from the reference voltage Vref, that is, a value represented by the following equation (6).

VIN1 = Vref + (Vi / 2) · {R3 / (R3 + R1)} (5) VIN2 = Vref− (Vi / 2) · {R4 / (R4 + R2)} (6) , when the potential difference Vi generated across the output generating unit 12 is changed in amplitude V _0, the generated voltage VS1 and VS
2 (curves shown by broken lines or two-dot chain lines in FIG. 9), and output voltages VIN1 and VIN1.
2 shows the changes (curves indicated by solid lines and dashed lines in FIG. 9).

As shown in the above equations (3) to (6) and FIG. 9, the amplitudes of the output voltages VIN1 and VIN2 of the sensor 10 are equal to the amplitudes of the generated voltages VS1 and VS2 generated from the output generation unit 12. It is attenuated in comparison. As described above, according to the conventional circuit shown in FIG. 8, the generated voltages VS1 and VS2 generated at both ends of the output generating unit 12 are converted into the output voltages VIN1 and VI of the sensor 10.
As N2, it could not be taken out as it was.

[0011] The present invention has been made in view of the above points, and has a substantially infinite input impedance.
It is an object of the present invention to provide a differential input circuit capable of directly taking out a voltage generated by a sensor as an output voltage.

[0012]

The above object is achieved by the present invention.
In a differential input circuit for receiving signals at a first input terminal and a second input terminal, a first reference voltage generating means for generating a first reference voltage; Reference voltage generating means for generating a low-voltage second reference voltage, and a first resistor having a predetermined resistance value and interposed between the first input terminal and the first reference voltage generating means When,
A second resistor having a predetermined resistance value and interposed between the second input terminal and the second reference voltage generating means;
A first current source connected to an input terminal and allowing a current equal to the current flowing through the second resistor to flow out from the first input terminal side; and a current connected to the second input terminal and flowing through the first resistor. And a second current source that causes a current equal to the above to flow into the second input terminal side.

In the present invention, the first input terminal and the second input terminal
Devices that generate a potential difference Vi are connected to both ends of the input terminal. The first input terminal is connected to the first resistor through the first resistor.
A predetermined current IA flows from the reference generating means. Also, the first
A predetermined current IB flows from the input terminal through the first current source. A current IA equal to the current flowing through the first resistor flows into the second input terminal through the second current source. Also,
From the second input terminal to the second reference voltage generating means,
A current IB equal to the current flowing through the first current source flows out.

When the current IA becomes larger than the current IB in a state where the device is connected to the first input terminal and the second input terminal, the current flowing into both the first input terminal and the second input terminal is increased. IA is larger than current IB flowing out. In order to realize such a state, the first
From both the input terminal and the second input terminal, IS = IA-
It is necessary to allow the current represented by IB to flow to the device side.

If the current IA is smaller than the current IB in a state where the device is connected to the first input terminal and the second input terminal, the current flows into both the first input terminal and the second input terminal. Current IA is smaller than current IB flowing out. In order to realize such a state, it is necessary to flow a current represented by IS = IB-IA from the device side to both the first input terminal and the second input terminal.

When the device connected to the first input terminal and the second input terminal requires a balance of the current balance, the current is supplied from both the first input terminal and the second input terminal to the device side. And the device cannot supply current to both the first input terminal and the second input terminal. Therefore, when such a device is connected, the current IA and the current IB are controlled to the same value.

When the current IA and the current IB are controlled to be equal, no current is exchanged between the first input terminal and the device and between the second input terminal and the device. Therefore, in this case, an apparently infinite input impedance is realized in the differential input circuit. When the input impedance of the differential input circuit is infinite, it is possible to accurately detect the voltage generated at both ends of the device without being affected by the internal resistance or the like of the device.

In the present invention, the voltage VIN1 appearing at the first input terminal is expressed by the following equation using the resistance value R of the first resistor, the first reference voltage V _B , and the current IA flowing through the first resistor. It can be expressed as follows. VIN1 = V _B −IA · R On the other hand, under the same situation, the voltage VI appearing at the second input terminal
N2 is a resistance value R of the second resistor, a second reference voltage V _G ,
And it can be expressed as the following equation using the current IB flowing through the second resistor.

VIN2 = V _G + IB · R When a device that requires a balance of the current balance is connected to the first input terminal and the second input terminal, the current IA and the current IB have the same value as described above. Is controlled. Assuming that the value is I, VIN1 and VIN2 can be represented by the following equations.

[0020] _{VIN1 = V B -I · R VIN2} = V G + I · R current I is varied by the potential difference appearing across the device changes. As shown in the above equation, when the current I changes, the voltage VIN1 appearing at the first input terminal and the voltage VIN2 appearing at the second input terminal have the same amplitude and are in opposite phases to each other, that is, a certain reference voltage The phases change opposite to each other as the center.

[0021]

FIG. 1 is a circuit diagram of a differential input circuit according to an embodiment of the present invention. The sensor 10 is connected to the differential input circuit of the present embodiment. The sensor 10 includes an output generation unit 12 that generates a potential difference Vi according to the state of an object to be detected, and internal resistance generation units 14 and 16 having a predetermined resistance value RS / 2. Internal resistance generators 14, 16
Are connected to the output terminal 18 or 20 of the sensor 10, respectively. Hereinafter, when it is necessary to distinguish the resistance values of the internal resistance generating units 14 and 16 from the resistance values of the other resistors, those resistance values are referred to as R1 or R2, respectively.

The terminal 18 of the sensor 10 is connected to a signal line 28. A resistor 30 having a predetermined resistance value R is connected to the signal line 28. A reference voltage line 32 is connected to the resistor 30. Reference voltage line 32
Is supplied with a potential of a predetermined reference voltage 2Vref. Hereinafter, the current flowing through the resistor 30 during the operation of the differential input circuit is referred to as a current I3. When it is necessary to distinguish the resistance value of the resistor 30 from the resistance values of other resistors, the resistance value is referred to as R3.

A first current source 34 is connected to the signal line 28. The other end of the first current source 34 is grounded to a ground line. Hereinafter, during operation of the differential input circuit,
The current flowing into the ground line through the first current source 34 is called a current I1. The signal line 28 is further connected to a non-inverting terminal 38 of an operational amplifier 36. The output terminal 40 and the inverting terminal 42 of the operational amplifier 36 are connected to the base terminal 46 or the emitter terminal 48 of the first transistor 44, respectively. The collector terminal 50 of the first transistor 44 is grounded to a ground line via a terminal indicated by a symbol in FIG. 1 (hereinafter, referred to as a terminal).

The first transistor 44 is a PNP type transistor. The emitter terminal 48 of the first transistor 44 and the inverting terminal 42 of the operational amplifier 36 are connected to the reference voltage line 32 via a resistor 54.
The resistor 54 has a predetermined resistance value R. Hereinafter, when it is necessary to distinguish the resistance value of the resistor 54 from the resistance value of another resistor, the resistance value of the resistor 54 is referred to as R5. Further, a current flowing into the terminal through the first transistor 44 during operation of the differential input circuit is referred to as a current I5.

The other terminal 20 of the sensor 10 is connected to the signal line 5
5 is connected. The signal line 55 has a predetermined resistance value R
Is connected. The resistor 56 is
Grounded to the ground line. Hereinafter, the current flowing into the ground line through the resistor 56 during the operation of the differential input circuit is referred to as a current I4. When it is necessary to distinguish the resistance value of the resistor 30 from the resistance values of the other resistors, the resistance value is referred to as R4.

A second current source 58 is connected to the signal line 55. The reference voltage line 32 is connected to the second current source 58. Hereinafter, the current flowing through the second current source 58 during the operation of the differential input circuit is referred to as a current I2. A non-inverting terminal 62 of the operational amplifier 60 is further connected to the signal line 55. The output terminal 64 and the inversion terminal 66 of the operational amplifier 60 are connected to the base terminal 70 or the emitter terminal 72 of the second transistor 68, respectively. Collector terminal 7 of second transistor 68
Reference numeral 4 is connected to a reference voltage line 32 via a terminal indicated by a symbol in FIG. 1 (hereinafter, referred to as a terminal).

The second transistor 68 is an NPN transistor. The emitter terminal 72 of the second transistor 68 and the inverting terminal 66 of the operational amplifier 60 are grounded via a resistor 78 to a ground line. The resistor 78 has a predetermined resistance value R. Hereinafter, when it is necessary to distinguish the resistance value of the resistor 78 from the resistance value of another resistor, the resistance value of the resistor 78 is referred to as R6. Also, during the operation of the differential input circuit, the second transistor 6
The current flowing into 8 is referred to as current I6.

In this embodiment, the first current source 34 generates a current I1 flowing therethrough during operation of the differential input circuit.
It is configured to have the same value as the current I6 flowing into the second transistor 70. A portion surrounded by a broken line in FIG. 2 is a circuit diagram of the first current source 34 that realizes the above function. That is, the above function is achieved by connecting the terminal shown in FIG.
2 and the terminals and terminals shown in FIG. 1 are connected to the terminals and terminals shown in FIG.

The first current source 34 shown in FIG.
P-type transistors 80 and 82 are provided. The emitter terminal of the transistor 80 and the emitter terminal of the transistor 82 are both connected to the reference voltage line 32.
The base terminal of the transistor 80 and the base terminal of the transistor 82 are connected to each other. The base terminal of the transistor 80 is connected to the terminal together with its collector terminal.

According to the above configuration, one set of transistors 80 and 82 constitutes a current mirror through which the same current flows. Therefore, the current flowing through the transistor 82 is controlled to a value equal to the current flowing through the transistor 80. In the circuit shown in FIG. 2, the current flowing through the transistor 80 is equal to the current flowing from the terminal into the second transistor 68. As described above, the current flowing into the second transistor 68 from the terminal during the operation of the differential input circuit is I6. Therefore, according to the circuit shown in FIG. 2, the current flowing through the transistor 82 during the operation of the differential input circuit is controlled to I6.

The first current source 34 shown in FIG.
N-type transistors 84 and 86 are provided. The emitter terminal of the transistor 84 and the emitter terminal of the transistor 86 are both grounded to the ground line via the terminals. The base terminal of the transistor 84 and the base terminal of the transistor 86 are connected to each other. Also,
The base terminal of the transistor 84 is connected to the collector terminal of the PNP transistor 82 described above together with its collector terminal.

According to the above configuration, one set of transistors 84 and 86 constitutes a current mirror through which the same current flows. Therefore, the current flowing from terminal to terminal through the transistor 86 is controlled to a value equal to the current flowing through the transistor 84. FIG.
In the circuit shown in FIG. 7, the current flowing through the transistor 84 is the current flowing through the transistor 82, that is, the current I
It is the same amount as 6. Therefore, according to the first current source 34 shown in FIG. 2, the current flowing from the terminal to the ground line during the operation of the differential input circuit, that is, the current I1, can be controlled to the same value as the current I6. .

In the present embodiment, the current I2 flowing through the second current source 58 during operation of the differential input circuit is:
It is configured to have the same value as the current I5 flowing through the first transistor 44. A portion surrounded by a broken line in FIG. 3 is a circuit diagram of the second current source 58 that realizes the above function. That is, the above function is achieved by connecting the terminal shown in FIG.
1 and the terminals and terminals shown in FIG. 1 are connected to the terminals and terminals shown in FIG.

The second current source 58 shown in FIG.
N-type transistors 88 and 90 are provided. The emitter terminal of the transistor 88 and the emitter terminal of the transistor 90 are both grounded to a ground line. The base terminal of the transistor 88 and the base terminal of the transistor 90 are connected to each other. The transistor 8
The base terminal 8 is connected to the terminal together with its collector terminal.

According to the above configuration, one set of transistors 88 and 90 constitutes a current mirror for passing the same current. Therefore, the current flowing through the transistor 90 is controlled to a value equal to the current flowing into the transistor 88 from the terminal. In the circuit shown in FIG. 3, the current flowing from the terminal into the transistor 88 is the same as the current flowing through the first transistor 44. Further, as described above, the current flowing through the first transistor 44 during the operation of the differential input circuit is I5. Therefore, according to the circuit shown in FIG. 3, the current flowing through the transistor 90 during the operation of the differential input circuit is controlled to I5.

The second current source 58 shown in FIG.
P-type transistors 92 and 94 are provided. The emitter terminal of the transistor 92 and the emitter terminal of the transistor 94 are both connected to the reference voltage line 32 via the terminals. The base terminal of the transistor 92 and the base terminal of the transistor 94 are connected to each other. Further, the base terminal of the transistor 92 is connected to the collector terminal of the NPN transistor 90 described above together with its collector terminal.

According to the above configuration, one set of transistors 92 and 94 constitutes a current mirror through which the same current flows. Therefore, the current flowing from terminal to terminal through the transistor 94 is controlled to a value equal to the current flowing through the transistor 92. FIG.
In the circuit shown in FIG. 5, the current flowing through the transistor 92 is the current flowing through the transistor 90, that is, the current I
The same amount as 5. Therefore, according to the second current source 58 shown in FIG. 3, during the operation of the differential input circuit, the terminals and the current flowing through the terminals, that is, the current I2 can be controlled to the same value as the current I5.

Next, the operation of the differential input circuit of this embodiment will be described. In the following description, the sensor 10
The voltage appearing at both ends of the output generation unit 12 is generated voltage VS1
And VS2, and the voltages appearing at terminals 18 and 20 of sensor 10 as output voltages VIN1 and VIN2,
The current flowing into the sensor 10 from the terminal 20 and flowing out of the terminal 18 is called a current IS.

In the differential input circuit of this embodiment, the operational amplifier 36, the first transistor 44, and the resistor 54
Is a voltage that controls the current I5 flowing through the first transistor 44 to a value corresponding to the output voltage VIN1 of the sensor 10.
Functions as a current conversion circuit. That is, in the circuit of this embodiment, the operational amplifier 36 and the first transistor 4
4 is a non-inverting terminal 38 and an inverting terminal 42 of the operational amplifier 36.
Operate so as to have the same potential. Therefore, the output voltage VIN1 appears at the emitter terminal of the first transistor 44, similarly to the non-inverting terminal 38 of the operational amplifier 36.

The emitter terminal 48 of the first transistor 44
When the output voltage VIN1 appears at the both ends of the resistor 54, a potential difference represented by 2Vref-VIN1 is generated at both ends of the resistor 54. In this case, the current flowing through the resistor 54, that is, the current I flowing through the first transistor 44 through the resistor 54
5 is controlled to a value represented by the following equation. I5 = (2Vref−VIN1) / R5 (7) Similarly, in the differential input circuit of the present embodiment, the operational amplifier 60, the second transistor 68, and the resistor 78
The current I6 flowing through the second transistor 68 is supplied to the sensor 1
It functions as a voltage-current conversion circuit that controls to a value according to the output voltage VIN2 of 0. That is, in the circuit of the present embodiment, the operational amplifier 60 and the second transistor 68
Operates such that the non-inverting terminal 62 and the inverting terminal 66 of the operational amplifier 60 have the same potential. Therefore, the output voltage VIN2 appears at the emitter terminal of the second transistor 68, similarly to the non-inverting terminal 62 of the operational amplifier 60.

The emitter terminal 72 of the second transistor 68
When the output voltage VIN2 appears at the both ends, a potential difference of VIN2 is generated between both ends of the resistor 78. In this case, the resistor 7
8, the current I6 flowing through the second transistor 68 is controlled to a value represented by the following equation. I6 = VIN2 / R6 (8) The input impedance of the operational amplifier 36 can be regarded as substantially infinite. Therefore, the following relationship is established between the current I3 flowing through the resistor 30, the current I1 flowing through the first current source 34, and the current IS flowing through the sensor 10.

IS = I1−I3 (9) When the output voltage VIN1 appears at the terminal 18 of the sensor 10, a potential difference represented by 2Vref−VIN1 occurs at both ends of the resistor 30. In this case, the current I3 flowing through the resistor 30 can be expressed by the following equation. I3 = (2Vref−VIN1) / R3 (10) As described above, the current I1 flowing through the first current source 34
Is controlled to a value equal to the current I6. Further, in the differential input circuit of the present embodiment, the resistance value R6 of the resistor 78 and the resistance value R3 of the resistor 30 are both R as described above.
Therefore, the relation of the above equation (9) can be rewritten as the following equation using the relation of the above equations (8) and (10).

IS = VIN2 / R− (2Vref−VIN1) / R (11) Similarly, the input impedance of the operational amplifier 60 can be regarded as substantially infinite. Therefore, the resistor 54
Current flowing through the second current source 58 and a current I2 flowing through the second current source 58.
And the current IS flowing into the sensor 10 satisfies the following relationship.

IS = I2-I4 (12) When the output voltage VIN2 appears at the terminal 20 of the sensor 10, a potential difference of VIN2 is generated between both ends of the resistor 56. In this case, the current I4 flowing through the resistor 56 can be expressed by the following equation. I4 = VIN2 / R4 (13) As described above, the current I2 flowing through the second current source 58
Is controlled to a value equal to the current I5. Further, in the differential input circuit of this embodiment, the resistance value R5 of the resistor 54 and the resistance value R4 of the resistor 56 are both R as described above. Therefore, the relation of the above equation (12) can be rewritten as the following equation using the relation of the above equations (7) and (13).

IS = (2Vref−VIN1) / R−VIN2 / R (14) The relation of the above equation (11) and the relation of the above equation (14) are limited only when IS = 0. compatible. Therefore,
According to the operation input device of the present embodiment, the current IS flowing through the sensor 1010 can always be “0”. Current I
If S is "0", the internal resistances R1, R2 of the sensor 10
Does not cause a voltage drop. For this reason, in the operation input device of the present embodiment, the potential difference Vi generated between both ends of the output generation unit 12 and the output voltages VIN1 and VI of the sensor 10 are determined.
The following equations (15) and (16) hold with N2.

Vi = VIN1−VIN2 (15) VIN1 = 2Vref−I3 · R3 = 2Vref−I1 · R3 (16) As described above, in the differential input circuit, R3 = R, I1
= I6 holds. Therefore, the relation of the above equation (16) can be rewritten as the following equation using the relation of the above equation (8) (I6 = VIN2 / R).

VIN1 = 2Vref−VIN2 (17) From the relations of the above equations (15) and (17), the output voltages VIN1 and VIN2 can be expressed as follows. VIN1 = Vref + Vi / 2 (18) VIN2 = Vref-Vi / 2 (19) As shown in the above equations (18) and (19), the output voltages VIN1 and VIN2 of the sensor 10 are based on the reference voltages. Voltage V
With an amplitude of half of the potential difference Vi generated at both ends of the output generation section 12 around the ref, the phase changes with phases opposite to each other. As described above, according to the differential input circuit of the present embodiment, the potential difference Vi generated at both ends of the output generation unit 12 is determined by using the reference voltage Vref as the bias voltage and the terminal 1 of the sensor 10.
It can be generated between 8, 20 as it is.

The above-described function of the operation input device is realized by the first current source 34 connected to one terminal 18 of the sensor 10.
Flows the same amount of current I1 (= I6) as the current I4 (= I6) flowing through the resistor 56, and the second current source 58 connected to the other terminal 20 of the sensor 10 Current I2 of the same amount as flowing current I3 (= I5)
(= I5).

That is, in the circuit shown in FIG. 1, for example, when the output voltage VIN1 of the sensor 10 increases by ΔV, the current I3 flowing through the resistor 30 decreases by ΔV / R. In this case, as the current I3 (= I5) decreases, the current I2 flowing through the second current source 58 also decreases by ΔV / R. If the current I1 flowing through the first current source 34 does not change when the current I3 decreases by ΔV / R as described above, the first current from the terminal 18 of the sensor 10 is supplied to compensate for the decrease in the current I3. In the direction flowing into the source 34, ΔV / R
Current (hereinafter, referred to as IS ₍₊₎₎ having a magnitude of?

On the other hand, the current I1 flowing through the first current source 34
Assuming that no change has occurred in (= I6), no change should have occurred in the current I4 (= I6) equal to the current I1. If the current I4 flowing through the resistor 56 does not change when the current I2 flowing through the second current source 58 decreases by ΔV / R as described above, the terminal 20 of the sensor 10 is used to compensate for the decrease in the current I2. Flows into the resistor 56 from the current IS having a magnitude of ΔV / R (hereinafter referred to as IS
₍ Referred to as _(-)) should flow.

As described above, if output current VIN1 increases by ΔV, and if currents I3 and I2 decrease by ΔV / R, then currents I1 and I4 do not change. Reverse current IS
_{(-) And} IS ₍₊₎ are distributed at the same time. To avoid such inconsistency, the differential input circuit operates such that if the currents I3 and I2 decrease by ΔV / R, the currents I1 and I4 also decrease by ΔV / R. In this case, the current I flowing through the sensor 10
S becomes "0", and the above contradiction is resolved. When the current I4 decreases by ΔV / R, the output voltage VIN2 of the sensor 10 changes in the opposite phase to the output voltage VIN1, and decreases by ΔV.

As described above, if the current I1 flowing through the first current source 34 is controlled to the same value as the current I4 and the current I2 flowing through the second current source 58 is controlled to the same value as the current I3, the current flowing through the sensor 10 is controlled. Assuming that the current IS is "0", that is, the input impedance of the differential input circuit is apparently infinite, the potential difference Vi generated in the output generator 12 can be taken out as it is as the output voltages VIN1 and VIN2, and the output voltages VIN1 and VIN1 VIN2 with equal amplitude,
And in a phase opposite to each other, that is, a predetermined reference voltage V
It can be changed symmetrically around ref.

Next, a method for improving the noise resistance of the differential input circuit of this embodiment will be described with reference to FIG. As shown in FIG. 1, the output voltages VIN1, V
According to the configuration in which IN2 is received by the differential input circuit, a signal line connecting one terminal 18 of the sensor 10 and the differential input circuit and the other terminal 20 of the sensor 10 It is possible to cancel noise that is superimposed equally on both signal lines connecting to the differential input circuit. In this regard,
The differential input circuit has high noise resistance.

However, if the circuit connected to the terminal 18 and the circuit connected to the terminal 20 are unequal due to variations in the elements constituting the differential input circuit, etc.
In some cases, a difference occurs in a voltage induced by noise superimposed on a signal line, and a noise component cannot be removed. In order to suppress such noise components, it is desirable that the voltage induced by noise superimposed on the signal line be low. Further, in order to reduce the voltage induced by noise to a low voltage, it is desirable that the differential input circuit has a small input impedance with respect to signals input in the same phase to the two signal lines.

FIG. 4 is a circuit diagram in which a noise power supply 96 is connected to the internal resistance generators 14 and 16 in place of the output generator 12 in the circuit shown in FIG. According to the circuit configuration shown in FIG. 4, in-phase signals can be supplied to the differential input circuit of this embodiment. Hereinafter, a voltage generated by the noise power supply 96 is a generated voltage V _N , a current flowing out of the terminal 18 is a current IS1, and a current flowing out of the terminal 20 is a current IS
Called 2. The voltages generated at the terminals 18 and 20 are referred to as output voltages VIN1 and VIN2 as in the case of FIG.

As described above, the operational amplifiers 36 and 60 have a large input impedance. Therefore, the current I
Between S1, current I1, and current I3, and current IS2
And the current I2 and the current I4 are expressed by the following equations (2
0) and (21) are established. IS1 = I1-I3 (20) IS2 = I4-I2 (21) The current I1 can be represented by I1 = I6 = VIN2 / R (see the above equation (8)). The current I3 is I3 = (2V
ref−VIN1) / R ((1)
0) expression). Therefore, the above equation (20) can be expressed as the following equation.

IS1 = (VIN2 / R) − (2Vref−VIN1) / R (22) The current I4 can be expressed by I4 = VIN2 / R (see the above equation (13)). The current I2 is I2 = I5 =
It can be expressed by (2Vref−VIN1) / R (see the above equation (7)). Therefore, the above equation (21) can be expressed as the following equation.

IS2 = (VIN2 / R) − (2Vref−VIN1) / R (23) As shown in the above equations (22) and (23), in the circuit shown in FIG. 4, IS1 = IS2 Is established. The resistance values R1, R2 of the internal resistance generating units 14, 16 are
Both are RS / 2. Therefore, the output voltages VIN1, VI
The relationship of VIN1 = VIN2 is established between N2.

The output voltage VIN2 = I4.R is calculated according to (2) above.
Using the relations of the expressions 1) and (7), it can be expressed as the following expression. VIN2 = (I2 + IS2) .R = 2Vref-VIN1 + IS2.R (24) Accordingly, VIN1 and VIN2 can be represented by the following equations.

VIN1 = VIN2 = Vref + IS2 · (R / 2) (25) As described above, the differential input circuit has a
Both the side connected to the terminal 18 and the side connected to the terminal 20 show an input impedance of R / 2 equally. In the present embodiment, the resistance values R of the resistors 30, 56, 54, 78 included in the differential input circuit are set to sufficiently small values. For this reason, the differential input circuit according to the present embodiment exhibits an apparently infinite input impedance with respect to a signal having an opposite phase, but has a sufficiently small input impedance with respect to a signal having the same phase. For this reason, according to the differential input circuit of the present embodiment, the generated voltages VS1 and VS2 generated in the output generator 12 of the sensor 10 are
Can be taken out as the output voltages VIN1 and VIN2, and high noise resistance against superimposed noise can be ensured.

Next, using the differential input circuit of this embodiment,
A method for detecting an output signal of a resistance change type sensor that changes a resistance value according to the state of an object to be detected, such as a magnetoresistive element, will be described. FIG. 5 shows a circuit diagram in which a magnetoresistive element 98 is connected to a conventional differential input circuit. As a method of detecting the resistance value RM of the magnetoresistive element 98, conventionally,
As shown in FIG. 5, a pull-up resistor 1
00, the pull-down resistor 102 is connected, the bias point is determined by the resistors 22 and 24 and the reference power supply 26, and the output voltages VIN1 and VIN2 corresponding to the resistance RM are generated at both ends of the magnetoresistive element 98. It has been known.

However, according to the circuit configuration shown in FIG. 5, since the resistors 22 and 24 are connected in parallel with the magnetoresistive element 98, the characteristics of the output voltages VIN1 and VIN2 are not proportional to the resistance value RM. Therefore, depending on the circuit configuration shown in FIG. 5, it is difficult to accurately detect the state of the resistance change type sensor such as the magnetoresistive element 98. FIG.
Is a magnetic resistance element 98 using the differential input circuit of this embodiment.
FIG. 2 is a circuit diagram of a circuit configured to detect a resistance value RM of FIG. In the circuit shown in FIG. 6, both ends of the magnetoresistive element 98 are connected to signal lines 28 and 55 leading to a differential input circuit. The constant current source 104 is connected to the signal line 28. The constant current source 104 is connected to the reference voltage line 32. The constant current source 104 operates so that a predetermined current I flows therein. Similarly, a constant current source 106 is connected to the signal line 55. The constant current source 106 is grounded to a ground line. The constant current source 106 operates so that the current I flows therein.

As described above, the differential input circuit of this embodiment is
The input signal has an apparently infinite input impedance with respect to the signal having the opposite phase. Therefore, in the circuit shown in FIG. 6, the current I flowing through the constant current sources 104 and 106 flows through the magnetoresistive element 98 as it is. In this case, output voltages VIN1 and VIN2 which change in opposite phases with respect to the reference voltage Vref and have a potential difference represented by I · RM are generated at both ends of the magnetoresistive element 98. Therefore, according to the differential input circuit of the present embodiment, it is possible to easily and accurately detect a change in the resistance value of the resistance change sensor.

In the above embodiment, the signal line 28
The signal line 55 is connected to the “first input terminal” according to claim 1.
2. The "second input terminal" of claim 2, the reference voltage line 32 is "first reference voltage generating means" of claim 1, and the ground line is "second reference voltage" of claim 1. In the "generating means", the resistor 30 corresponds to the "first resistor" according to claim 1, and the resistor 56 corresponds to the "second resistor" according to claim 1, the operational amplifier 36, the first transistor 44, and the resistor. The operational amplifier 60, the second transistor 68, the resistor 78, and the second current source 58 are the same as the “first current source” according to claim 1.
Correspond to the “second current source” of the first aspect, respectively.

Incidentally, in the above embodiment, the first
The current source 34 and the constant current source 106 are grounded, and the second current source 58 and the constant current source 104 are connected to the reference voltage line 32. These current sources are connected to another voltage source and driven. May be. Further, in the above embodiment, the resistor 56 and the resistor 78 are grounded to the ground line. However, the present invention is not limited to this. May be connected.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a circuit diagram of the differential input circuit according to the present embodiment. In FIG. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The differential input circuit of this embodiment is different from the differential input circuit shown in FIG.
Instead of using the first transistor 108,
This is realized by using the second transistor 110 instead of the transistor 68. First transistor 108
Is a P-channel MOS transistor. The second transistor 110 is an N-channel MOS transistor.

In the differential input circuit shown in FIG. 1, the current flowing through resistor 54 is the current I3 flowing through resistor 30.
(2Vref-VIN1) / R.
However, some of the current flowing through resistor 54
It is consumed as the base current of the transistor 44. Therefore, the current I5 flowing out of the collector terminal 50 of the first transistor 44 is strictly smaller than the current I3.

Similarly, in the differential input circuit shown in FIG. 1, the current flowing through the resistor 78 is controlled to VIN2 / R, which is equal to the current I4 flowing through the resistor 56. However, the current flowing through the resistor 78 is the second transistor 6
8 is the sum of the base current and the collector current. Therefore, the current I6 flowing into the collector terminal 74 of the second transistor 68 is strictly smaller than the current I4.

As described above, the first current source 34 attempts to flow the current I1 equal to the current I6. Further, the second current source 58 tries to flow a current I2 equal to the current I5. Therefore, if a bipolar transistor is used in the current conversion circuit of the differential input circuit, the current I1 and the current I2, and the current I3 and the current I2
4, a slight error occurs.

On the other hand, the first transistor 108 and the second transistor 110 used in the circuit of this embodiment operate without flowing the gate current.
Therefore, according to the differential input circuit of the present embodiment, the current I1 flowing through the first current source 34 and the current I4 flowing through the resistor 56, and the current I2 flowing through the second current source 58 The current I3 flowing through the resistor 30 can be accurately matched. Therefore, according to the differential input circuit of the present embodiment, a more accurate operation can be realized as compared with the above-described differential input circuit of the first embodiment.

In the above embodiment, the operational amplifier 36, the first transistor 108, the resistor 54,
The “first current source” according to claim 1, wherein the first current source 34 is.
In addition, the operational amplifier 60, the second transistor 110, the resistor 78, and the second current source 58 correspond to the “second current source” of the first aspect.

[0072]

As described above, according to the present invention, the voltages VIN1 and VIN2 having an apparently infinite input impedance and appearing at the first input terminal and the second input terminal.
Can be realized in a differential input circuit that can be changed in opposite phases with respect to an appropriate reference voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a differential input circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a first current source included in the differential input circuit shown in FIG.

FIG. 3 is a circuit diagram of a second current source included in the differential input circuit shown in FIG.

FIG. 4 is a circuit diagram in which a noise power supply that supplies an in-phase signal is connected to the differential input circuit of the present embodiment.

FIG. 5 is a circuit diagram illustrating a main part of a conventional differential input circuit for detecting a resistance value RM of a magnetoresistive element.

FIG. 6 is a circuit diagram of a circuit configured to detect a resistance value RM of a magnetoresistive element using the differential input circuit of the present embodiment.

FIG. 7 is a circuit diagram of a differential input circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a main part of a conventional differential input circuit.

FIG. 9 shows a generated voltage VS1, which is generated in an output generating unit of the sensor.
VS2 and the output voltage VI input to the conventional differential input circuit
It is a waveform of N1 and VIN2.

[Explanation of symbols]

 Reference Signs List 10 sensor 12 output generator 14, 16 internal resistance generator 28, 55 signal line 30, 54, 56, 78 resistor 34 first current source 36, 60 operational amplifier 44; 108 first transistor 58 second current source 68; 110 Second transistor 98 Magnetoresistive element VS1, VS2 Generated voltage VIN1, VIN2 Output voltage

Claims (1)

[Claims] 1. A differential input circuit for receiving a signal at a first input terminal and a second input terminal, wherein: a first reference voltage generating means for generating a first reference voltage; Reference voltage generating means for generating a low-voltage second reference voltage, a first resistor having a predetermined resistance value and interposed between the first input terminal and the first reference voltage generating means A second resistor having a predetermined resistance value and interposed between the second input terminal and the second reference voltage generating means; and a second resistor connected to the first input terminal, A first current source that causes a current equal to the flowing current to flow out from the first input terminal side, and a current equal to the current flowing through the first resistor that is connected to the second input terminal and flows into the second input terminal side And a second current source.