JPH10256376A - IC placement and routing system and semiconductor device manufactured using the same - Google Patents

Abstract

(57) [Summary] When a semiconductor circuit is generated by an IC layout and wiring system, the space between wirings is reduced according to a design rule, so that the capacitance between wirings is increased and wiring delay is increased. After performing initial wiring (42), a distance between wirings and a parallel distance of each wiring are calculated (43). The non-wiring area of each wiring is set in consideration of the wiring capacity condition description (34) (44). By setting the unacceptable area and rewiring the wiring that violates the design rule (4
5) Calculate the wiring delay (46). If the constraint conditions described in the interconnect delay constraint description (35) are satisfied, the interconnect processing ends. If not, the non-wiring area is expanded and set, and the calculation of wiring and wiring delay is repeated. If the constraint condition cannot be satisfied with a certain number of repetitions, a placement and wiring description of a circuit with the smallest wiring delay among the repetitions is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC layout and wiring system for designing a semiconductor circuit, and a semiconductor device manufactured using the same.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor manufacturing technology, factors affecting the operation speed of a circuit have been caused by the delay of wiring connecting between cells rather than the delay of cells in the circuit itself. The main factor that determines the wiring delay is the wiring capacitance C, which depends on the operating voltage, temperature, and manufacturing variations of the circuit. In the manufacturing process of 0.5μ or less,
In addition to the wiring capacitance of each wiring, the influence of the capacitance between wirings parasitic between the wirings is increasing.

FIG. 5 shows an increase graph of the capacitance between wirings.
The interwiring capacitance increases in proportion to the parallel distance L between adjacent wirings, and increases in inverse proportion to the interwiring distance D. That is, it is necessary to increase the distance between the wirings to some extent in order to suppress the wiring delay in addition to reducing the distance in accordance with the design rule.

Here, an example of circuit wiring of an IC placement and wiring system according to the prior art will be described.

FIG. 6 shows an example of wiring in a circuit arranged and wired in the prior art. Wiring A (1) and Wiring B (2)
Are wired in parallel at a distance L. In the prior art, the distance D between the wiring A (1) and the wiring B (2) is
In accordance with design rules in the manufacturing process, they are packed as much as possible so as to fit within a predetermined wiring arrangement area.

FIG. 8 shows an input / output flow diagram of a conventional IC placement and routing system. The IC arrangement and wiring system (37) receives the logic circuit description (36), arranges the cell information shown in the cell library description (39), and performs wiring. In the placement and routing, the wiring position is determined in consideration of the design rule constraint description (40) according to the manufacturing process and the wiring delay constraint description (41) for realizing the operating frequency of the circuit. The inter-capacity was not considered as a constraint.

[0007]

However, in the above-mentioned prior art, there is a problem that the capacitance between wirings increases in a manufacturing process of 0.5 μm or less, which greatly affects wiring delay.

FIG. 7 shows a cross-sectional view of the prior art wiring example of FIG. The wiring A (3) has a wiring capacitance CA (5), and the wiring B (4) has a wiring capacitance CB (7). Wiring A (3)
The inter-wiring capacitance CD (6) becomes parasitic in inverse proportion to the inter-wiring distance D between the wiring A and the wiring B (4), and the wiring delay of the wiring A (3) and the wiring B (4) increases greatly.

In another conventional technique, as shown in FIG. 9, for the purpose of preventing malfunction due to crosstalk between wirings,
There is an attempt to provide a shield made of metal or the like between wirings.
Assuming a position where the shield S (9) is to be arranged in advance between the wiring A (8) and the wiring B (10), the wiring is set to be at least twice the minimum distance D between wirings + the width of the shield S according to the design rule. You need to keep a break. In this attempt, as shown in the cross-sectional view of FIG. 9 and FIG. 10, by connecting the shield S (13) to the power supply or the ground (16), it is possible to suppress the capacitance between wirings. Since the wiring area (11) shown becomes considerably large, there arise problems such as the inability to complete the wiring of the entire circuit, an increase in the circuit size and an increase in manufacturing cost.

An object of the present invention is to set a non-wiring area around adjacent parallel wirings in a circuit in accordance with a parallel distance between wirings and determine a wiring position, thereby suppressing inter-wiring capacitance. And a semiconductor circuit using the same.

[0011]

SUMMARY OF THE INVENTION In designing a semiconductor circuit, a method for designing a semiconductor circuit is described.
In the C placement and routing system, there are a plurality of wirings connecting the respective cells constituting the semiconductor circuit, and a means for calculating a parallel distance in which the plurality of wirings are wired is provided. Has means for setting
An IC arrangement and wiring system, comprising: means for determining wiring positions of the plurality of wirings.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an IC arrangement and wiring system according to the present invention.

FIG. 1 shows an embodiment of a circuit arranged by the IC arrangement and wiring system of the present invention. Wiring A (17),
According to the parallel distance L of the wiring B (18), the wiring A (17)
A non-wiring area (20) is set around the area. The length of the non-wiring area is the length of the wiring A (17) or the length of the wiring B
(18) The length can be freely determined between the lengths, and the width can be determined in consideration of the degree of wiring congestion in the circuit, the required delay margin of the wiring, and the like. In the IC arrangement / wiring system for realizing the embodiment, the minimum distance D between the wirings is calculated from the end of the non-wiring area (20) on the wiring B (18) side, and the wiring B
The arrangement position of (18) is determined. Thus, assuming that the width of the non-wiring area (20) is W, the distance between the wiring A (17) and the wiring B (18) is D + W.

FIG. 2 is a cross-sectional view of a circuit embodiment arranged by the IC arrangement and wiring system of the present invention shown in FIG. Compared to the wiring example in the prior art shown in FIG.
Since the inter-wiring distance is increased by the width of the non-wiring area, the inter-wiring capacitance C (D + W) (26) is
D (6) can be reduced.

FIG. 3 shows an embodiment of an input / output flow of the IC arrangement / wiring system of the present invention.

In FIG. 3, an IC placement / wiring system (30) of the present invention receives a logic circuit description (29) as input and arranges cell information shown in a cell library description (32) to perform wiring. At the time of placement and routing, description of the design rule constraint conditions (40) according to the manufacturing process, description of the wiring delay constraint conditions (41) for realizing the operating frequency of the circuit, and initialization of the size of the non-wiring area. The wiring position is determined in consideration of the wiring capacitance condition description (34). The wiring capacity condition description (34) describes the increase / decrease relationship of the wiring capacity according to the wiring distance and the wiring parallel distance with respect to the manufacturing process.

FIG. 4 is a functional flowchart of the wiring processing section of the IC placement and wiring system according to the present invention.

After performing the initial wiring (42), the distance between wirings and the parallel distance of each wiring are calculated (43). The non-wiring area of each wiring is set in consideration of the wiring capacity condition description (34) (44). By setting the unacceptable area and rewiring the wiring that violates the design rule (4
5) Calculate the wiring delay (46). If the constraint conditions described in the interconnect delay constraint description (35) in FIG. 3 are satisfied, the interconnect processing ends. If not, the non-wiring area is expanded and set, and the calculation of wiring and wiring delay is repeated. If the constraint condition cannot be satisfied with a certain number of repetitions, a placement and wiring description of a circuit with the smallest wiring delay among the repetitions is generated.

By setting the width of the non-wiring area large, the wiring area may be squeezed and the wiring of the entire circuit may not be completed. This phenomenon can be avoided by reducing the width of the non-routable area from the value set at 44 in FIG. 4 and calculating the wiring and the wiring delay again.

As described above, in the above-described embodiment, the means for setting the non-wiring area by the parallel distance value in consideration of the parallel distance in which a plurality of wirings connecting the cells are wired in the IC placement and wiring system is taken into consideration. By introducing and determining the wiring position, the space between the wirings can be expanded without causing a significant increase in the circuit scale, and the capacitance between the wirings can be suppressed.

[0021]

As described above, according to the present invention,
For a semiconductor circuit to be wired in an IC arrangement / wiring system, an IC that can increase the space between wirings without causing a significant increase in circuit scale, suppress the capacitance between wirings, and reduce wiring delay of the semiconductor circuit. An arrangement and wiring system can be provided.

[Brief description of the drawings]

FIG. 1 is a wiring diagram wired by an embodiment of an IC arrangement / wiring system of the present invention.

FIG. 2 is a cross-sectional view of a wiring routed by an embodiment of the IC placement and routing system of the present invention.

FIG. 3 is an input / output flowchart of an IC arrangement / wiring system of the present invention.

FIG. 4 is a functional flowchart in an IC placement and routing system wiring processing unit of the present invention.

FIG. 5 is a graph showing an increase in inter-wire capacitance.

FIG. 6 is a wiring diagram (1) wired by a conventional IC placement and routing system.

FIG. 7 is a cross-sectional view of a wiring diagram (1) wired by a conventional IC arrangement / wiring system.

FIG. 8 is an input / output flow diagram of a conventional IC placement and wiring system.

FIG. 9 is a wiring diagram (2) wired by a conventional IC arrangement / wiring system.

FIG. 10 is a cross-sectional view of a wiring diagram (2) wired by a conventional IC placement and routing system.

[Explanation of symbols]

1, 2, 3, 4, 8, 9, 10, 12, 13, 14, 1
7, 18, 22, 23 are wirings between cells, 19, 20, 2
7 and 28 are non-wiring areas, 11 and 21 are wiring areas, 5,
7, 15, 17, 24, 25 are wiring capacitances, 6, 16, 2,
6 is an inter-wire capacitance, 29 and 36 are logic circuit descriptions, 30, 3
7 is an IC layout and wiring system, 31 and 38 are circuit layout and wiring descriptions, 32 and 39 are cell library descriptions, 33 and 40 are design rule constraint description, 35 and 41 are wiring delay constraint description, and 34 is wiring capacity condition description. , 42-46 are I
This is a functional block unit constituting the C placement and routing system.

Claims (2)

[Claims] In an IC placement and routing system for designing a semiconductor circuit, there are a plurality of wirings connecting between cells constituting the semiconductor circuit, and there is means for calculating a parallel distance in which the plurality of wirings are wired. An IC having means for setting a non-wiring area based on the parallel distance value and means for determining wiring positions of the plurality of wirings.
An arrangement / wiring system and a semiconductor device manufactured using the same. 2. The method according to claim 1, wherein the I is used for designing a semiconductor circuit.
An IC placement and routing system, comprising: a means for adjusting a distance between the plurality of wirings according to a wiring delay constraint condition of the plurality of wirings.
And a semiconductor device manufactured using the same.