JPH10256552A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a method of manufacturing a thin film transistor in which a mask process step is reduced to reduce a process cost. In a method of manufacturing a semiconductor device having two conductive thin film transistors on an insulating substrate, a semiconductor thin film is formed on an insulating substrate, a gate insulating film is formed thereon, and a gate electrode is formed thereon. A step of injecting a first conductivity type impurity into the semiconductor thin film 2 at a first concentration using the gate electrode 4 as a mask, a step of forming a gate electrode of the first conductivity type thin film transistor and both sides thereof, Forming a first mask film M1 that covers the semiconductor thin film of the thin film transistor of the first conductivity type, and using the first mask film M1 as a mask, a second concentration of a first conductivity type impurity higher than the first concentration in the semiconductor thin film. And forming a second mask film M2 covering the semiconductor thin film of the first conductivity type thin film transistor, and using the mask as a mask to form a second mask film M2 in the semiconductor thin film of the second conductivity type thin film transistor. Further comprising the step of the second than the first concentration of impurities of the conductivity type by implanting a third concentration of the high concentration of the second conductivity type semiconductor, characterized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a CMOS semiconductor device formed on an insulating substrate used for a liquid crystal display device or the like.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display panel comprises a TFT substrate on which a thin film transistor is formed, a counter substrate thereof, and a liquid crystal layer sandwiched between them. Among them, the TFT substrate is provided with a plurality of scan buses and a data bus intersecting the scan buses on a glass substrate, and a thin film transistor (TFT) for pixel selection and a pixel electrode at the intersection. This liquid crystal display panel further requires a scan driver circuit for driving the scan bus and a data driver circuit for applying a signal according to display data to the data bus.

[0003] In view of the demand for cost reduction, it is desired to form the above-described driver circuit on a glass substrate in the same manner as the display section. In order to save power consumption, these driver circuits are constituted by CMOS circuits. In addition, in order to form on a glass substrate, a polycrystalline silicon layer is formed on the surface of the glass substrate, and an N-type MOS transistor and a P-type MOS transistor are formed thereon. That is,
An I-type semiconductor layer is formed of a polycrystalline silicon layer, an N-type impurity is introduced therein to form a drain / source region to form an N-type MOS transistor, and a P-type impurity is introduced. To form a drain / source region to form a P-type MOS transistor. As described above, the transistor of the driver circuit has a thin film transistor (TFT) structure like the selection transistor in the display region.

[0004]

As described above, the polycrystalline silicon layer formed on the glass substrate is grown at a lower temperature than the single crystal silicon substrate, and the film quality is not so good. Therefore, an LDD (Light Doped Drain) structure is adopted for the N-type transistor in order to suppress the leakage current when the transistor is off and to improve the reliability. In addition, the LDD portion has a length several times (for example, 0.3 μm to several μm) longer than that used in a semiconductor device using single crystal silicon due to the above requirement. Therefore, like a semiconductor device using a single crystal silicon substrate,
The manufacturing process of the LDD structure using the insulating film formed on the side wall of the gate electrode cannot be used.

Therefore, to form a drive circuit on a liquid crystal display substrate, it is necessary to form an LDD structure using a resist mask.

However, it is not preferable to add a new mask process to form an LDD structure in the portion of the N-type MOS transistor because it causes an increase in cost. In order to form a CMOS structure, a mask process for forming source / drain regions of a P-type transistor and a mask process for forming source / drain regions of an N-type transistor are required. It is not preferable to add a mask process for forming a structure.

A process using a gate oxide film has been proposed to form an LDD structure. However, in the method of doping impurities from above the gate oxide film, the impurities are trapped in the gate oxide film. This is not preferable because TFT characteristics are poor.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a method of manufacturing a CMOS semiconductor device having a TFT structure with a small number of mask processes.

Another object of the present invention is to provide a method of manufacturing a CMOS semiconductor device in which impurities are not trapped in a gate oxide film.

[0010]

According to the present invention, there is provided a method of manufacturing a semiconductor device having two conductive thin film transistors on an insulating substrate. A step of forming a thin film, a gate insulating film thereon, and a gate electrode thereon, and using the gate electrode as a mask, implanting a first conductivity type impurity into the semiconductor thin film at a first concentration. Forming a first mask film covering the gate electrode of the first conductivity type thin film transistor and both sides thereof, and the semiconductor thin film of the second conductivity type thin film transistor, and masking the first mask film; Implanting the impurity of the first conductivity type at a second concentration higher than the first concentration into the semiconductor thin film of the thin film transistor of the first conductivity type; and Thin Forming a second mask film covering the semiconductor thin film of the transistor, using the second mask film as a mask, the second conductive type impurity is contained in the semiconductor thin film of the second conductive type thin film transistor. Implanting at a third concentration higher than one concentration to form the second conductivity type semiconductor.

According to the above process, the LDD region and the source / drain region of the N-type transistor are formed by two mask steps.
A drain region and a source / drain region of a P-type transistor can be formed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. However, the technical scope of the present invention is not limited to the embodiment.

FIG. 1 is a diagram showing a configuration of a TFT substrate of a general liquid crystal display device. On a transparent substrate 50 such as glass, scan bus lines SB1 to SBm are provided in the horizontal direction, and data bus lines DB1 to DBn are provided in the vertical direction.
The pixel selection transistor 52 and the pixel electrode 54 are provided at the intersection. The pixel selection transistor 52 is composed of, for example, an N-type TFT MOS transistor. Scan canvas line is scan driver 5
6 driven. The data bus line is driven by the data driver 58. Each of the drivers 56 and 58 is constituted by a CMOS circuit using a TFT.

FIG. 2 is a diagram showing a manufacturing process according to an embodiment of the present invention. In the figure, an N-type MOS transistor is shown on the left and a P-type MOS transistor is shown on the right. First, as shown in FIG. 2A, an I-type semiconductor layer 2 made of, for example, a polysilicon layer having a thickness of about 60 nm is formed on a transparent insulating substrate 1 made of glass or the like. To In addition, for example, 1
Gate insulating film 3 made of a silicon oxide film of about 50 nm
Is formed thereon, an aluminum layer of, for example, about 250 nm is formed thereon, and the gate electrode 4 is formed by etching.

As shown in FIG. 2B, the gate electrode 4
Is used as a mask to introduce phosphorus ions (P) at high acceleration and low concentration over the entire surface of the substrate by ion doping,
Low concentration regions 7 and 8 are formed respectively. The high acceleration is, for example, about 100 kV, and the low concentration is 2 × 10
It is about ¹⁴ cm ^-2 , the acceleration is such that the phosphorus ions pass through the gate oxide film 3, and the concentration is low enough for the LDD structure.

As shown in FIG. 2C, a resist layer is formed on the surface of the substrate, and the resist layer is formed by a usual lithography process.
On the P-type transistor side, a mask film M1 is formed on the N-type transistor side to cover the gate electrode 4 and the LDD regions on both sides thereof. Then, for example, the gate insulating film 3 other than the LDD portion of the N-type TFT is removed by etching with plasma using a mixed gas of trifluoromethane gas (CHF ₃ ) and carbon tetrafluoride gas (CF ₄ ). Then, phosphorus ions are introduced at a high concentration by an ion doping method using the mask M1. For example, 20k
At a speed of V, it is about 2 × 10 ¹⁵ cm ⁻² . Therefore, N
The source / drain region 6 of the TFT of the type becomes a region having a high impurity concentration, and an LDD structure having a relatively low concentration is formed on the channel region side of the region 6.

As shown in FIG. 2D, after the mask M1 is removed, a new N-type TFT is coated,
A second mask M2 exposing the TFT of the mold is formed. Then, using the P-type gate electrode 4 as a mask, the gate insulating film 3 is removed by the same plasma etching method as described above. Then, for example, boron ions (B) are introduced into the exposed region 8 at a high concentration by an ion doping method.
The acceleration is, for example, about 10 kV, and the concentration is a high concentration, for example, about 4 × 10 ¹⁵ cm ⁻² .

Thereafter, through a general annealing step, the source / drain regions 6, 8 of the N-type and P-type TFTs and the LDD region of the N-type TFT are activated.
By introducing and activating boron ions, which are P-type impurities, at a high concentration, the region 8 which is lightly doped with N-type in FIG. 2B is inverted to P-type. In general, boron ions are more easily diffused than phosphorus ions.
Facilitates mold reversal.

Then, as shown in FIG. 2E, an interlayer insulating film 9 made of, for example, silicon nitride is formed, a contact hole 10 is formed, and finally a wiring 11 is formed. As described above, the N-type TFT and the P-type TFT are provided.
A semiconductor device having a D structure is completed.

In the above embodiment, first, a low-concentration impurity is introduced into the entire surface, and then two masks are used to form the source / drain regions of the N-type transistor and the P-type transistor. Introduce a high concentration of impurities. Therefore, only two mask processes are required to form the LDD region and the P-type and N-type source / drain impurity regions. Further, when introducing high-concentration impurities into the source / drain regions of the N-type TFT, the high-concentration impurities are not introduced into the gate oxide film above the LDD region, so that impurities are trapped in the gate oxide film. There is no.

FIG. 3 is a process chart of the second embodiment. In the second embodiment, FIG.
After the process shown in FIG. 3B, the processes shown in FIGS. 3A to 3E are performed. 2A and 2B, as described above, a polysilicon layer 2 is formed on a transparent insulating substrate 1 such as glass.
Is formed and patterned into an island shape, a silicon oxide layer 3 is formed thereon as a gate insulating film, and a gate electrode 4 made of aluminum or the like is formed thereon. Then, using the gate electrode 4 as a mask, the entire surface is doped with P ions at a low concentration. The process so far is equivalent to the above-described process.

Next, as shown in FIG. 3A, a first mask layer M1 which covers the gate electrodes 4 of the P-type TFT region and the N-type TFT region and the LDD regions on both sides thereof is formed. . The mask layer is formed, for example, by coating a resist layer on the surface and performing a normal lithography process using a mask.

Then, without removing the gate oxide film, high-concentration phosphorus ions are implanted at a relatively high acceleration with a high concentration by ion doping, thereby introducing a high-concentration impurity into the source / drain region 6 of the N-type TFT. This ion doping step is performed, for example, at an acceleration of 100 kV and 2 × 1
It is performed at a high concentration of about 0 ¹⁵ cm ^-2 .

Next, as shown in FIG. 3B, the first mask layer M1 is removed, and a second mask layer M2 covering the N-type TFT region is formed. Then, for example, boron ions (B) are implanted through the gate oxide film by an ion doping method to form source / drain regions of the P-type TFT. The condition at this time is, for example, an acceleration of 75 kV and a high concentration of about 4 × 10 ¹⁵ cm ⁻² . Therefore, the source / drain regions 8 which were initially made low-concentration n-type by annealing thereafter are inverted to p-type.

Then, as shown in FIG. 3C, after the impurity region is activated by an ultraviolet laser or the like, an interlayer insulating film 9 made of silicon nitride is formed, for example, to a thickness of about 300 nm. A resist mask 10 is formed thereon to form a contact hole.

As shown in FIG. 3D, the above-described plasma etching using the resist mask 10
The gate oxide film 3 is removed together with the interlayer insulating film 9. Then, as shown in FIG. 3E, the wiring 11 made of aluminum is formed.
Is formed and patterned into a predetermined shape.

In the second embodiment, the gate electrode 4 is formed in order to form the LDD region of the N-type TFT.
Perform low-concentration overall ion doping using as a mask,
The respective high concentration source / drain regions are formed using the resist masks M1 and M2, respectively. Therefore, only two masks are required to form those regions. In the second embodiment, the gate oxide film 3 is not etched before the source / drain regions of the N-type and P-type TFTs are formed. Also, the number of steps can be reduced. However, for this purpose, high-concentration impurity doping is performed through the gate insulating film. However, the region of the gate insulating film is not located above the LDD region, and thus does not adversely affect the operation characteristics of the TFT.

FIG. 4 is a process chart of the third embodiment. In this embodiment, the gate insulating film 3 is removed at an early stage of the process by using a P-type TFT and an N-type TFT.
The difference from the above embodiment is that the process is performed simultaneously with the FT.

The state shown in FIG. 4A is the same as that shown in FIG. Then, as shown in FIG.
Is used as a mask, N-type impurity ions such as, for example, phosphorus ions are implanted at a high acceleration and a low concentration through the silicon oxide film 3 by ion doping. As a result, the regions 7 and 8 become N-type. This condition is equivalent to that of FIG. 2B, for example, about 100 kV and about 2 × 10 ¹⁴ cm ⁻² . Thus, the region 7 becomes an LDD region thereafter.

As shown in FIG. 4C, the gate electrode 4 is used as a mask by the above-described plasma etching method.
The silicon oxide film 3 is removed. Thus, the silicon oxide film 3 in the P-type and N-type TFT regions is removed. This process is different from the first embodiment.

As shown in FIG. 4D, a P-type TFT region is covered, a gate electrode 4 of an N-type TFT and a first resist mask film M1 covering both sides thereof are formed. N-type impurity ions are implanted at a high concentration.
The conditions are, for example, at a speed of 20 kV and 2 × 10 ¹⁵ c
m- ² . As a result, a high-concentration source / drain region 6 and a low-concentration LDD region are formed in the N-type TFT.

As shown in FIG. 4E, the N-type T
A second resist mask film M2 covering the FT region is formed, and a high concentration of P-type impurity ions such as boron ions is implanted into the P-type TFT region using the gate electrode 4 as a mask. The condition is, for example, that the acceleration is 10
It is about kV, and the concentration is as high as about 4 × 10 ¹⁵ cm ⁻² .

Thereafter, through a general annealing step, the source / drain regions 6, 8 of the N-type and P-type TFTs and the LDD region of the N-type TFT are activated.
By introducing boron ions, which are P-type impurities, at a high concentration, the region 8 lightly doped with N-type in FIG. 4B is inverted to P-type.

Thereafter, as shown in FIG. 4F, an interlayer insulating film 9 is formed, an electrode contact hole 10 is formed, and a wiring 11 made of aluminum or the like is formed.

FIG. 5 is a diagram showing a part of the process of the fourth embodiment. This embodiment is shown in FIG.
(A), (b), and (c) of the third embodiment shown in FIG.
Is different from the third embodiment in that the order of the steps (b) and (c) is reversed.

That is, the state shown in FIG.
Same as (a). Thereafter, as shown in FIG. 5B, the gate oxide film 3 is removed by the gas plasma etching method using the gate electrode 4 as a mask. Then, using the gate electrode 4 as a mask, low-concentration N-type impurity ions are implanted over the entire surface by ion doping. This condition is, for example, that phosphorus ions are accelerated at an acceleration of 20 kV for 2
The density is about 10 ¹⁴ cm ^-2 . In this process,
The acceleration is relatively small because it does not pass through the gate insulating film 3.

The subsequent processes are shown in FIGS.
Therefore, the description is not repeated here.

[0038]

As described above, according to the present invention, N
Region and source / drain region of P-type TFT and P
Since the source and drain regions of the TFT of the type can be formed by using two masks, the cost of the process can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a TFT substrate of a general liquid crystal display device.

FIG. 2 is a process diagram of an embodiment of the present invention.

FIG. 3 is a process chart of a second embodiment.

FIG. 4 is a process chart of a third embodiment.

FIG. 5 is a diagram showing a part of a process according to a fourth embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Semiconductor thin film 3 Gate insulating film 4 Gate electrode 9 Interlayer insulating film 10 Contact hole M1 First mask film M2 Second mask film

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device having two conductive thin film transistors on an insulating substrate, comprising: a semiconductor thin film on the insulating substrate, a gate insulating film thereon, and a gate electrode thereon. Forming, using the gate electrode as a mask, injecting a first conductivity type impurity into the semiconductor thin film at a first concentration, and a gate electrode of the first conductivity type thin film transistor and both sides thereof And forming a first mask film covering the semiconductor thin film of the second conductivity type thin film transistor, and using the first mask film as a mask, forming the first mask film in the semiconductor thin film of the first conductivity type thin film transistor. Implanting one conductivity type impurity at a second concentration higher than the first concentration, and a second mask film covering the semiconductor thin film of the first conductivity type thin film transistor. Forming, using the second mask film as a mask, the second conductivity type impurity in the semiconductor thin film of the second conductivity type thin film transistor at a third concentration higher than the first concentration. Implanting the semiconductor into the second conductivity type semiconductor. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of etching and removing the gate insulating film using the first mask film as a mask. 3. The method according to claim 1, further comprising a step of etching and removing the gate insulating film using the second mask film and a gate electrode of the second conductive type thin film transistor as a mask. A method for manufacturing a semiconductor device. 4. The interlayer insulating film according to claim 1, wherein an interlayer insulating film is formed after the step of implanting the impurity, and an opening reaching a source / drain region of the first and second conductive type thin film transistors is formed in the interlayer insulating film. A method for manufacturing a semiconductor device, further comprising a step of forming a film and a gate insulating film. 5. The method according to claim 1, wherein after the step of implanting a first conductivity type impurity into the semiconductor thin film at a first concentration using the gate electrode as a mask,
A method of manufacturing a semiconductor device, comprising a step of removing the gate insulating film using the gate electrode as a mask. 6. The method according to claim 1, wherein, before the step of implanting a first conductivity type impurity into the semiconductor thin film at a first concentration using the gate electrode as a mask,
A method of manufacturing a semiconductor device, comprising a step of removing the gate insulating film using the gate electrode as a mask.