JPH10257578A - On/off control data receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control plural on/off controlled devices through a common control line. SOLUTION: A transmitter 12 transmits a header, address data and 1-bit on/off control data to a control line 11 sequentially, plural receivers 131 -13n are connected to the control line 11. In each of the receivers the header is detected through a header detection part 31 from an input signal, a clock signal is detected through a clock detection part 32 for every bit, a shift register 33 is cleared by the detection of the header, the input signal is fetched to the shift register 33 with the detection clock, a compactor part 36 compares the fetched address data with its own address in a register 35 and when they coincide, the succeeding on/off control data are latched to a data fetch part 34 and controlled devices 141 -14n connected to each of the receivers 131 -13n are controlled as the start, stop or flickering or the like corresponding to the latched contents.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to, for example, flash control of a neon light or an electric light, start / stop control of a motor or a heater, and on / off of a digital input signal sent from a remote place to the self. The present invention relates to an on / off control data receiver for detecting control data and controlling on / off of a controlled device.

[0002]

2. Description of the Related Art Conventionally, in order to remotely control on / off of a neon lamp and an electric lamp, and control of starting and stopping a motor and a heater, a control line must be separately provided for each controlled device. I was going.

[0003]

Conventionally, wiring is individually connected to controlled devices. Therefore, if there are many controlled devices, the number of wirings becomes large and complicated, and there is a risk of erroneous wiring. In addition, there was a problem that the price became high.

[0004]

According to the present invention, a header is detected from a digital input signal by a header detector,
Further, the clock is detected from the input signal by the clock detection unit, the shift register is cleared by the detected header, the shift register is shifted by the detected clock, and the input signal is taken into the shift register. The comparison unit compares the inside of the shift register with the address stored in the address register,
When a match is detected by the comparison, the data of the input signal is fetched by the data fetch unit for one clock by the match detection output, and the controlled device is turned on / off in accordance with the content of the fetched data.

[0005]

FIG. 1 shows a control system to which the present invention is applied. Single common control line 11 of the control data transmitter 12 and a plurality of on-off control data receiver 13 ₁ to 13 _n according to the invention is connected. As shown in FIG. 2A, the control data transmitter 12 sequentially sends a header 21, address data 22, and 1-bit on / off data 23, and a clock component for each bit such as a bi-phase code or a Manchester code. Send out the included digital data signal. The header 21 has a high level longer than the data “0”.

The on / off control data receivers 13 _{1 to} 13 _n according to the present invention have the same configuration, and each receiver has a unique address. As shown the specific structure in the receiver 13 _1, the digital input signal from the control line 11 is the header detection unit 31, the clock detection unit 32, the shift register 33, is supplied to the data acquisition unit 34. The header detection unit 31 includes, for example, an integration circuit. When the integration output exceeds a predetermined level, the header detection unit 31 determines that the header 21 has been input and detects the header 21. The clock detector 32 detects a clock for each bit (data) of the input signal, for example, from the input signal of FIG. 2A as shown in FIG. 2B. Address given in advance to the receiver 13 ₁ are stored in the address register 35.

When the header is detected by the header detection unit 31, the contents of the shift register 33 are cleared by the detection output, and the shift register 33 is shifted by the clock detected by the clock detection unit 32.
Therefore, the address data 22 in the input signal is taken into the shift register 33. When data of a predetermined number of bits, that is, the number of bits constituting the address data 22 is taken into the shift register 33, the shift register 3
The comparison unit 36 compares the address data 22 fetched in 3 with its own address in the address register 35. When they match, the on / off data 23 following the address data 22 is taken into the data take-in unit (for example, a 1-bit latch circuit) 34 with the match detection output.

[0008] Data captured by the data capturing unit 34
Receiver 13 according to the contents of₁Connected to
Equipment 14₁Is controlled on / off. Receiver in the same way
13 _Two~ 13_nTo the content of the data captured
Depending on the controlled device 14_Two~ 14 _nIs controlled on / off.

[0009]

As described above, according to the present invention, an address addressed to itself is detected from an input signal, and only the on / off data at that time is taken in. Therefore, a common control is performed for each controlled device. The wire 11 can be used, the wiring is very simple, and there is no possibility of erroneous wiring.

Further, according to such a configuration, even if the control data signal is set at a high speed, each receiver can operate without being affected by noise and without malfunction, thereby enabling high-speed control.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a control system configured using an on / off control data receiver according to an embodiment of the present invention.

FIG. 2A is a diagram showing an example of a transmission control data signal of a transmitter, and FIG. 2B is a diagram showing an example of a reproduction clock in a receiver corresponding to the transmission control data.

Claims (1)

[Claims] 1. An on / off control data receiver for controlling on / off of a controlled device based on received on / off control data, a header detector for detecting a header of a digital input signal, and a clock detector for detecting a clock from the input signal. A shift register that is cleared by the detected header, shifted by the detected clock, and receives the input signal, an address register that stores its own address, a content of the shift register and a content of the address register. A comparison unit that compares the address and detects a match, and a match detection output of the comparison unit, which outputs 1
An on / off control data receiver, comprising: a data capturing unit that captures data only by a clock and controls on / off of the controlled device according to the content of the captured data.