JPH10261714A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a method for manufacturing a semiconductor device having fine, high aspect ratio and highly reliable contacts. A first contact hole is opened in a first conductive layer on an insulating film formed on a semiconductor substrate, and a second conductive layer is formed on a side wall of the first contact hole.
3a is formed, the opening diameter of the first contact hole CH1 is reduced, the second contact hole CH2 is opened in the insulating film 25 using the second conductive layer 33a as a mask, and the second contact hole CH2 is formed on the first conductive layer 32 and the second conductive layer 33a. In addition, the third conductive layer 34 is formed in the second contact hole CH2 and the first contact hole CH1 which communicate with each other, and the concave portion formed on the surface of the third conductive layer 34 is filled with the flattening layer 26a. The flattening layer 26 of the concave portion of the third conductive layer, leaving the conductive layer.
a, the first conductive layer 32, the second conductive layer 33a, and the third conductive layer 34 are removed by etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having fine high aspect ratio contacts.

[0002]

2. Description of the Related Art As the integration and performance of semiconductor devices have advanced as seen in recent VLSIs and the like, fine processing of semiconductor devices has become an essential condition. In order to finely process a semiconductor device, for example, it is necessary to finely process a wiring portion while reducing a gate width of a gate electrode of a transistor and an area occupied by a capacitor in a DRAM or the like.

For example, a DRAM (Dynamic Random Acceses)
s Memory), as a process driver in a semiconductor device, has been increasingly miniaturized and increased in capacity in recent years. DRAM is a field-effect transistor (M) having a metal-oxide-semiconductor stack for switching.
It has a memory cell structure having an OSFET) and a memory capacitor. With the increase in the degree of integration, the size of the memory cell is reduced, and the area occupied by the memory capacitor is also reduced.

In order to reduce the area occupied by the memory capacitor, various structures have been developed for the electrode structure. Conventionally, a planar type having a planar structure was used, but now, the storage node electrode is three-dimensionally used and the side wall surface of the storage node electrode is used, without increasing the area occupied by the capacitor. A stack type, a trench type, and the like, which can increase a storage capacity by increasing a surface area, have been developed.

Among the above types, the stack type is a CUB (capacito) having a memory capacitor below a bit line.
r under bitline), COB (capacitor over bitline) with a memory capacitor above the bit line
Development to the method is progressing. In case of COB stack type,
Since the capacitor is formed after the bit line, there is an advantage that the largest capacitor determined by microfabrication can be formed on the cell region. For example, various types such as a cylinder type and a fin type have been developed.

In a semiconductor device having a COB type memory capacitor as described above, a capacitor is formed in an upper layer such as a gate electrode and a bit line. Therefore, it is necessary to open a contact hole having a high aspect ratio in order to form a storage node contact of a memory capacitor on a thick interlayer insulating film covering a gate electrode, a bit line, and the like. Furthermore, in order to increase the degree of integration of semiconductor devices, it is important to reduce the area occupied by the memory capacitor and also to miniaturize the wiring parts such as contacts. It is becoming important.

As described above, as a technique for forming a fine contact hole having a high aspect ratio, a layer serving as a mask for forming the contact hole is formed on the inner wall of the contact hole to reduce the diameter of the contact hole. Opening methods have been developed. less than,
A method for opening the contact hole by reducing the diameter will be described with reference to the drawings.

First, as shown in FIG. 5A, an element isolation insulating film 2 is formed on a semiconductor substrate 10 by a LOCOS method or the like.
After the formation of 1, ion implantation for forming an active region of the transistor and improving punch-through breakdown voltage is performed. A gate insulating film 22 is formed on the active region by a thermal oxidation method or the like, and, for example, polysilicon and tungsten silicide are respectively deposited on the active layer by a CVD method. Silicon gate 31a and silicide gate 31b
A polycide gate electrode 31 is formed. Next, ion implantation is performed using the gate electrode 31 as a mask,
The source / drain diffusion layer 11 is formed to form a field effect transistor. Next, for example, silicon oxide is deposited on the entire surface by covering the gate electrode 31 by a CVD method,
A gate covering insulating film 23 is formed, and further, for example, silicon nitride is deposited on the entire surface by CVD to form an etching stopper layer 24.

Next, as shown in FIG. 5B, for example, silicon oxide is deposited on the etching stopper layer 24 by CVD.
Then, the interlayer insulating film 25 is formed by flattening by reflow or etch back. On the upper layer, for example, polysilicon is deposited by a CVD method to form a first layer.
The conductive layer 32 is formed.

Next, as shown in FIG. 5C, a resist film is patterned on the first conductive layer 32 to have a diameter of, for example, 0.3 μm, and etching such as RIE (reactive ion etching) is performed. First contact hole CH penetrating through first conductive layer 32 and opening to above interlayer insulating film 25
Open one. At this time, the etching is stopped when a part of the upper surface of the etching stopper 24 is exposed.

Next, as shown in FIG. 6 (d), for example, polysilicon is deposited on the entire surface of the upper layer of the first conductive layer 32 and the inside of the first contact hole CH1 by the CVD method so as to have a thickness of, for example, 110 nm. Then, a second conductive layer 33 is formed.

Next, as shown in FIG. 6E, the second conductive layer 33 is etched by RIE or the like so as to remain on the side wall of the first contact hole CH1.
The second conductive layer 33a of the sidewall is formed.

Next, as shown in FIG.
Using a CR (Electron Cyclotron Resonance) type plasma etching apparatus, a second contact hole CH2 that exposes the semiconductor substrate 10 through the interlayer insulating film 25 is opened. At this time, the opening diameter of the second contact hole CH2 is, for example, about 0.1 μm, and a fine contact hole can be formed by reducing the diameter of the etching mask by forming the second conductive layer 33a of the sidewall.

Next, as shown in FIG. 7 (g), for example, polysilicon is formed by a CVD method on the first conductive layer 32 and the upper layer of the second conductive layer 33a of the side wall and the second contact hole and the first contact which communicate with each other. The third conductive layer 34 is formed on the entire surface in the hole.

In the subsequent steps, the entire surface is etched back by, for example, etching such as RIE, the conductive layer outside the contact hole is removed, and the second conductive layer 33a of the sidewall and the third conductive layer are formed in the contact hole. A buried wiring layer 35 composed of the layer 34a is formed.

[0016]

However, when a contact is formed by using the above-described method of forming a sidewall on the inner wall of the contact hole, narrowing the diameter of the contact hole, and forming an open wiring layer by opening. 7
As shown in (g), since the third conductive layer 34 has a dent above the contact hole, the entire surface is etched back by etching such as RIE to remove the conductive layer outside the contact hole. FIG.
As shown in (h), the recess remains as it is above the contact hole of the buried wiring layer 35, causing plug loss. In particular, in a contact hole in which the opening diameter at the top of the contact hole is wide as shown in FIG.

The manner in which the above-described plug loss occurs will be described with reference to FIG. As shown in FIG. 8A, when the buried conductive layer 36 is formed in the contact hole opened in the interlayer insulating film 27, a recess H is generated above the contact hole. Next, when the conductive layer outside the contact hole is removed by etching back, the dent H remains as it is, as shown in FIG. If the upper layer wiring 37a is further formed on the upper layer of the buried wiring layer 36a in which the plug loss PL has occurred, as shown in FIG. Contact failures, such as failure of wiring, and the reliability of wiring is greatly reduced. It also has an adverse effect on the planarization of the upper layer.

As shown in FIG. 7 (h), if the over-etching amount is reduced to suppress the above-mentioned plug loss, short-circuiting may occur in portions other than the contact hole opening due to the problem of uniformity of etching. There is a problem that such a conductive layer material is left to form the remaining conductor 34b.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. Accordingly, an object of the present invention is to form a side wall on the inner wall of a contact hole, reduce the diameter of the contact hole and open the buried wiring layer. The method of forming the plug is suppressed, the plug loss is suppressed, and a conductive layer material that may cause a short circuit in a portion other than the contact hole opening is not left. An object of the present invention is to provide a method for manufacturing a semiconductor device having a contact.

[0020]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an insulating film on a semiconductor substrate and forming a first conductive layer on the insulating film. Performing a step of forming a first contact hole in the first conductive layer, forming a second conductive layer on a side wall of the first contact hole, and reducing an opening diameter of the first contact hole; Forming a second contact hole in the insulating film using the second conductive layer as a mask; and forming the second contact hole on the first conductive layer and the second conductive layer and in the second contact hole and the first contact hole communicating with each other. Forming a third conductive layer, forming a planarization layer on the third conductive layer by filling the recess formed on the surface of the third conductive layer, and forming a recess on the surface of the third conductive layer Flattening embedded in Removing the flattening layer while leaving a flattened surface of the third conductive layer, and flattening the recessed portion while leaving the conductive layer inside the first contact hole and the second contact hole. Etching the first layer, the first conductive layer, the second conductive layer, and the third conductive layer.

The method of manufacturing a semiconductor device according to the present invention is as follows.
A flattening layer is provided on the third conductive layer, and a recess formed on the surface of the third conductive layer above the contact hole is buried with the flattening layer, so that the conductive layer outside the contact hole is etched back. It is possible to suppress the occurrence of plug loss due to the fact that the dent remains as it is when removing. In this case, it is possible to simultaneously etch away by setting the etching conditions such that the third conductive layer and the flattening layer have the same etching selectivity, and it is possible to perform etching from the concave portion generated on the surface of the third conductive layer. However, it does not mean that plug loss occurs first, or the flattening layer formed in the concave portion formed on the surface of the third conductive layer remains and the conductive layer outside the contact hole cannot be removed. Further, when the conductive layer outside the contact hole is removed, sufficient over-etching may be performed to avoid leaving a conductive layer material that may cause a short circuit in a portion other than the contact hole opening. Does not exacerbate plug loss.

In the above-described method for manufacturing a semiconductor device, preferably, the flattening layer is formed by SOG (Spin On Glass). By applying SOG, a recess formed on the surface of the third conductive layer above the contact hole can be buried, and a planarization layer having a flat surface can be formed.

In the method of manufacturing a semiconductor device described above, preferably, the flattening layer is formed of a resist film. By applying the resist film, a recess formed on the surface of the third conductive layer above the contact hole can be buried, so that a flattening layer having a flat surface can be formed.

Further, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming an insulating film on a semiconductor substrate; forming a first conductive layer on the insulating film; Forming a first contact hole penetrating through the first conductive layer and reaching above the insulating film; forming a second conductive layer on a side wall of the first contact hole; Narrowing, forming a second contact hole in the insulating film using the second conductive layer as a mask, and forming the second contact hole on the first conductive layer and the second conductive layer and communicating with each other. Forming a third conductive layer in the first contact hole, forming a planarization layer on the third conductive layer by filling a recess formed in the surface of the third conductive layer; Of the surface of the conductive layer Removing the planarization layer while leaving the planarization layer embedded in the portion, and planarizing the surface of the third conductive layer; and leaving the conductive layer inside the first contact hole and the second contact hole. Etching the flattening layer, the first conductive layer, the second conductive layer, and the third conductive layer left in the recess.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Since the first contact hole penetrating the first conductive layer and reaching the upper part of the insulating film is formed, the final contact hole formed by opening the second contact hole has a diameter of an upper portion as compared with a lower portion. Is increased, and according to the conventional contact forming method, a shape in which plug loss appears remarkably is obtained. However, according to the present invention, even in the contact having such a shape, the recess formed on the surface of the third conductive layer above the contact hole is buried with the flattening layer, so that it is etched back to form the outside of the contact hole. When the conductive layer is removed, it is possible to suppress the occurrence of plug loss due to the dent remaining as it is. Further, plug loss is not deteriorated even if sufficient over-etching is performed to avoid leaving a conductive layer material that may cause a short circuit in a portion other than the contact hole opening.

In the method of manufacturing a semiconductor device described above, preferably, the flattening layer is formed by SOG or a resist film. By flattening with an SOG or a resist film, a recess formed on the surface of the third conductive layer above the contact hole can be buried, and a flattening layer having a flat surface can be formed.

Further, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film on a semiconductor substrate; a step of forming a first conductive layer on the insulating film; A step of forming a first contact hole in the first conductive layer, a step of forming a second conductive layer on a side wall of the first contact hole to reduce an opening diameter of the first contact hole, and a step of forming the second conductive layer Opening a second contact hole in the insulating film using a mask as a mask; and forming a third conductive layer on the first conductive layer and the second conductive layer, and in the second contact hole and the first contact hole communicating with each other. Forming a flattened layer on the third conductive layer by burying the recess formed on the surface of the third conductive layer; and burying the flattened layer on the surface of the third conductive layer. Leaving a planarization layer Removing the planarization layer and planarizing the surface of the third conductive layer; partially etching and removing the third conductive layer; and etching and removing the planarization layer embedded in the recess. And etching the first conductive layer, the second conductive layer, and the third conductive layer while leaving the conductive layers inside the first contact hole and the second contact hole.

The method of manufacturing a semiconductor device according to the present invention is as follows.
There is a difference in the etching selectivity between the third conductive layer and the planarizing layer,
Even under the condition that both layers cannot be etched at the same etching rate, first, part of the third conductive layer is removed by etching, and then, the flattened layer in the concave portion formed on the surface of the third conductive layer is removed by etching. By doing so, it is possible to suppress the occurrence of plug loss, in which the dent formed on the surface of the third conductive layer above the contact hole remains as it is.
Further, plug loss is not deteriorated even if sufficient over-etching is performed to avoid leaving a conductive layer material that may cause a short circuit in a portion other than the contact hole opening.

In the above method for manufacturing a semiconductor device, preferably, the flattening layer is formed by SOG or a resist film. By flattening with an SOG or a resist film, a recess formed on the surface of the third conductive layer above the contact hole can be buried, and a flattening layer having a flat surface can be formed.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present embodiment. Semiconductor substrate 1
There is an active region separated by an element isolation insulating film 21 such as LOCOS on the polysilicon gate 31a and the tungsten silicide gate 3 via a gate insulating film 22.
A polycide gate electrode 31 made of 1b is formed. A source / drain diffusion layer 11 is formed in the semiconductor substrate 10 on the side of the gate electrode 31 to form a field effect transistor. A gate coating insulating film 23 made of, for example, silicon oxide and an etching stopper layer 24 made of silicon nitride are formed so as to cover the gate electrode 31, and an interlayer insulating film 25 made of, for example, silicon oxide is formed thereon. A contact hole reaching the semiconductor substrate 10 is opened in the interlayer insulating film 25, and a buried wiring layer 35 including a second conductive layer 33a and a third conductive layer 34a of a sidewall is buried in the contact hole.

In such a semiconductor device, plug loss of the embedded wiring layer formed in the contact hole is suppressed,
A semiconductor device having a fine and high aspect ratio contact with which the reliability of wiring is ensured, in which a conductive layer material is not left in a portion other than an opening of a contact hole.

The method for manufacturing the above semiconductor device will be described below with reference to the drawings.

First, as shown in FIG. 2A, after an element isolation insulating film 21 is formed on a semiconductor substrate 10 by a LOCOS method or the like, an active region of a transistor is formed and punch-through breakdown voltage is improved. Is performed. A gate insulating film 22 is formed on the active region by thermal oxidation or the like, and, for example, polysilicon and tungsten silicide are respectively deposited on the gate insulating film 22 by a CVD method. Gate 31a and silicide gate 31b
A polycide gate electrode 31 is formed. Next, ion implantation is performed using the gate electrode 31 as a mask,
The source / drain diffusion layer 11 is formed to form a field effect transistor. Next, for example, silicon oxide is deposited on the entire surface by covering the gate electrode 31 by a CVD method,
A gate covering insulating film 23 is formed, and further, for example, silicon nitride is deposited on the entire surface by CVD to form an etching stopper layer 24.

Next, as shown in FIG. 2B, for example, silicon oxide is deposited on the etching stopper layer 24 by CVD.
Then, the interlayer insulating film 25 is formed by flattening by reflow or etch back. On the upper layer, for example, polysilicon is deposited by a CVD method to form a first layer.
The conductive layer 32 is formed.

Next, as shown in FIG. 2C, a resist film is patterned on the first conductive layer 32 to a diameter of, for example, 0.3 μm, and etching such as RIE (reactive ion etching) is performed. First contact hole CH1 penetrating through first conductive layer 32 and reaching above interlayer insulating film 25
Open. At this time, the etching is stopped when a part of the upper surface of the etching stopper 24 is exposed.

Next, as shown in FIG. 3D, for example, polysilicon is deposited on the entire surface of the first conductive layer 32 and the inside of the first contact hole CH1 by a CVD method so as to have a thickness of 110 nm. The two conductive layers 33 are formed.

Next, as shown in FIG. 3E, the second conductive layer 33 is etched by RIE or the like so as to leave the side wall portion of the first contact hole CH1, and the second conductive layer 33 of the side wall is etched. The layer 33a is formed. Thereby, the opening diameter of the first contact hole is reduced to about 0.1 μm.
m.

Next, as shown in FIG.
Using a CR (Electron Cyclotron Resonance) type plasma etching apparatus, a second contact hole CH2 that exposes the semiconductor substrate 10 through the interlayer insulating film 25 is opened. At this time, the opening diameter of the second contact hole CH2 is, for example, about 0.1 μm, and a fine contact hole can be formed by using the second conductive layer 33a of the sidewall as a mask for the contact hole opening.

Next, as shown in FIG. 4G, for example, polysilicon is formed by CVD on the first conductive layer 32 and the upper layer of the second conductive layer 33a of the side wall, and the second conductive layer 33a.
The third conductive layer 34 is formed by filling the contact hole CH2 and the first contact hole and depositing them over the entire surface. At this time, the third conductive layer 3 above the contact hole
The surface of No. 4 has a dent.

Next, as shown in FIG. 4H, for example, SOG (SpinOn Glass) is applied on the entire surface of the third conductive layer 34 to form a flattening film 26. At this time, SO
Since G is liquid, the third part above the contact hole
The SOG uniformly penetrates into the dents formed on the surface of the conductive layer, the unevenness is leveled, and the flattening film 26 having a flat surface without dents can be formed.

Next, as shown in FIG. 4I, etch back is performed until the third conductive layer 34 is exposed,
SOG only in the concave portion 26a at the top of the contact hole
The remaining flattening film 26 is removed except for the above.

Next, the entire surface is etched back by etching such as RIE to remove the conductive layer outside the contact hole, and the second conductive layer 33a and the third conductive layer 34a of the sidewall are formed in the contact hole. The semiconductor device shown in FIG. 1 is formed by forming the embedded wiring layer 35. At this time, by selecting etching conditions under which the etching selectivity of the polysilicon forming the first to third conductive layers and the like and the SOG forming the planarizing film 26a in the recessed portion of the third conductive layer becomes substantially the same, It is possible to form the buried wiring layer 35 having a flattened plug loss suppressed above the contact hole.

The first to third conductive layers 32, 33a, 3
4 and the flattening film 2 in the concave portion of the third conductive layer
FIG. 4 (i) shows a case in which the etching conditions under which the etching selectivity with SOG of FIG.
First, a part of the third conductive layer 34 made of polysilicon or the like is partially etched away from the process shown in FIG.
Flattening film 26 at the concave portion of the third conductive layer made of OG or the like
A similar effect can be obtained by removing a by etching.

In the subsequent steps, a second interlayer insulating film is formed, and a contact can be stacked on the flattened contact.

As described above, as shown in FIG. 1, the plug loss is suppressed, and the conductive layer material is not left in portions other than the contact hole openings. A secured contact can be formed. The above-mentioned contact can solve the conventional problems by applying a liquid such as SOG, and can be realized at low manufacturing cost.

The present invention can be applied to any semiconductor device having a contact hole, such as a MOS transistor semiconductor device such as a DRAM, a bipolar semiconductor device, or an A / D converter. It is possible to provide a semiconductor device having a fine, high aspect ratio and highly reliable contact to a semiconductor device which has been miniaturized, miniaturized, and miniaturized.

The present invention is not limited to the above embodiment. For example, although SOG is used to fill a recess formed in the third conductive layer, a resist film may be used. In addition, a material that can be liquefied or liquefied in a normal state and that can fill a recess formed in the third conductive layer can be used. In the opening step of the first contact hole, an opening is provided by etching that penetrates the first conductive layer 32 and reaches above the interlayer insulating film 25.
It may be stopped when the surface of the interlayer insulating film 25 is exposed by penetrating the conductive layer 32, or may be stopped before penetrating the first conductive layer 32. Each of the first to third conductive layers can have a multilayer structure. Further, it is also possible to combine a self-aligned contact opening technique in which the opening of the second contact hole is once stopped by the etching stopper film and the second contact hole is opened again. Others
Various changes can be made without departing from the spirit of the present invention.

[0049]

According to the present invention, plug loss is suppressed by using a method in which a sidewall is formed on the inner wall of a contact hole, the diameter of the contact hole is reduced and an opening is formed to form a buried wiring layer. A fine semiconductor device having a high aspect ratio and highly reliable contact, in which a conductive layer material that causes a short circuit is not left in a portion other than the opening, can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to the present invention. FIG. 2A illustrates a process up to a process of forming an etching stopper layer, and FIG.
(C) shows the process up to the step of opening the first contact hole.

FIG. 3 shows a step that follows the step shown in FIG. 2;
Until the conductive layer formation step, (e) shows the second side wall.
(F) shows up to the step of forming the second contact hole up to the step of forming the conductive layer.

FIG. 4 shows a step that follows the step shown in FIG. 3;
(H) shows up to the step of forming a flattening film, and (i) shows up to the step of etching the flattening film.

FIG. 5 is a cross-sectional view showing a manufacturing process of a conventional method of manufacturing a semiconductor device, in which (a) shows a process up to the formation of an etching stopper layer, and (b) shows a process up to a process of forming a first conductive layer.
(C) shows the process up to the step of opening the first contact hole.

FIG. 6 shows a step that follows the step shown in FIG. 5;
Until the conductive layer formation step, (e) shows the second side wall.
(F) shows up to the step of forming the second contact hole up to the step of forming the conductive layer.

FIG. 7 shows a step that follows the step shown in FIG. 6;
(H) shows up to the step of forming a conductive layer by etching and up to the step of forming a buried wiring layer by etching.

FIGS. 8A and 8B are diagrams for schematically explaining the formation of plug loss according to a conventional example, in which FIG. 8A shows up to a step of forming a buried wiring layer, FIG. (C) shows the process up to the step of forming the upper wiring.

[Explanation of symbols]

10: semiconductor substrate, 11: source / drain diffusion layer, 2
DESCRIPTION OF SYMBOLS 1 ... Element isolation insulating film, 22 ... Gate insulating film, 23 ... Gate covering insulating film, 24 ... Etching stopper film, 25 ...
Interlayer insulating film, 26: flattening film, 26a: flattening film at the concave portion of the third conductive layer, 27, 28: insulating film, 31: gate electrode, 32: first conductive layer, 33, 33a: second conductive layer,
34: third conductive layer, 35: embedded wiring layer, 36, 36
a: embedded wiring layer, 37a: upper wiring, CH1, CH
2: Contact hole, H: recess, PL: plug loss.

Claims (9)

[Claims] A step of forming an insulating film on the semiconductor substrate; a step of forming a first conductive layer on the insulating film; a step of opening a first contact hole in the first conductive layer; Forming a second conductive layer on the side wall of one contact hole and reducing the opening diameter of the first contact hole; and opening a second contact hole in the insulating film using the second conductive layer as a mask; Forming a third conductive layer on the first conductive layer and the second conductive layer and in the second contact hole and the first contact hole communicating with each other; and a concave portion formed on the surface of the third conductive layer. Forming a flattening layer on the third conductive layer by embedding the third conductive layer; removing the flattening layer while leaving the flattening layer buried in the concave portion on the surface of the third conductive layer; Flattening the surface of the The planarization layer, the first conductive layer, the second conductive layer, and the third conductive layer left in the concave portion are removed by etching while leaving the conductive layers inside the first contact hole and the second contact hole. And a method for manufacturing a semiconductor device. 2. The method according to claim 1, wherein said planarizing layer is formed by SOG. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said planarizing layer is formed of a resist film. 4. A step of forming an insulating film on a semiconductor substrate, a step of forming a first conductive layer on the insulating film, and a first step of penetrating the first conductive layer and reaching above the insulating film. A step of forming a contact hole; a step of forming a second conductive layer on a side wall of the first contact hole to reduce an opening diameter of the first contact hole; Opening a second contact hole; forming a third conductive layer on the first conductive layer and the second conductive layer and in the second contact hole and the first contact hole communicating with each other; Forming a flattening layer on the third conductive layer by burying a recess formed in the surface of the third conductive layer; and leaving the flattening layer buried in the recess on the surface of the third conductive layer. The third layer is removed Planarizing the surface of the conductive layer; and a planarizing layer left in the recess, leaving the conductive layer inside the first contact hole and the second contact hole, the first conductive layer, and the second conductive layer. Etching the layer and the third conductive layer. 5. The method according to claim 4, wherein said planarizing layer is formed by SOG. 6. The method of manufacturing a semiconductor device according to claim 4, wherein said flattening layer is formed of a resist film. 7. A step of forming an insulating film on a semiconductor substrate; forming a first conductive layer on the insulating film; opening a first contact hole in the first conductive layer; Forming a second conductive layer on the side wall of one contact hole and reducing the opening diameter of the first contact hole; and opening a second contact hole in the insulating film using the second conductive layer as a mask; Forming a third conductive layer on the first conductive layer and the second conductive layer and in the second contact hole and the first contact hole communicating with each other; and a concave portion formed on the surface of the third conductive layer. Forming a flattening layer on the third conductive layer by embedding the third conductive layer; removing the flattening layer while leaving the flattening layer buried in the concave portion on the surface of the third conductive layer; Flattening the surface of the A step of partially removing the third conductive layer by etching; a step of etching and removing the planarization layer embedded in the concave portion; leaving a conductive layer inside the first contact hole and the second contact hole. , The first conductive layer, the second
Etching the conductive layer and the third conductive layer. 8. The method according to claim 7, wherein said planarizing layer is formed by SOG. 9. The method for manufacturing a semiconductor device according to claim 7, wherein said flattening layer is formed of a resist film.