JPH10270462A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of operating speed and improve frequency dispersion of drain conductance and drain lag, by a method wherein a second conductivity type semiconductor layer is not formed in a part just under a first conductivity type drain region. SOLUTION: This transistor is provided with the following; a heavily doped N-type source region 4s linked with a lightly doped N-type source region 5s, a heavily doped N-type drain region 4d linked with lightly doped N-type drain region 5d, and a source electrode 7s and a drain region 7d which make ohmic contact with the heavily doped N-type source region 4s and the heavily doped N-type drain region 4d, respectively. The heavily doped N-type source region 4s and the lightly doped N-type drain region 5d are formed in the surface part of a p-type semiconductor layer 8A, which is not formed on the bottom surface of the heavily doped N-type drain region 4s. Thereby, deterioration of operating speed is prevented, and frequency dispersion of drain conductance and drain lag can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a field effect transistor.

[0002]

2. Description of the Related Art Gallium arsenide (GaAs) MESFET
(Metal Semiconductor FET ((Metal Se
HFET (heterojunction FET) and HJFET (heterojunction FET).
on FET)) is a vibrant research and development of high-speed, low-power ICs and high-output devices in the microwave and millimeter-wave bands, taking advantage of the fact that GaAs has a higher electron mobility than silicon (Si). Has been advanced. In particular, in recent years, the demand for GaAs FETs has been increasing more and more due to the spread of portable devices requiring low power consumption and the expansion of application fields of wireless communication.

[0003] GaAs FETs are usually formed on a semi-insulating substrate. The use of a semi-insulating substrate reduces G from the viewpoint of reducing parasitic capacitance and operating the element at high speed.
This is an advantage of aAsFET. However, on the other hand, the semi-insulating substrate causes unstable operation of the device. A semi-insulating substrate is obtained by compensating for shallow impurity levels with deep impurity levels (traps). Since the deep impurity level contained in the substrate requires much longer time to capture and emit carriers than the operation speed of the device, the frequency dispersion of the drain conductance at a low frequency and the response delay (drain lag) of the drain current are reduced. This caused a serious problem in practical use of the device.

Conventionally, in order to solve such a problem, a technique is provided in which a p-type buried layer is provided between a semi-insulating substrate and an active layer so that changes in trapped charges in the substrate are not directly transmitted to the active layer. Has often been used.

FIG. 6 shows a conventional ME having a p-type buried layer.
It is sectional drawing which shows SFET.

An insulating region 2 is formed in a semi-insulating GaAs substrate 1 using boron ion implantation to divide an active region, and a p-type buried layer 8 is formed using beryllium ion implantation. An n-type channel layer 3 is formed using silicon ion implantation, a gate electrode 6 is formed, and a high-concentration drain region 4d, a high-concentration source region 4s, a low-concentration drain region 5d, a low-concentration source region 5s, and a drain are formed. Electrode 7
d, forming a source electrode 7s; Since the p-type buried layer 8 is coupled to the high-concentration source region 4s by capacitive coupling due to the PN junction and leakage current, the potential is fixed. Thereby, frequency dispersion and drain lag are improved.

FIG. 7 shows a conventional H type having a p-type buried layer.
It is sectional drawing which shows a JFET.

On a semi-insulating GaAs substrate 101, a non-doped buffer layer 120 (high-purity GaAs layer), a p-type buried layer 108 (p-type GaAs layer), a high-purity non-doped G
aAs layer 121, n-type electron supply layer 122 (n-type Al _x G
a _1-x As (for example, x = 0.5) is sequentially epitaxially grown. 102 is an insulating region for partitioning the active region, 106 is a gate electrode provided in a recess of the n-type electron supply layer 122, and 104d is an n-type drain region (n ⁺
Type GaAs layer) and 104s are n-type source regions (n ⁺ type G
a), 107 d is a drain electrode, 107 s is a source electrode, and 103 is a channel layer (two-dimensional electron gas layer). The p-type buried layer 108 is an n-type source region 104s
And the potential is fixed by parasitic coupling or leakage current. Non-doped GaAs layer 1 on which channel layer is formed
A non-doped buffer layer 120 is interposed between the non-doped buffer layer 120 and the semi-insulating GaAs substrate 101.
At about m, the influence of the deep impurity level in the semi-insulating GaAs substrate cannot be prevented, so a p-type buried layer must be provided.

[0009]

SUMMARY OF THE INVENTION The above-mentioned MESFET
In order to effectively control the frequency dispersion and drain lag of the HJFET and the HJFET, the concentration of the p-type impurity (Be) in the p-type buried layer must be increased so that a neutral region is formed in a part thereof. No. That is, it is necessary to prevent the p-type buried layer below the gate electrode from being depleted when the drain voltage is applied. However, when the p-type impurity concentration increases, the parasitic capacitance between the p-type buried layer and the channel or drain region increases, and there is a problem in that the original operation speed of the device decreases.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a field effect transistor capable of preventing a reduction in operation speed and improving frequency dispersion of drain conductance and drain lag.

[0011]

According to a first field effect transistor of the present invention, a first conductivity type channel layer formed on a compound semiconductor substrate having a semi-insulating compound semiconductor region at least under the first field effect transistor; A second conductivity type semiconductor layer provided between an insulating compound semiconductor region and the first conductivity type channel layer; and a source electrode connected to the first conductivity type channel layer and supplying a first conductivity type carrier. A first conductivity type source region and a drain electrode into which carriers of the first conductivity type flow directly into ohmic contact, and a first conductivity type drain region directly making ohmic contact with the second conductivity type; The semiconductor layer is not provided on at least a part of a portion immediately below the drain region of the first conductivity type.

In this case, the second conductivity type semiconductor layer can be formed by selectively introducing the second conductivity type impurity.

The semiconductor layer of the second conductivity type may be an epitaxial layer, and the epitaxial layer may be converted to the first conductivity type immediately below the drain region of the first conductivity type by introducing impurities of the first conductivity type. can do.

Furthermore, the second conductivity type semiconductor layer may extend below the first conductivity type source region.

According to a second field effect transistor of the present invention, a first conductivity type channel layer formed on a surface portion of a semi-insulating compound semiconductor substrate, a gate electrode which makes a Schottky junction with the first conductivity type channel layer, A lightly doped first conductivity type source region and a lightly doped first conductivity type drain region provided with the gate electrode interposed therebetween; a lightly doped first conductivity type source region connected to the lightly doped first conductivity type source region; A high-concentration first-conductivity-type drain region connected to the low-concentration first-conductivity-type drain region; and a source electrode and a drain that make ohmic contact with the high-concentration first-conductivity-type source region and the high-concentration first-conductivity-type drain region, respectively. An electrode, wherein the high concentration first conductivity type source region, the low concentration first conductivity type source region,
A first conductivity type channel layer and a low-concentration first conductivity type drain region are provided on a surface portion of the second conductivity type semiconductor layer, and the first conductivity type semiconductor layer is provided at least immediately below the high concentration first conductivity type drain region. It is not provided in some.

According to a third field effect transistor of the present invention, a non-doped buffer layer, a second conductivity type semiconductor layer, a non-doped semiconductor layer, and a band gap having a band gap higher than that of the non-doped semiconductor layer are sequentially epitaxially grown on a semi-insulating compound semiconductor substrate. A carrier supply layer including a wide first conductivity type semiconductor layer; a gate electrode in contact with the carrier supply layer; a first conductivity type source region provided on the carrier supply layer with the gate electrode interposed therebetween; A field effect transistor having a drain region of the first conductivity type, and a source electrode and a drain electrode in direct ohmic contact with the source region and the first drain region of the first conductivity type, respectively. Being provided in contact with a region and penetrating through the second conductive type semiconductor layer A.

According to the first or second field effect transistor of the present invention, the second conductive type semiconductor layer is located immediately below the first conductive type drain region or the high-concentration first conductive type drain region where the drain electrode makes direct ohmic contact. Is not provided in at least a part of the device, the parasitic capacitance is reduced. The second conductivity type semiconductor layer provided between the semi-insulating compound semiconductor region and the first conductivity type channel layer is coupled to the first conductivity type source region by parasitic coupling or leakage current.

In the third field effect transistor of the present invention, the first conductive type semiconductor layer in contact with the first conductive type drain region penetrates the second conductive type semiconductor layer, so that the parasitic capacitance is reduced. The first conductivity type semiconductor layer is coupled to the first conductivity type source region by parasitic coupling or leakage current.

[0019]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

In this embodiment, a semi-insulating GaAs substrate 1 is used.
An n-type channel layer 3 formed on the surface of the semiconductor device, a gate electrode 6 Schottky-bonded to the n-type channel layer 3, a low-concentration n-type source region 5s and a low-concentration n-type A drain region 5d; a high-concentration n-type source region 4s connected to the low-concentration n-type source region 5s; a high-concentration n-type drain region 4d connected to the low-concentration n-type drain region 5d; It has a source electrode 7s and a drain region 7d which make ohmic contact with the high-concentration n-type drain region 4d, respectively. The high-concentration n-type source region 4s, the low-concentration n-type source region 5s, the n-type channel layer 3, and the low-concentration The n-type drain region 5d is a p-type semiconductor layer 8
A, and the p-type semiconductor layer 8A is not provided on the bottom surface of the high-concentration n-type drain region 4d.

Next, the manufacturing method of the first embodiment will be described.

As shown in FIG. 2A, semi-insulating GaAs
The insulating region 2 is formed on the surface of the s-substrate 1 by implanting boron ions, for example, to define an active region having a first rectangular surface shape, and then using the photoresist film 9 as a mask to form Be. ^{+ At} 70 keV, 2 × 10 ¹² c
The implantation is performed at m ⁻² to form the buried implantation layer 8a. The first rectangle is occupied by the surface of the buried injection layer 8a.
It is assumed that an opening designed to be divided into two of a rectangle and a remaining third rectangle is provided in the photoresist film 9. Next, as shown in FIG. 2B, using the photoresist film 10 as a mask, Si ions are implanted into the surface of the active region at 30 keV and 8 × 10 ¹² mc ^-2 to form an implanted layer 3.
a is formed. After that, the buried injection layer 8a and the injection layer 3
2a by simultaneously annealing and activating
As shown in (c), a p-type buried layer 8A and an n-type channel layer 3 are formed. Next, a gate electrode 6 that crosses the active region is formed by depositing and patterning a heat-resistant WSi film, a silicon oxide film 11 is deposited on the entire surface, and anisotropic etching is performed. As shown in
An insulating spacer 13 is formed. Next, 10
Injection is performed at 0 keV and 3 × 10 ¹³ cm ⁻² , and the high-concentration injection layer 4 s is self-aligned with the gate electrode 6 and the insulating spacer 13.
a, 4da are formed. Next, the insulating spacer 13 is removed, Si ions are implanted at 50 keV and 1 × 10 ¹³ cm ⁻² , and the low-concentration implanted layer 5sa is self-aligned with the gate electrode 7 as shown in FIG. 5 da is formed. Next, annealing is performed to simultaneously activate the high-concentration injection layers 4sa and 4da and the low-concentration injection layers 5sa and 5da, as shown in FIG. A concentration source region 5s and a low concentration drain region 5d are formed. Next, a source electrode 7s and a drain 7d that make ohmic contact with the high-concentration source region 4s and the high-concentration drain region 4d, respectively, are formed.

The p-type buried layer 8A is in contact with the side surface of the high-concentration drain region 4d, but is not provided on the bottom surface. Therefore, the parasitic capacitance of the high-concentration drain region 4d is smaller than that of the conventional example of FIG. Reduced. Ga of the present embodiment
As MESFET (gate length 1 μm, gate width 100
μm) is 20.6G.
Hz, which is much higher than the measured fT of 15.5 GHz of the same one except that the p-type buried layer 8A is not provided (the measured fT of the conventional example of FIG.
At 2.6 GHz, the fT was smaller than 15.2 GHz, which was the same as the measured fT of the same device except that the p-type buried layer 8 was not provided.)

N-type channel layer 3 and low concentration drain region 5
d, the positional relationship between the low-concentration source region 5s and the high-concentration source region 4s and the p-type buried layer 8A is the same as that of the conventional example shown in FIG. 6, so that the frequency dispersion of the drain conductance and the drain lag are the same as the conventional example. . FIG. 3 is a graph showing the frequency dependence of the drain conductance.
In the example of the embodiment, the solid line is an actual measurement example without a p-type buried layer (in each case, the gate length is 1 μm and the gate width is 1).
0 μm).

When there is no p-type buried layer, while the drain conductance changes with the frequency,
In the present embodiment, almost no fluctuation is observed similarly to the conventional example, and it is understood that the original function of the p-type buried layer is not lost even if the structure of the embodiment is adopted. FIG. 4 (a),
(B) is a graph showing the drain lag of the first embodiment in FIG. 1 and the one without the p-type buried layer, respectively. It is a measurement result of the drain current when the voltage between the gate and the source is set to 0 and the drain voltage is changed from 2 V to 3 V into a square wave with a pulse width of 10 ms. First
In this embodiment, overshoot and undershoot were not observed as in the conventional example. The reason why the drain current is smaller in FIG. 4A is that the threshold becomes shallower by providing the p-type buried layer.

In the present embodiment, the p-type buried layer 8A is
Although it is in contact with the high-concentration drain region 4d, the fT
Can be improved. Further, it may be separated from the high-concentration drain region 4d, but it is preferable to make contact with the entire bottom surface of the n-type channel layer 3. Although an n-type channel layer or the like is provided by directly ion-implanting a semi-insulating GaAs substrate, a high-purity non-doped GaAs layer is epitaxially grown on a semi-insulating GaAs substrate, and an n-type channel layer 3 is formed on the non-doped GaAs layer. Etc. may be formed. In that case, the junction surface between the non-doped GaAs layer and the semi-insulating GaAs substrate may be separated from the p-type buried layer. The n-type channel layer is formed by ion-implanting a non-doped GaAs layer.

Further, as a compound semiconductor, InP may be used in addition to GaAs.

FIG. 5 is a sectional view showing a second embodiment of the present invention.

In this embodiment, a non-doped buffer layer 120 (high-purity GaAs layer), a p-type buried layer 108A (p-type GaAs layer), and a high-purity non-doped G layer are sequentially epitaxially grown on a semi-insulating GaAs substrate 101.
an electron supply layer 122 composed of an n-type Al _x Ga _{1 -x} As layer (for example, x = 0.2) having a wider band gap than the aAs layer 121 and the non-doped GaAs layer 121, and a gate electrode 106 in contact with the electron supply layer 122 And the gate electrode 10
6, the n-type source region 104s and the n-type drain region 104d provided on the electron supply layer 122 with the source electrode 107s and the drain electrode directly in ohmic contact with the n-type source region 104s and the n-type drain region 104d, respectively. Field effect transistor (H
JFET), the n-type semiconductor layer 123 contacts the n-type drain region 104d and the p-type buried layer 10
8A. The n-type semiconductor layer 123 corresponds to the n-type source region 104 in FIG.
Before forming the s and n-type drain regions, the electron supply layer 12 is formed.
2, non-doped GaAs layer 121, p-type buried layer 10
8 is formed by injecting Si ions through hole 8 and annealing. Thereby, the n-type drain region 10
The p-type buried layer below 4d is converted to a part of the n-type semiconductor layer 123. The channel layer is a two-dimensional electron gas layer 103. When the area of the n-type drain region 104d is, for example, a gate length of 0.5 to 1 μm, the gate width × 5 μm, the thickness of the non-doped GaAs layer 121 is, for example, 100 nm, and the thickness of the p-type buried layer 108A (concentration: 1 × 10 18 cm −3). If the thickness is, for example, 20 nm, the opposing area is largely reduced due to the absence of the p-type buried layer below the n-type drain region 104d, and the parasitic capacitance of the drain is reduced. The n-type source region 104s and the channel layer (10
Since the relative positional relationship between 3) and the p-type buried layer is the same as in the conventional example, the frequency dispersion of the drain conductance and the drain lag can be improved as in the conventional example, and the decrease in the current gain cutoff frequency fT can be suppressed.

Although the present embodiment relates to a GaAs-AlGaAs HJFET, it goes without saying that the compound semiconductor material is not limited to this.

In FIG. 5, the non-doped GaAs layer 121 is not provided, and the n-type Alx Ga1-x As layer (122) is not provided.
ME with undoped GaAs layer instead of GaAs
An SFET can be formed. Then, fT can be improved as compared with the case where the n-type semiconductor layer 123 is not provided.

Although the above description has been made by taking an n-channel FET as an example, it will be apparent that the present invention can be applied to a p-channel FET without having to keep a detailed description.

[0033]

As described above, the drain region in ohmic contact with the drain electrode of the field effect transistor having the second conductivity type semiconductor layer provided below the first conductivity type channel layer, and the second conductivity type semiconductor layer By reducing the parasitic capacitance, the operation speed can be prevented from lowering and the frequency dispersion of drain conductance and drain lag can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIGS. 2A to 2E are cross-sectional views illustrating the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a graph showing the frequency dependence of the drain conductance of the first embodiment.

FIG. 4 is a graph showing the drain lag of the first embodiment (FIG. 4A) and a graph showing the drain lag of the case without the p-type buried layer (FIG. 4B).

FIG. 5 is a sectional view showing a second embodiment of the present invention.

FIG. 6 is a sectional view showing a conventional GaAs MESFET.

FIG. 7 is a sectional view showing a conventional HJFET.

[Explanation of symbols]

 Reference Signs List 1,101 semi-insulating GaAs substrate 2,102 insulating region 3 n-type channel layer 3a injection layer 103 two-dimensional electron gas layer 4d high-concentration n-type drain region 4da high-concentration injection layer 104a n-type drain region 4s high-concentration n-type source Region 4sa High-concentration injection layer 5d Low-concentration n-type drain region 5da Low-concentration injection layer 5s Low-concentration n-type source region 5sa Low-concentration injection layer 105s N-type source region 6,106 Gate electrode 7d, 107d Drain electrode 7s, 107s Source electrode 8, 8A, 108, 108A p-type buried layer 9 photoresist film 10 photoresist film 11 silicon oxide film 12 photoresist film 13 insulating spacer 120 non-doped buffer layer 121 non-doped GaAs layer 122 n-type electron supply layer 123 n-type semiconductor layer

Claims (6)

[Claims] 1. A semiconductor device comprising: a first semiconductor layer formed on a compound semiconductor substrate having a semi-insulating compound semiconductor region at least below the first semiconductor substrate;
A conductive type channel layer, a second conductive type semiconductor layer provided between the semi-insulating compound semiconductor region and the first conductive type channel layer, and a first conductive type channel layer,
A first conductivity type source region that makes direct ohmic contact with a source electrode that supplies carriers of first conductivity type, and a first conductivity type drain region that makes direct ohmic contact with a drain electrode into which carriers of the first conductivity type flow. The field effect transistor according to claim 1, wherein the second conductivity type semiconductor layer is not provided at least partially under the first conductivity type drain region. 2. The field effect transistor according to claim 1, wherein the second conductivity type semiconductor layer is formed by selectively introducing a second conductivity type impurity. 3. The semiconductor layer of the second conductivity type is an epitaxial layer, and the epitaxial layer is formed directly below the drain region of the first conductivity type by introducing an impurity of the first conductivity type.
2. The field effect transistor according to claim 1, wherein the field effect transistor is converted to a conductivity type. 4. The field effect transistor according to claim 1, wherein the second conductivity type semiconductor layer extends below the first conductivity type source region. 5. A first conductive type channel layer formed on a surface portion of a semi-insulating compound semiconductor substrate, a gate electrode for Schottky junction with the first conductive type channel layer, and a gate electrode interposed therebetween. A lightly doped first conductivity type source region and a lightly doped first conductivity type drain region;
A high-concentration first conductivity-type source region connected to a conductivity-type source region and a high-concentration first conductivity-type drain region connected to the low-concentration first conductivity-type drain region; A source electrode and a drain electrode, each of which is in ohmic contact with the first conductivity type drain region, wherein the high concentration first conductivity type source region, the low concentration first conductivity type source region, the first conductivity type channel layer, Concentration 1
A conductivity type drain region is provided on a surface portion of a second conductivity type semiconductor layer, and the second conductivity type semiconductor layer is not provided on at least a part immediately below the high-concentration first conductivity type drain region. Characteristic field effect transistor. 6. A non-doped buffer layer, a second conductive type semiconductor layer, a non-doped semiconductor layer, and a first conductive type semiconductor layer having a wider band gap than the non-doped semiconductor layer sequentially grown epitaxially on a semi-insulating compound semiconductor substrate. A carrier supply layer, a gate electrode in contact with the carrier supply layer, a first conductivity type source region provided on the carrier supply layer with the gate electrode interposed therebetween, and a first conductive type source region.
In a field effect transistor having a conductivity type drain region, and a source electrode and a drain electrode which are in direct ohmic contact with the first conductivity type source region and the first conductivity type drain region, respectively, the first conductivity type semiconductor layer is the first conductivity type semiconductor layer. A field effect transistor provided in contact with the conductivity type drain region and penetrating the second conductivity type semiconductor layer.