JPH10270773A - Hall element - Google Patents

Abstract

(57) Abstract: Provided is a Hall element which is hardly affected by contamination on the element surface and has a reduced offset voltage caused by a piezo effect by an insulating film for protecting the element surface. SOLUTION: On the surface of an active layer region 2 surrounded by two current electrode layers 4, 4, and two sensor electrode layers 5, 5, a diffusion layer having a conductivity type opposite to that of the active layer, that is, a current path limiting layer. 6
Is provided, the current flowing on the surface of the active layer region 2 is suppressed, and the current flows through the deep portion of the active layer region 2. This makes the device less susceptible to contamination from the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called horizontal Hall element to which a magnetic field is applied vertically.

[0002]

2. Description of the Related Art FIG. 14 shows the structure of a conventional horizontal Hall element. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG. An n-type Si epitaxial layer is deposited on the p-type Si substrate 1 to form the active layer region 2 of the Hall element, so that a part of the n-type Si epitaxial layer is left and p-type impurities reach the p-type Si substrate 1. The entire surface is diffused to form an element isolation layer 3. In the active layer region 2 of the n-type Hall element, two current electrode layers 4 and 4 and two sensor electrode layers 5 and 5 are formed by n-type diffusion. On these two current electrode layers 4, 4 and the two sensor electrode layers 5, 5,
Two current electrodes 4a, 4a, two sensor electrodes 5a, 5
a is provided respectively. Note that an element isolation electrode may be provided on the element isolation layer 3.

A current flows between the two current electrode layers 4, 4,
By applying a magnetic field vertically to the surface of the Si active layer region 2, the two sensor electrode layers 5,
A Hall voltage is induced between the five.

When aiming at practical use of a Hall element, it is essential to ensure long-term reliability of the element. In the case of a horizontal Hall element, a current flows through the surface of the element as shown in FIG. 14, and therefore, it is necessary to take measures to prevent contamination of the surface of the element. In a conventional semiconductor device, an insulating film (oxide film) is widely used to prevent contamination.

[0005]

Although the Hall element has been widely used as a pressure sensor, even when used as a magnetic field sensor, the stress applied to the element is sensed as an offset voltage.

In the case of a Hall element, when an insulating film is used to prevent contamination of the element surface, when a stress due to a difference in elasticity between the insulating film and Si is applied to the element, this is sensed (piezo effect). there were.

When a horizontal Hall element is put to practical use as a magnetic field sensor, a current flows on the element surface. Therefore, it is necessary to take measures to prevent contamination of the element surface and to minimize the stress applied to the element. The present invention has been made in view of such a point, and has as its object to reduce the influence of contamination on the element surface by moving the current path away from the element surface.

[0008]

According to the Hall element of the present invention, a semiconductor active layer having a conductivity type opposite to that of the substrate is provided on a semiconductor substrate, and the active layer has two or more current terminals and two or more current terminals. One or more sensor terminals are arranged, a main current flows substantially parallel to the surface of the active layer, and a magnetic field is applied in a horizontal Hall element applied in a direction perpendicular to the surface of the active layer. It is characterized in that means for limiting are provided.

As a means for restricting the current path, a diffusion layer having a conductivity type opposite to that of the active layer can be provided in a predetermined range on the surface of the active layer region surrounded by the current terminal and the sensor terminal.

With this configuration, the current flowing on the surface of the active layer is suppressed, and the current path of the current flowing between the current terminals is limited to the deep portion of the active layer. This diffusion layer can be used as it is with only a built-in potential, but in order to more reliably flow a current deep into the active layer, a predetermined potential is applied to the diffusion layer. By applying a potential, a depletion layer extends from the diffusion layer, and the current path is limited to the deep portion of the active layer. Further, a potential gradient may be applied to the inside of the diffusion layer from the outside. For example, it is possible to externally adjust the extension of the depletion layer by providing two or more electrodes in the diffusion layer and adjusting the potential from the outside.

Furthermore, an insulator can be provided on at least a part of the periphery of the diffusion layer or on the active layer side of two or more current terminals in order to surely allow a current to flow deep into the active layer. One or more diffusion layers having the same conductivity type as this diffusion layer and a higher dopant concentration than this diffusion layer may be provided in the region of this diffusion layer. Two or more diffusion layers having a high dopant concentration may be provided in the region of the diffusion layer, and the diffusion layers having a high dopant concentration may be arranged symmetrically with respect to at least one of the current terminal and the sensor terminal.

An insulator may be provided around the diffusion layer having a high dopant concentration. Also, by providing an insulator on the active layer side of two or more current terminals without providing a diffusion layer, a current can flow through the deep portion of the active layer.

Further, if an insulator is provided on the active layer side of two or more current terminals and two or more sensor terminals, it is possible to reduce the influence from the element isolation layer. A configuration may be adopted in which an insulating film is interposed between the substrate and the active layer. That is, it may be manufactured using an SOI (Silicon On Insulator) wafer. By doing so, the depletion layer does not extend at all in the active layer region, and it is possible to avoid variations in various hole characteristics based on the potential difference between the substrate and the active layer region.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following drawings, the same parts or corresponding parts are denoted by the same reference numerals. (First Embodiment) FIGS. 1A and 1B are diagrams showing a configuration of a horizontal Hall element according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. ) Is a sectional view taken along line XX ′ of FIG.

An n-type Si epitaxial layer having a conductivity type opposite to that of the substrate 1 is deposited on a semiconductor substrate such as a p-type Si substrate 1 to form an active layer region 2 of a Hall element. Leave the epitaxial layer and remove the p-type impurity
The entire surface is diffused and formed until the silicon substrate 1 is reached, thereby forming an element isolation layer 3. Two current electrode layers 4 and 4 and two sensor electrode layers 5 and 5 are formed by n-type diffusion in the active region 2 of the n-type Hall element in the element isolation layer 3. A diffusion layer having a conductivity type opposite to that of the active layer, that is, a current path limiting layer 6 is formed on the surface of the active layer region 2 surrounded by the two current electrode layers 4 and 4 and the two sensor electrode layers 5 and 5. Provide.

Two current electrodes 4a, 4a and two sensor electrodes 5a, 5a are provided on the two current electrode layers 4, 4, and the two sensor electrode layers 5, 5, respectively. Although no electrode is provided on the element isolation layer 3 in this embodiment, an element isolation electrode may be provided on the element isolation layer 3.

A current is passed between the two current electrode layers 4, 4,
By applying a magnetic field vertically to the surface of the Si active layer region 2, the two sensor electrode layers 5,
5, a current path limiting layer 6 is provided on the surface of the active layer region 2.
Is suppressed, and the current flows through the deep portion of the active layer region 2 as shown in FIG. This makes it less susceptible to contamination of the element surface.

(Second Embodiment) Next, FIG. 2 shows a configuration of a horizontal Hall element according to a second embodiment of the present invention.
FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view of FIG.
It is X 'sectional drawing.

In the first embodiment, the current path limiting layer 6 is used as it is, with only the built-in potential. However, in the second embodiment, the current path limiting layer 6 is placed on the current path limiting layer 6. An electrode 6a is provided, and a potential is applied to the current path limiting layer 6 through this electrode. In FIG. 2, the current path limiting electrode 6a is provided over the entire surface of the current path limiting layer 6, but the current path limiting electrode 6a may be provided on a part of the surface of the current path limiting layer 6. .
By applying a potential to the current path limiting electrode 6a, the depletion layer 7 extends from the current path limiting layer 6 to a deep portion of the active layer region 2, and the current path can be further limited to a deeper element. By changing the depletion layer 7
Can be varied as needed.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
1 shows a configuration of a horizontal Hall element according to the embodiment. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG.

In the third embodiment, the current path limiting electrode 6a in the second embodiment is
And a potential gradient is externally applied. As shown in the figure, two current path limiting electrodes 6a are provided, and the voltages applied to the two current path limiting electrodes 6a, 6a are alternately changed according to changes in the AC voltage applied to the current electrodes 4a, 4a. The current electrodes 4a, 4a
Irrespective of the potential between a, the thickness of the depletion layer 7 can be kept constant, and stable hole characteristics can be obtained even when used with an AC power supply.

(Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
1 shows a configuration of a horizontal Hall element according to the embodiment. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG.

In this embodiment, in addition to providing the current limiting layer 6, a gate layer 8 of the same conductivity type as the current limiting layer 6 and having a high dopant concentration and one or more gate electrodes 8a provided thereon are provided. It is a thing. FIG. 4 shows one case. The gate layer 8 and the gate electrode 8a allow the offset voltage, that is, the current electrode 4
It is provided for the purpose of removing the voltage generated at the sensor electrodes 5a, 5a even when no magnetic field is applied due to imbalance of a four-terminal bridge composed of the sensor electrodes 5a, 5a.

Although it is more effective to provide a gate electrode 8a on the gate layer 8 and apply a potential to the gate electrode 8a as shown in the figure, the gate electrode 8a is not provided on the gate layer 8 without providing the gate electrode 8a. Alternatively, the gate layer 8 can be used in a state of only the built-in potential. (Note that a technique for removing an offset voltage by a gate layer is disclosed in
No. 30646. (Fifth Embodiment) FIGS. 5 and 6 show a configuration of a horizontal Hall element according to a fifth embodiment of the present invention. In these figures, FIG. 1A is a plan view, and FIG.
It is X 'sectional drawing.

The fifth embodiment is different from the fourth embodiment in that the gate layer 8 and the gate electrode 8a for removing the offset voltage are removed.
Are provided two or more. FIG. 5 shows that four gate layers 8 and a gate electrode 8 a are connected to two current electrodes 4.
a, 4a and two sensor electrodes 5a, 5a. That is, the four gate layers 8 and the gate electrode 8a are symmetrical with respect to the straight line C1 located at the center of the two current electrodes 4a, 4a, and
a, 5a are also symmetrically arranged with respect to the straight line C2 located at the center.

With such a symmetrical arrangement, stable hole characteristics can be obtained even when an AC power supply is used. It is effective to arrange the two or more gate layers 8 and the gate electrodes 8a symmetrically with respect to the two current electrodes 4a, 4a and the two sensor electrodes 5a, 5a. , 4a, and one of the two sensor electrodes 5a, 5a. FIG. 6 shows a case where the electrodes are arranged symmetrically with respect to the two sensor electrodes 5a, 5a, that is, symmetrically with respect to a straight line C2 located at the center of the two sensor electrodes 5a, 5a.

(Sixth Embodiment) In this embodiment, an insulator trench 9 is formed around an offset voltage removing gate layer 8.
Is provided.

FIG. 7 shows a case where an insulator trench 9 is provided around the offset voltage removing gate layer 8 shown in FIG. 5, which is one of the fifth embodiments. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG.

As described above, by providing the insulator trench 9 around the offset voltage removing gate layer 8, the depletion layer 7 extending from the current path limiting layer 6 and the depletion layer 7 extending from the gate layer 8 can be reliably formed. In addition, they can be controlled independently.

Although the insulator trench 9 is provided around the offset voltage removing gate layer 8 of the fourth embodiment, the insulator trench 9 is provided around the gate layer 8 shown in FIG. Can be implemented in the same manner.

(Seventh Embodiment) Next, the current path limiting layer 6
FIGS. 8 and 9 show a seventh embodiment in which an insulator trench 9 is provided on the current path limiting layer 6 side or at least a part of the periphery of the current path limiting layer 6. In these figures, the figure (a) is a plan view, and the figure (b) is XX 'in the figure (a).
It is sectional drawing.

In the embodiment shown in FIG. 8, an insulator trench 9 is formed in the current electrode layer 4 on the current path limiting layer 6 side. As shown in FIG. 8, instead of forming the insulator trench 9 on the current path limiting layer 6 side of the current electrode layer 4, although not shown, the current path limiting at least a part of the periphery of the current path limiting layer 6. The insulator trench 9 may be formed in the layer 6 on the current path limiting layer 6 side. Further, as shown in FIG. 9, an insulator trench 9 may be formed all around the current path limiting layer 6. In any of these cases, the provision of the insulator trench 9 allows the depletion layer 7 from the current path limiting layer 6 to extend to a deeper portion of the active layer region 2 as compared with the case where the insulator trench 9 is not provided. And stable hole characteristics can be obtained.

(Eighth Embodiment) FIG. 10 shows the configuration of a horizontal Hall element according to an eighth embodiment of the present invention. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG.

In this embodiment, an insulator trench 9 is formed in the current electrode layers 4 and 4 on the active layer region 2 side.
Thus, it is possible to easily limit the current path so that the current flows through the deep part of the active layer region 2.

As described above, the method of forming the insulator trench 9 on the active layer region 2 side of the current electrode layers 4 and 4 to limit the current path is the same as in the first to eighth embodiments. It can be applied and used together.

(Ninth Embodiment) This embodiment is an eighth embodiment.
11 is also provided on the side surface of the element, that is, on the side where the sensor electrode layers 5 and 5 are provided.
The configuration is shown in FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG. With such a configuration, the influence from the element isolation layer 3 can be reduced.

In FIG. 10, the insulator trench 9 is interrupted at the positions of the sensor electrodes 5 and 5, but is not interrupted at the positions of the sensor electrodes 5 and 5 and passes through the inside of the sensor electrodes 5 and 5. It may be continuous.

(Tenth Embodiment) This embodiment is different from the ninth embodiment in that the insulator trench 9 is provided also on the side surface of the element, that is, on the side where the sensor electrode layers 5 and 5 are provided. This is a combination of the first to seventh embodiments. FIG. 12 shows a configuration when combined with the case of the sixth embodiment. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG.

(Eleventh Embodiment) In this embodiment, the Hall elements according to the above-described first to tenth embodiments are replaced with SO elements.
It is manufactured using an I (Silicon On Insulator) wafer. That is, an insulating oxide film layer 10 is formed on a substrate 1, and an active layer region 2 and the like of a Hall element are formed thereon. FIG. 13 shows a configuration when the Hall element according to the tenth embodiment is manufactured using an SOI wafer. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line XX ′ of FIG. With such a configuration, it is possible to eliminate the influence of the substrate on the element. That is, since the insulating oxide film layer 10 is provided between the substrate 1 and the active layer region 2, no depletion layer extends in the active layer region 2 and holes and the like based on the potential difference between the substrate 1 and the active layer region 2 are not formed. Characteristic fluctuation can be avoided. (Note that the Hall element is SO
Regarding the technology for manufacturing using an I wafer, see
No. 3,330,646. )

[0040]

As described above, according to the present invention,
Since the current flowing through the surface of the Hall element can be suppressed, it is less susceptible to the effects of contamination on the element surface.In addition, it is not necessary to stack insulating layers for protecting the element surface as many layers as in the past. It is possible to provide a Hall element in which the offset voltage due to the effect is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a Hall element according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a Hall element according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a Hall element according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an example of a Hall element according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of another example of the Hall element according to the fourth embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a Hall element according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a Hall element according to a sixth embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of an example of a Hall element according to a seventh embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of another example of the Hall element according to the seventh embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a Hall element according to an eighth embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a Hall element according to a ninth embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a Hall element according to a tenth embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of a Hall element according to an eleventh embodiment of the present invention.

FIG. 14 is a diagram showing an example of a conventional Hall element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Active layer area 3 ... Element isolation layer 4 ... Current electrode layer 4a ... Current electrode 5 ... Sensor electrode layer 5a ... Sensor electrode 6 ... Current path limiting layer (first diffusion layer) 6a ... Current path limiting Electrode 7: depletion layer 8: gate layer (second diffusion layer) 8a: gate electrode 9: insulator trench 10: insulating oxide film layer

Claims (13)

[Claims] A semiconductor active layer having a conductivity type opposite to that of the substrate is provided on a semiconductor substrate, and two or more current terminals and two or more sensor terminals are arranged on the active layer.
In a horizontal Hall element in which a main current flows substantially parallel to the surface of the active layer and a magnetic field is applied in a direction perpendicular to the surface of the active layer, a means for limiting a current path of the current is provided. Hall element. 2. A semiconductor active layer having a conductivity type opposite to that of the substrate is provided on a semiconductor substrate, and two or more current terminals and two or more sensor terminals are arranged on the active layer.
The main current flows substantially parallel to the surface of the active layer, and the magnetic field is applied to the surface of the active layer region surrounded by the current terminals and the sensor terminals in a horizontal Hall element applied in a direction perpendicular to the surface of the active layer. A Hall element, wherein a first diffusion layer having a conductivity type opposite to that of the active layer is provided in a predetermined range. 3. The Hall element according to claim 2, further comprising: means for applying a predetermined potential to said first diffusion layer. 4. The Hall element according to claim 2, further comprising: means for giving a predetermined potential gradient to said first diffusion layer. 5. A semiconductor active layer having a conductivity type opposite to that of the substrate is provided on a semiconductor substrate, and two or more current terminals and two or more sensor terminals are arranged on the active layer.
The main current flows substantially parallel to the surface of the active layer, and the magnetic field is applied to the surface of the active layer region surrounded by the current terminals and the sensor terminals in a horizontal Hall element applied in a direction perpendicular to the surface of the active layer. A first diffusion layer having a conductivity type opposite to that of the active layer is provided in a predetermined range, and a first diffusion layer having the same conductivity type as that of the first diffusion layer is provided in a region of the first diffusion layer. A Hall element comprising one or more second diffusion layers having a high dopant concentration. 6. The semiconductor device according to claim 1, further comprising at least two second diffusion layers in a region of the first diffusion layer, wherein the second diffusion layers are symmetric with respect to at least one of the current terminal and the sensor terminal. The Hall element according to claim 5, wherein the Hall element is arranged with: 7. The Hall element according to claim 5, further comprising means for applying a predetermined potential to at least one of the first and second diffusion layers. 8. The Hall element according to claim 5, wherein an insulator is provided around the second diffusion layer. 9. The semiconductor device according to claim 2, wherein an insulator is provided on at least a part of the active layer side of the two or more current terminals or around the first diffusion layer. The Hall element as described. 10. The Hall element according to claim 2, further comprising an insulator on an active layer side of said at least two current terminals and at least two sensor terminals. 11. A semiconductor active layer having a conductivity type opposite to that of the substrate is provided on a semiconductor substrate, and two or more current terminals and two or more sensor terminals are arranged on the active layer. In a horizontal Hall element in which a current flows substantially parallel to the active layer surface and a magnetic field is applied in a direction perpendicular to the active layer surface, an insulator is provided on the active layer side of the two or more current terminals. A Hall element characterized by the above-mentioned. 12. A semiconductor active layer having a conductivity type opposite to that of the substrate is provided on a semiconductor substrate, and two or more current terminals and two or more sensor terminals are arranged on the active layer. An electric current flows substantially parallel to the surface of the active layer, and a magnetic field is applied in a direction perpendicular to the surface of the active layer. A Hall element comprising an insulator provided thereon. 13. The Hall element according to claim 1, further comprising an insulating film between the substrate and the active layer.