JPH10271018A - Data converter - Google Patents

Abstract

(57) [Summary] A text output from a text-to-speech synthesizer 1 (12)
The KHz 12-bit linear data D1 is converted by the D / A converter 3 into an analog signal D2. The analog signal D2 is converted by the A / D converter 4 into 8-bit μ-law data D3. [Effect] It is possible to convert voice data having a different control clock frequency or bit number from that for the intra-office switching network and use it as voice data of the intra-office switching network 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data converter used to convert digital audio data and the like obtained by sampling an analog signal into data having different bit numbers and control clock frequencies.

[0002]

2. Description of the Related Art For example, text-to-speech synthesized data for transmitting voice guidance and the like in an intra-office switching network is obtained by sampling an analog signal at a control clock frequency of 8 KHz according to the μ-law rule. This signal encodes the analog level with 8 bits. This signal is called μ-law data, and is widely used in the switching network. On the other hand, various sound sources generated by various computers are not subject to such rules, and for example, those obtained by sampling at a control clock frequency of 12 KHz and encoding them in 12 bits in order to guarantee high sound quality are used.

[0003]

However, the above-mentioned prior art has the following problems to be solved.
Various sound source data generated by a general computer or the like include data that is desired to be used as it is in an intra-office switching network. However, since the data format is different, the data cannot be directly captured. Therefore, a sound source is newly prepared for the intra-office switching network, and a data generation process based on the μ-law rule is performed. Here, μ adapted to the local exchange network by incorporating data with different control clock frequencies and bit numbers
-It is most economical if conversion to the raw data format is possible. The same can be said for not only voice data by the text voice synthesizer for the intra-office switching network but also data obtained by digitally converting various analog signals.

[0004]

The present invention employs the following structure to solve the above problems. <Configuration 1> Digital data having a predetermined number of bits and a control clock frequency obtained by sampling an analog signal is received, the signal is converted, and digital data having a number of bits and a control clock frequency different from the input digital data are received. A digital-to-analog conversion circuit that receives input digital data and converts it into an analog signal, and that receives the output of the digital-to-analog conversion circuit and has a different number of bits and control clock frequency from the input digital data. An analog-to-digital conversion circuit for converting the digital data into digital data and outputting the digital data.

<Configuration 2> Digital data of a predetermined number of bits and a control clock frequency obtained by sampling an analog signal is received, the signal is converted, and the number of bits and the control clock frequency different from the input digital data are converted. A frequency conversion circuit that receives the input digital data and outputs digital data having a control clock frequency different from the input digital data, and receives an output of the frequency conversion circuit, A data conversion device, comprising: a bit data conversion circuit that converts digital data having a different number of bits from input digital data and outputs the digital data.

<Structure 3> In the structure 2, when the digital data is converted into digital data having a lower control clock frequency, of the signals input to the frequency converter, the signal adjacent to the signal to be deleted by the frequency converter is output. A data conversion device which changes a signal to be converted into a complementary value in which a level change near the signal is smooth when viewed as an analog signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below using specific examples. <Example 1> FIG. 1 is a block diagram of a data converter according to Example 1. This device includes a D / A converter 3 that receives an output of the text-to-speech synthesizer 1, an A / D converter 4 that receives an output of the D / A converter 3,
It comprises an intra-office switching network 2 for receiving the output of the A / D converter 4. With this device, the voice data generated by the text-to-speech synthesizer 1 can be sent to the local exchange network 2 and used.

The speech data generated by the text-to-speech synthesizing device 1 is 12-bit width data sampled at a sampling frequency of, for example, 12 KHz. In the figure, it is indicated as 12 KHz 12-bit linear data D1. The D / A converter 3 is a circuit that receives digital data having a 12-bit width and converts the digital data into an analog signal D2. The A / D converter 4 is a circuit that receives an analog signal and outputs digital data having a control clock frequency of 8 KHz and an 8-bit width. This output was indicated as μ-law data D3. That is, the μ-law data output by the A / D converter 4 is supplied to the local exchange 2.

As shown in FIG. 1, the D / A converter 3
Converts the digital data generated by the text-to-speech synthesizer 1 into an analog signal D2. This analog signal can be converted into digital data of any format by the A / D converter 4. Therefore, by generating the μ-law data defined by the μ-law rule by the A / D converter 4, digital data having a control clock frequency and a bit number different from the input data can be obtained.

The text-to-speech synthesizer 1 is a memory that stores, for example, speech data generated by a computer. The same processing can be performed by arranging a device that outputs a signal obtained by digitizing various analog signals instead of the text-to-speech synthesis device 1. Further, the signal converted and output by the A / D converter 4 is in the μ-law format for the intra-office switching network 2, but can be digital data of any format depending on the request of the output side. That is, it may be converted into digital data having an arbitrary control clock frequency with an arbitrary number of bits.

<Effect of Specific Example 1> The circuit having the above configuration described above temporarily outputs the output of the text-to-speech
Since the analog signal is converted by the A converter 3 and converted into digital data of a desired format by the A / D converter 4, input data having a different control clock frequency and bit number can be converted and used as it is.

FIG. 2 is a block diagram of a data converter according to a second embodiment. This device receives a 12 KHz 12-bit linear data D1 output from a text-to-speech synthesizer 1, and performs a frequency conversion. A frequency conversion unit 5 receives data output from the frequency conversion unit 5 and converts the number of bits. A part 6. The output of the bit data converter 6 is accepted by the intra-office switching network 2.

The data output from the text-to-speech synthesizer 1 is the data D1 used in the specific example 1 having a 12-kHz 12-bit width. The frequency converter 5 is a circuit that accepts digital data sampled at a control clock frequency of 12 KHz, samples at a control clock frequency of 8 KHz, and outputs the sampled data. Frequency converter 5
Is 8 KHz 12-bit linear data D4.
The bit data converter 6 is a circuit that converts 12-bit digital data into 8-bit data and outputs it. Thus, the configuration is such that the μ-law data D3 is obtained.

FIG. 3 is a diagram for explaining the operation of the apparatus according to the second embodiment. The timing chart shown in this figure shows input / output signals of the frequency conversion unit 5 shown in FIG. (A) is a control clock of a signal output from the text-to-speech synthesizing apparatus 1, and is indicated as 12 KHz clock K1. (B)
Is data D1 output from the text-to-speech synthesis apparatus 1 and input to the frequency conversion unit 5.

(C) is a control clock K2 of a signal required on the output side, which is shown as an 8 KHz clock in the figure. (D) shows the data D4 output from the frequency conversion unit 5. As shown in the figure, 12-kHz digital data A, B, C, D,... P input in synchronization with the 12-kHz clock K1 are converted to the 8-kHz clock K2.
Is latched and output at the falling edge of. Thereby, as shown in the figure, B, C, E, F, H, I,
... data is obtained. In other words, frequency conversion for validating two out of three data can be performed.

After performing the frequency conversion in this way, it is sent to the bit data conversion unit 6 shown in FIG. The bit data conversion unit 6 receives the 12-bit digital data and
It is converted into digital data corresponding to the bits. This accepts, for example, a 12-bit address signal,
What is necessary is just to comprise with the memory which outputs 8-bit data from the applicable address.

FIG. 4 is a diagram for explaining the operation of the bit data converter. FIG. 7A shows the relationship between the address of 12-bit linear data and the value of the digital data stored at that address expressed in analog level. Digital data is associated with an address from "000" to "FFF" in a manner linearly proportional to the analog level.
Note that "7FF" is a zero level, the upper half is a positive value, and the lower half is an insignificant value. The address is displayed in hexadecimal.

(B) shows μ-law data. This graph was also expressed in exactly the same format as (a). The horizontal axis indicates the address, and the vertical axis indicates the analog level. By comparing (a) and (b) in the figure, it is possible to determine to which address a signal of the same analog level corresponds. According to this correspondence, it is sufficient to design the bit data conversion unit 6 in which 12-bit digital data is used as an address and 8-bit digital data is stored in the corresponding address.

Thus, the apparatus shown in FIG. 2 once samples the output of the text-to-speech synthesizer at 8 KHz,
The digital data is converted into 12-bit digital data, which is further converted into 8-bit digital data.
Get the data.

<Effects of the Second Embodiment> According to the configuration of the second embodiment, similarly to the first embodiment, voice data having different control clock frequencies and bit widths can be taken in and used for the intra-office switching network. In comparison with the device of the first embodiment, since the input data is not converted into an analog signal, and the conversion process is performed as digital data, there is an effect that the device is not affected by noise.

<Embodiment 3> FIG. 5 is a block diagram of a data converter according to Embodiment 3. This device is obtained by adding a data adjustment unit 7 to the device of the specific example 2 shown in FIG. The data adjusting unit 7 is configured to receive the output of the text-to-speech synthesizing device 1, perform adjustment, and input the adjusted result to the frequency conversion unit 5.

FIG. 6 is a diagram for explaining the operation of the data adjustment unit. (A) of the figure shows a clock K1 of 12 KHz which is a control clock frequency of input data. (B) shows 12 KHz data D1 of the input data. (C) shows data D5 obtained by adjusting this data according to a certain rule.
(D) shows the control clock frequency 8 of the signal to be output.
2 shows a KHz clock K2. (E) shows the data D6 of 8 kHz output from the frequency conversion unit 5 of FIG.

The data adjusting section 7 is a circuit which receives data D1 as shown in FIG. 3B and outputs data D5 as shown in FIG. As described above, when data of 12 KHz is latched by an 8 KHz clock and output as 8 KHz data, one out of three data must be deleted. However, when the output signal is viewed as an analog signal, a portion where data is deleted may have a sudden level change. Therefore, when the signal adjacent to the signal to be deleted is viewed as an analog signal, the data adjustment unit 7 calculates a complement value so that a level change in the vicinity of the signal is smooth.

For example, the signals B, C, and C shown in FIG.
When D is directly input to the frequency converter 5 shown in FIG.
The signals B and C are latched and output, but the signal D is deleted. At this time, when viewed as an analog signal, the signal C
As a result, the signal level greatly changes. Therefore, the signal C is converted into an average value of C and D in advance. That is, when signals are input in order of B, C, D, and E, a signal corresponding to C next to the signal D to be deleted is
(C + D) / 2. When the signal adjusted in this way is input to the frequency conversion unit 5, the signal is output in the order of B, (C + D) / 2, E as shown in FIG. As a result, the change in the signal becomes smoother than the change in the signals B, C, and E, and signal deterioration due to frequency conversion can be relieved.

In this embodiment, the signal immediately before the signal to be deleted is adjusted by replacing the signal immediately before the signal to be deleted with the average value of the signal to be deleted and the signal immediately before the signal to be deleted. Can be replaced. In addition, when viewed as an analog signal, any intermediate value may be used instead of an average value as long as the value is a complementary value such that a level change in the vicinity thereof becomes smooth.

<Effect of Embodiment 3> The addition of the data adjustment unit to the device of Embodiment 2 makes the level change of the output signal smooth, and converts the restored wave closer to the output of the text-to-speech synthesizer. Can be obtained as output.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data conversion device according to a specific example 1.

FIG. 2 is a block diagram of a data conversion device according to a specific example 2.

FIG. 3 is a diagram illustrating the operation of a frequency conversion unit.

FIG. 4 is a diagram illustrating the operation of a bit data conversion unit.

FIG. 5 is a block diagram of a data conversion device according to a specific example 3.

FIG. 6 is a diagram illustrating the operation of a data adjustment unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Text-to-speech synthesizer 2 Local exchange network 3 D / A converter 4 A / D converter

Claims (3)

[Claims] A digital signal having a predetermined number of bits and a control clock frequency obtained by sampling an analog signal is converted, the signal is converted, and a digital signal having a number of bits and a control clock frequency different from the input digital data is received. A digital-to-analog conversion circuit for receiving data which is input and converting the digital data into an analog signal; receiving a digital-to-analog conversion circuit output; An analog-to-digital conversion circuit for converting the digital data into frequency digital data and outputting the converted digital data. 2. A method for receiving digital data having a predetermined number of bits and a control clock frequency obtained by sampling an analog signal, converting the signal, converting the digital signal into a digital signal having a bit number and a control clock frequency different from the input digital data. A frequency conversion circuit that receives input digital data and outputs digital data having a control clock frequency different from the input digital data; and receives an output of the frequency conversion circuit and receives input data. A data conversion device comprising: a bit data conversion circuit that converts digital data into digital data having a bit number different from that of digital data and outputs the digital data. 3. The digital signal according to claim 2, wherein, when converting the digital data into digital data having a lower control clock frequency, the signal input to the frequency converter is adjacent to the signal deleted by the frequency converter. A data conversion device characterized in that when a signal is viewed as an analog signal, the signal is changed to a complement value in which a level change near the signal is smooth.