JPH10271396A - Flaw correction pulse generation circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To generate a flaw correction pulse capable of correcting flaws in two consecutive pixels of a CCD by simply adding a simple circuit. A flaw correction pulse for one pixel output from a flaw correction pulse generator 101 is input to a DFF 104, an OR gate 105, and a selector 106. The output of the DFF 104 is input to the OR gate 105 and the OR gate 105
Is input to the selector 106. Selector 102
Selects a two-pixel continuous correction signal for each flaw based on the output of a counter inside the flaw correction pulse generator 101.
The output of the selector 102 is delay-adjusted by the delay circuit 103 so that it has the same phase as the flaw correction pulse output from the flaw correction pulse generator 101, and then input to the selector 106, where the selector 106 corrects for two consecutive pixels. In this case, the output of the OR gate 105 is used.
1 is selected and output to the flaw correction circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a Charge Coupled D
The present invention relates to a flaw correction pulse generation circuit used in a television camera or a video camera using an evice image pickup device (hereinafter abbreviated as CCD).

[0002]

2. Description of the Related Art In a camera using a CCD, C
In order to correct a white flaw of a CD, a flaw correction circuit and a flaw correction pulse generation circuit for generating a pulse for controlling a flaw correction operation are provided. FIG. 2 shows a configuration of a flaw correction pulse generation circuit used in a conventional CCD camera.

In FIG. 2, an output of an n-bit counter 201 for counting the number of flaw correction pulses is supplied to a selector 202.
Is input to the selector 203. The selector 202 selects the value of the horizontal pixel position that defines the horizontal position of each of the n flaws based on the output of the counter 201. Selector 203
Selects the value of the vertical line position defining the vertical line position of each of the n flaws according to the output of the counter 201.
The values of the horizontal pixel position and the vertical line position of the flaw are obtained in advance for each CCD.

[0004] Output signals of the selectors 202 and 203 are input to a horizontal / vertical counter / comparator unit 204. Horizontal and vertical counter, comparator section 204
Clock FCK and horizontal control signal HRST
N and a vertical control signal VRSTN are input, and a flaw correction pulse (pulse for one pixel) is output to a flaw correction circuit (not shown) at timing corresponding to the horizontal and vertical positions of each of the n flaws. Then, based on the flaw correction pulse, the flaw correction circuit corrects the white flaw of the CCD.

[0005]

However, in the above-mentioned conventional configuration, the number of flaw correction pulses is two due to the hardware configuration.
Since it cannot occur continuously in pixels (that is, the counter is incremented by a flaw correction pulse), there is a problem that even if flaw correction is performed, flaws cannot be completely removed from a large flaw.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a flaw correction pulse generating circuit which can perform flaw correction for two consecutive pixels for each flaw with a simple circuit configuration. With the goal.

[0007]

In order to achieve this object, the present invention provides a register for a two-pixel continuous correction signal for each flaw, which is the output of a conventional flaw correction pulse generation circuit.
A D flip-flop for inputting a flaw correction pulse for controlling the flaw correction operation of each flaw, an OR gate circuit for receiving the output of the D flip-flop and the flaw correction pulse, and performing flaw correction for each of the n flaws A selector 1 for selecting a signal for controlling whether to perform two consecutive pixels by the output of an n-bit counter of a conventional flaw correction pulse generation circuit, a delay circuit for delaying the output of the selector 1, and an output of the delay circuit A selector 2 is provided for selecting and outputting the output of the OR gate circuit and the flaw correction pulse. Then, a two-pixel continuous correction signal is set so that a flaw correction pulse is continuously generated for two pixels for a large flaw, and a flaw correction pulse for one pixel is generated for other flaws as before.
Set the pixel continuity correction signal.

As a result, a flaw correction pulse generation circuit for a flaw correction circuit capable of correcting flaws for two consecutive pixels is obtained.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a D flip-flop to which a pulse signal for controlling the operation of CCD flaw correction is input, an OR gate circuit to which the output of the D flip-flop and the pulse signal are input, and n A first selector for selecting a signal for controlling whether or not to perform flaw correction for two consecutive pixels for each flaw, a delay circuit for delaying an output of the first selector, and an output of the delay circuit , A second selector for selecting and outputting the output of the OR gate circuit or the pulse signal, thereby generating a flaw correction pulse for two consecutive pixels for a large flaw, In this case, the flaw correction pulse is generated for one pixel as in the prior art, so that the performance of flaw correction can be improved.

Hereinafter, a flaw correction pulse generation circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a flaw correction pulse generation circuit according to an embodiment of the present invention. In FIG. 1, a clock FCK, a horizontal control signal HRST
N and the vertical control signal VRSTN are input to the flaw correction pulse generator 101. The flaw correction pulse generation unit 101 shown in FIG. 1 is the flaw correction pulse generation circuit shown in FIG. 2 described in the related art, and applies a flaw correction pulse having a pulse width of 1 clock to n flaw positions. Output at the corresponding timing.

The flaw correction pulse output from the flaw correction pulse generator 101 is input to a D flip-flop (DFF) 104. The output of the D flip-flop 104 is input to the OR gate circuit 105 together with the flaw correction pulse output from the flaw correction pulse generator 101. The output of the OR gate circuit 105 is a flaw correction pulse having a pulse width of 2 clocks,
This corresponds to a flaw correction pulse when flaw correction is performed for two consecutive pixels.

On the other hand, the selector 102 has an n-bit counter (the n-bit counter 2 shown in FIG. 2) for counting the number of flaw correction pulses inside the flaw correction pulse generator 101.
01), a two-pixel continuous correction signal for each of the flaws at n locations (n is a natural number) is selected. Selector 102
Is input to the delay circuit 103, delay-adjusted so as to have the same phase as the flaw correction pulse which is the output signal of the flaw correction pulse generator 101, and then input to the selector 106. The selector 106 uses the OR gate circuit 1 when correcting two consecutive pixels based on the output of the delay circuit 103.
If the output of the pixel 05 is not corrected for two consecutive pixels (one-pixel correction), the output of the flaw correction pulse generator 101 is selected for each flaw and output to a flaw correction circuit (not shown).

As described above, according to the present embodiment, by adopting such a circuit configuration, it is possible to arbitrarily perform two-pixel continuous flaw correction for each flaw by simply adding a simple circuit. .

The two-pixel continuous correction signal input to the selector 102 is predetermined and may be generated by providing a register or the like. The two-pixel continuous correction signal is
Since it is for controlling the selector 106, each signal may be 1 bit.

Further, in the present embodiment, the case of correcting flaws of two pixels in succession has been described. However, another D flip-flop is added after the D flip-flop 104, and the output of the flaw correction pulse generation unit 101 and The three logical sums with the outputs of the two D flip-flops are taken and the two-pixel continuous correction signal input to the selector 102 is extended by two bits as a three-pixel continuous flaw correction signal to select the state of one to three bits As long as the signal is possible, continuous correction of three pixels is also possible.
Further, continuous damage correction of three or more pixels can be performed by similar circuit expansion.

[0017]

As described above, according to the present invention, the conventional 1
It is possible to arbitrarily perform two-pixel continuous flaw correction for each flaw by simply adding a simple circuit to the flaw correction pulse generation circuit corresponding to the flaw of a pixel, thereby improving the performance of flaw correction. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a flaw correction pulse generation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional flaw correction pulse generation circuit.

[Explanation of symbols]

 101 flaw correction pulse generator 102, 106 selector 103 delay circuit 104 D flip-flop 105 OR gate circuit 201 n-bit counter 202, 203 selector 204 horizontal, vertical counter, comparator

Claims (1)

[Claims] 1. A D flip-flop to which a pulse signal for controlling a CCD flaw correction operation is input, an OR gate circuit to which an output of the D flip-flop and the pulse signal are input, and n places (n is a natural number) A first selector for selecting a signal for controlling whether or not to perform flaw correction for two consecutive pixels for each flaw, a delay circuit for delaying an output of the first selector, and an output of the delay circuit. And a second selector for selecting and outputting the output of the OR gate circuit or the pulse signal and outputting the pulse signal.