JPH10271521A - Digital convergence circuit - Google Patents

Abstract

(57) [Summary] A digital convergence circuit that does not require adjustment of digital convergence for each signal and that does not cause convergence deviation even if the size or the number of lines of a display image is variable. When a vertical synchronizing signal is supplied to a switch, a switch is set to a latch on a first line, and an adder adds output signals from latch circuits and L _START + L. The value of _INT (the number of the first scanning line of the input signal in the reference format) is output to the latch circuits 3 and 4 and held. From the second line, the switch 6 is set to the latch 3 side. Thereafter, the value of L _INT is added to the latch circuit 3 for each line, and the operation of latching by the latch circuit 4 is repeated. The number of lines L _c from the latch circuit 4 that represents what knots of standard format scan line L of the input signal RAM8
And outputs digital convergence data to the convergence circuit in accordance with this.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a projection display device using a CRT, and more particularly to a digital convergence circuit in a projection display device.

[0002]

2. Description of the Related Art A conventional general vertical deflection circuit for a display is described in page 31 of Hitachi Consumer IC Data Book, Image IC (issued in March, 1990; second edition). The sawtooth signal waveform generated by the CR oscillator in synchronization with the vertical frequency is generated, the current is amplified by a vertical output amplifier using the signal waveform as a reference, and a sawtooth current flows through the deflection yoke.

Meanwhile, in a projection type CRT display device, as shown in FIG.
The RT 21 is independent, and the images on the phosphor screens of the three CRTs 21 are screened by the lens 22 on the screen 23.
This is a method of enlarging and projecting. Therefore, even if the same image is displayed on the fluorescent screen of each CRT 21, the image on the screen is shifted as shown in FIG.

Therefore, in a CRT projection type display device, a convergence correction circuit is provided to correct a color shift and adjust so as to overlap on a screen.

A convergence circuit is generally a digital convergence correction circuit which provides grid-like coordinates as shown in FIG. 6, adjusts color shifts on the coordinates, and interpolates other points based on grid-like coordinate data. is there.

[0006]

The multi-scan type projection display is designed to be able to display various signals having different synchronization frequencies, but each signal has digital convergence data for the following reasons. There is a need.

(1) When the horizontal frequency changes, non-linear distortion of the deflection circuit occurs, and convergence deviation occurs at a different horizontal frequency even if the image is displayed at the same horizontal size.

(2) When the size of the display image is changed, the position of the coordinates at the original size is different from the position of the coordinates at the new size, so that proper digital convergence correction cannot be performed at the new size.

For this reason, it is necessary to perform digital convergence adjustment by the number of signals, and there has been a problem that the number of adjustment steps is enormous.

In order to eliminate the need to perform the digital convergence adjustment for each signal, the following (1)
The problems (1) and (2) need to be solved, but the problem (1) can be solved by connecting a scan converter in front of the projector and keeping the horizontal scanning frequency constant. Further, since the output width of the video in the horizontal direction can be freely set by the scan converter, it is not necessary to change the horizontal size.

In the vertical direction, even if a scan converter is used, the number of scanning lines cannot be changed, so that the size must be changed by a vertical deflection circuit as in the prior art.

However, when the vertical size is changed, (2)
Therefore, it is necessary to develop digital convergence data according to the size. However, even if this development is performed, the conventional circuit cannot perform accurate convergence correction for the following reasons.

That is, as shown in FIG. 7, when the digital convergence adjustment is performed in the state of the largest size and the size is reduced, the position of the scanning line when the size of the digital convergence data of the large size is reduced is reduced. It is conceivable that the convergence deviation is corrected in association with. However, in reality, when the size is changed due to the fact that the deflection circuit is not linear, the shape of the current waveform is shifted as shown in FIG. This current waveform shift is shown in FIG.
As shown in FIG. In FIG. 8, the vertical axis indicates the current value, and the horizontal axis indicates the display screen size.

As described above, in the conventional convergence circuit, since the position of the coordinates is shifted, even if the convergence data is replaced according to the size when the size is changed, it is impossible to correct the convergence correctly as a result. A problem arises that it is not possible.

An object of the present invention is to eliminate the need to adjust digital convergence for each signal in a horizontal deflection single scan and vertical deflection multiscan projection type display apparatus, and to make the size and number of lines of a display image variable. Another object of the present invention is to realize a digital convergence circuit in which convergence deviation does not occur.

[0016]

[Means for Solving the Problems]

(1) The present invention is configured as follows to achieve the above object. That is, in the digital convergence circuit, a series of data for each horizontal scanning line representing a sawtooth waveform of a vertical cycle is stored, and memory means for repeating reading of the data for each vertical scanning line, and data read from this memory means A D / A converter that converts a series of data into an analog signal and generates an analog sawtooth waveform of a vertical scanning period, and outputs a vertical deflection yoke using the output waveform of the D / A converter as a reference signal. Address generating circuit for generating an address corresponding to the position of a scanning line corresponding to each horizontal scanning line of the circuit; and memory means for storing digital convergence correction data for each address corresponding to the position of the scanning line And convergence compensation with the digital convergence data assigned by the address generation circuit. Configured to the.

Since the vertical deflection output circuit can freely generate a vertical deflection waveform, it is possible to generate a vertical deflection sawtooth waveform that does not cause a shift in the current waveform even if the size is changed.

Further, a reference format is provided, digital convergence adjustment is performed only in the reference format, and convergence correction according to the number of lines and the size of each input signal is performed by scanning digital data of scanning lines at the same position of data in the reference format. This can be done by using convergence data.

(2) In a projection type image display device having a display screen on which images displayed on a plurality of cathode ray tubes are projected, a video signal generating means and a video signal generating means for generating a video signal from the video signal generating means are provided. A memory means for storing a series of data for each horizontal scanning line representing a sawtooth waveform having a vertical period, and repeating the reading of the data for each vertical scanning line; and converting the series of data read from this memory means to analog. A vertical deflection output circuit for driving a vertical deflection yoke using an output waveform of the D / A converter as a reference signal; and a vertical deflection output circuit for driving the vertical deflection yoke using the output waveform of the D / A converter as a reference signal. An address generating circuit for generating an address corresponding to the position of the scanning line corresponding to each horizontal scanning line of the output circuit; and an address corresponding to the position of the scanning line. A memory means for storing digital convergence correction data for each digital convergence data, and a digital convergence circuit for performing convergence correction with the digital convergence data allocated by the address generation circuit. A signal is supplied, vertical deflection is performed by the vertical deflection output circuit, convergence is corrected by the convergence circuit, and an image based on the video signal is displayed by the plurality of cathode ray tubes, and an image displayed on the plurality of cathode ray tubes is displayed. Is projected on the display screen.

If the above digital convergence circuit is applied to a projection type image display device, a projection type image display device capable of displaying a high quality image without a convergence deviation even if the size of the display image or the number of lines is made variable. can do.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital convergence circuit according to an embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a main part of a digital convergence circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a vertical deflection circuit used in the present invention.

First, the configuration of the vertical deflection circuit shown in FIG. 2 will be described. In FIG. 2, reference numeral 11 denotes a CPU (central processing unit),
12 is a memory means (S-RAM for generating sawtooth waveform), 1
3 is a D / A (digital / analog) converter (D / A converter for sawtooth waveform output), 14 is a vertical output amplifier, 15 is a vertical deflection coil, 16 is a current feedback resistor, 17
Is a negative feedback impedance, and 18 is a subtractor.

The memory 12 stores data for each horizontal line representing a vertical deflection waveform having a sawtooth waveform calculated by the CPU 11, and each time a horizontal drive pulse HD of a horizontal scanning cycle is supplied, Each time a sequential address is designated, data of a sequential horizontal line is read, and each time a vertical drive pulse VD of a vertical scanning cycle is supplied, the data is reset to a head address.

That is, when the vertical drive pulse VD is supplied, the head address (data of the first horizontal line) is read from the memory 12, and every time the horizontal drive pulse HD is supplied, the second horizontal line is read. Data of each horizontal line is read in order from the data.

The data read from the memory 12 is supplied to a D / A converter 13, where the data is converted from a digital signal to an analog signal. The signal converted into the analog signal is amplified by a vertical output amplifier via a subtractor 18 and is then amplified by a vertical deflection coil 15 and a current feedback resistor 1.
6. An output signal from the vertical deflection coil 15 is supplied to a subtractor 18 via a negative feedback impedance 17.
, And is subjected to a subtraction process from the output signal from the D / A converter 13 to be supplied to a vertical output amplifier.

Here, the equation of the vertical sawtooth waveform in the reference format stored in the memory 12 is shown in the following equation (1). V _SAWR (L) = V _A × (L−V _LR / 2) + V _LIN × (L−V _LR / 2) ² + V _S × (L−V _LR / 2) ³ −−− (1) where L scanning line number, V _SAWR (L) is the position of the L-th scanning line (digital data), V _a is the amplitude (reference amplitude), V _LIN is the linearity component, V _S is the S-component, V _LR
Is the number of scanning lines in the reference format.

The general formula of the vertical sawtooth waveform based on the above formula (1) is expressed by the following formula (2). V _SAW (L) = V _A × P _L (L−V _L / 2) + V _LIN × {P _L (L−V _L / 2)} ² + V _S × {P _L (L−V _L / 2)} ³ −−− (2) where P _L is V _SIZE × V _LR / V _L , where V _SIZE is the ratio of the size (it is not completely the size ratio because there is a linearity S-shaped component), and _VL is the input. This is the number of signal scanning lines.

If a vertical sawtooth waveform is generated based on the above equation (2), as shown in FIG. 3, even if the display image size is changed from a large size (reference format) to a small size, the sawtooth shape is changed. The profile itself of the sawtooth waveform does not change, only the range in which the waveform is used changes. Similarly, changing the number of lines does not change the profile of the sawtooth waveform.

The digital convergence data after the convergence adjustment is provided in association with the position of each scanning line of the reference signal.

When various signals are input, the number and size of lines differ depending on the signals. However, since the vertical sawtooth waveform has a constant profile as described above, the same digiton data at the position of the scanning line may be assigned to the scanning line at the same position as the scanning line of the reference signal. Will be.

For this purpose, it is sufficient to calculate which scanning line of the reference signal corresponds to the scanning line of the input signal. This can be simply given by the following equation (3). L _C = L _START + L × L _INT (3) where L _C indicates the number of the scanning line L of the input signal in the standard format. L _START indicates the number of the scanning line in the reference format where the position of the first scanning line of the input signal is. L _INT indicates V _LR / V _L.

Lc in the above equation (3) is the scanning line L of the input signal.
At the position (address) of the scanning line of the reference signal.

Using the above equation, a digital convergence circuit according to an embodiment of the present invention can be embodied. Next, a correction circuit of a digital convergence circuit according to an embodiment of the present invention will be described with reference to FIG.

In FIG. 1, the latch circuit 2 determines how many (L _INT ) to advance for each scanning line by the input signal.
It is set by it (upper 10 bits: integer part, lower 10 bits: decimal part). The latch circuit 1 calculates whether the first scan line in the input signal corresponds to what line of the standard format, and subtracting the value from the value L _INT (L _START), 20bi
It is set by t (upper 10 bits: integer part, lower 10 bits: decimal part).

The output signal of the latch circuit 1 is supplied to one input terminal of the switch 6. When the switch 6 is set to the latch circuit 1 side, the latch circuit 1
Is added by the adder 5 to the output signal of the latch circuit 2 via the switch 6. The output signal of the adder 5 is supplied to the latch circuits 3 and 4.

The output signal of the latch circuit 3 is supplied to the other input terminal of the switch 6. When the switch 6 is set on the latch circuit 3 side, the latch circuit 3
Is added by the adder 5 to the output signal of the latch circuit 2 via the switch 6.

The output signal from the latch circuit 4 is R
AM8. The RAM 8 stores digital convergence data calculated by the CPU 7.

In the above configuration, when the vertical synchronizing signal VD is supplied to the switch 6, the switch 6 is set to the latch 1 side in the first line. Then, the adder 5 adds the output signal of the latch circuit 1 and the output signal of the latch circuit 2, and calculates the value of L _START + L _INT , that is, the number of lines of the input signal corresponding to the first scanning line in the reference format. It outputs to the latch circuits 3 and 4 whether it corresponds to the eye.

The output value is held in the latch circuits 3 and 4. The latch circuit 4 has the upper 10bi
t, i.e., latches only the integer part, which is:
The number of lines L _c becomes the scanning line L represents how many eyes of the standard format of the input signal, and outputs this as the address of the RAM 8.

From the second scanning line, the switch 6 is connected to the latch 3
Set to side. Thereafter, for each line, the value of L _INT (the value of the latch circuit 2) is added to the latch circuit 3, and the operation of being latched by the latch circuits 3 and 4 again is repeated.

Then, from the latch circuit 4, the number of lines L representing the number of scanning lines L of the input signal in the reference format
_c is supplied to the RAM 8 as an address. RAM8
Outputs the stored digital convergence data to a convergence circuit (not shown) according to the number of lines L _C (address) supplied from the latch circuit 4.

[0042] If the digital convergence circuit configured as described above, since it is possible to exactly match the data of the convergence correction in the position (address) and the standard format of the vertical scanning lines of the input signal, the number of lines L _c
, The digital convergence data may be sequentially output from the digital convergence data storage RAM 8 to the convergence circuit.

The image signal convergence-adjusted by the convergence circuit is projected on the screen 23 from the CRT via the lens 22.

As described above, according to the embodiment of the present invention, even when the number of lines and the size change, the correlation between the reference format and the scanning lines of the formats of the respective signals is obtained, and the scanning lines of the input signal are converted to the scanning format of the reference format. Since it is possible to automatically calculate which scanning line of a signal corresponds with a simple configuration, there is no need to adjust digital convergence for each signal, and the size of the displayed image and the number of lines can be changed. Also, it is possible to realize a digital convergence circuit in which convergence deviation does not occur.

A plurality of cathode ray tubes which are supplied with a video signal from the video signal generating means, are vertically deflected by a vertical deflection output circuit, are subjected to convergence correction by a convergence circuit, and display an image based on the video signal, are provided. If the digital convergence circuit is applied to a projection type image display device including a display screen on which an image displayed on a cathode ray tube is projected, even if the size or the number of lines of the display image is variable, no convergence deviation occurs. A projection-type image display device (projection-type CRT display device) that can display high-quality video can be realized.

The latch circuit 1 and the latch circuit 2 may be configured to receive the signals L _START and L _INT from the CPU 7 or may be configured to supply the signals from the CPU 11. CPs other than the CPUs 7 and 11
It is also possible to supply by U.

[0047]

Since the present invention is constructed as described above, the following effects can be obtained. Horizontal single scan,
In a vertical multi-scan display, even if the number of lines and the size change, the correlation between the reference format and the scanning lines of each signal format is performed, and the scanning line of the input signal corresponds to which scanning line of the reference format signal.
Since calculations can be performed automatically with a simple configuration, there is no need to adjust digital convergence for each signal.
In addition, a digital convergence circuit in which convergence does not occur even if the size of the display image and the number of lines are variable can be realized.

A plurality of cathode ray tubes which are supplied with a video signal from a video signal generating means, are vertically deflected by a vertical deflection output circuit, are subjected to convergence correction by a convergence circuit, and display an image based on the video signal. If the digital convergence circuit is applied to a projection type image display device including a display screen on which an image displayed on a cathode ray tube is projected, even if the size or the number of lines of the display image is variable, no convergence deviation occurs. A projection-type image display device capable of displaying a high-quality image can be realized.

[Brief description of the drawings]

FIG. 1 is a main block diagram of a digital convergence circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a vertical deflection circuit used in the present invention.

FIG. 3 is a vertical deflection waveform diagram according to the present invention.

FIG. 4 is a diagram illustrating the principle of a projection display.

FIG. 5 is an explanatory diagram of projection distortion of the projection display.

FIG. 6 is a diagram of grid points for digital convergence adjustment.

FIG. 7 is a correlation diagram of scanning line positions when the size is changed.

FIG. 8 is a conceptual diagram of distortion when a size caused by a non-linear component of a vertical deflection circuit is varied.

FIG. 9 is a conceptual diagram showing a state of deviation of digital convergence coordinates due to deflection distortion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Latch circuit 1 2 Latch circuit 2 3 Latch circuit 3 4 Latch circuit 4 5 Adder 6 Switch 7 Convergence control CPU 8 Digital convergence data storage RAM 11 Display control CPU 12 S-RAM for sawtooth waveform generation 13 Sawtooth waveform output D / A converter 14 Vertical output amplifier circuit 15 Vertical deflection yoke 16 Current feedback resistor 17 Negative feedback impedance 18 Subtractor 21 CRT 22 Lens 23 Screen

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Sachi Ikeda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Visual Information Media Division, Hitachi, Ltd. (72) Inventor Hiroyuki Shinji Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Inside Hitachi Image Information System, Ltd.

Claims (2)

[Claims] 1. A memory means for storing a series of data for each horizontal scanning line representing a sawtooth waveform having a vertical period, and for repeating reading of the data for each vertical scanning line, and a series of data read from the memory means. A D / A converter for converting data into an analog signal and generating an analog sawtooth waveform having a vertical scanning period; and a vertical deflection output circuit for driving a vertical deflection yoke using the output waveform of the D / A converter as a reference signal. An address generating circuit for generating an address corresponding to the position of a scanning line corresponding to each horizontal scanning line, and memory means for storing digital convergence correction data for each address corresponding to the position of the scanning line; With
A digital convergence circuit for performing convergence correction using digital convergence data assigned by the address generation circuit. 2. A projection type image display device having a display screen on which images displayed on a plurality of cathode ray tubes are projected, wherein: a video signal generating means; and a vertical period of a video signal generated from the video signal generating means. A series of data for each horizontal scanning line representing a saw-tooth waveform of the same, and a memory means for repeating reading of the data for each vertical scanning line; and a series of data read from this memory means, A vertical deflection output circuit for driving a vertical deflection yoke using the output waveform of the D / A converter as a reference signal; An address generating circuit that generates an address corresponding to the position of the scanning line corresponding to the coordinates of each horizontal scanning line, and an address corresponding to the position of the scanning line, Memory means for storing digital convergence correction data, and a digital convergence circuit for performing convergence correction with the digital convergence data assigned by the address generation circuit, wherein a video signal from the video signal generation means is supplied. The vertical deflection output circuit vertically deflects, the convergence is corrected by the convergence circuit, an image based on the image signal is displayed by the plurality of cathode ray tubes, and the image displayed on the plurality of cathode ray tubes is displayed on the display screen. A projection type image display device characterized in that the image is projected on a screen.