JPH1027156A - Bus arbiter controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use a system bus with high use efficiency by weighting a bus acquisition request according to its generation time and the priority level of a bus master, and allowing the bus master to acquire the bus at the weighted bus acquisition request. SOLUTION: An AND bus inputs system bus acquisition request signals a2-a4 from respective bus masters and a time signal a1 indicating the time when the requests are generated, and outputs acquisition request signals a6-a8 generated by adding the generation time information to the system bus acquisition request signals a2-a4 to a maximum decision encoder 13 and a pulse transmitter 11. The maximum decision encoder 13 outputs a system bus acquisition enabling signal a17 onto the system bus with system bus acquisition request signals a6-a8 from an AND 10 and state signals a12-a14 from a counter 12 in response to the system bus acquisition request signal a4 of currently top priority.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus arbiter control device, and more particularly to a bus arbiter control device of a bus arbitration control system having a hierarchical bus structure in an information transfer system of an information processing device.

[0002]

2. Description of the Related Art As shown in FIG. 1, for example, a system bus in a current information processing apparatus has a hierarchical bus structure. That is, a plurality of bus masters 3, 4, and 5 share a single bus 9.

A bus master is a device having a bus control function, and bus slaves 6 and 7 are bus masters 3, 4, 5
Subordinate to. The bus 8 is connected to a central processing unit 1, a main memory 2, and a bus bridge 3 as a bus arbiter that can be a bus master.

[0004] Therefore, in order to use a certain bus, a bus arbiter that has arbitrated the bus request and obtained the right to use the bus uses the bus. The first of these bus arbitrations is a fixed priority in which the priority of the request source is fixed, the second is a round robin in which the priority of the request source is rotated and the buses are equally allocated, and the third is a bus arbitration in the request order of the request source. Are assigned in the order of request time series.

However, the first bus arbitration cannot cope with the changing priority, and the second bus arbitration is equal, but is not immediately assigned to a high priority bus master. In the third bus arbitration, a high-priority bus master should be allocated even if the waiting time is small, but this is not possible.

FIG. 4 is a block diagram of a conventional common bus arbitration control system disclosed in Japanese Patent Application Laid-Open No. 3-263158. In FIG. 4, a common bus 31 for transferring information and devices having at least two or more bus control functions, for example, a central processing unit 34, an input / output control unit 35,
In an information processing device including a bus master such as 36 and a bus arbitration control device 33, at least one or more timers 43, 44,
45, and a storage unit for storing an initial value of the timer. The storage unit stores the allowable bus acquisition wait time for each bus master. The bus arbitration control unit 33 is notified of a bus use request from the bus master. When the countdown of the bus master timers 43, 44, and 45 is started and the bus becomes available, when there is a bus use request from at least two or more bus masters, the timer of each bus master timer is A bus arbitration control function that compares the values, permits the bus master with the smallest value to use the bus, suspends the countdown of the timer for the bus master permitted to use the bus, and returns the count value to the initial value By having the device 33, the bus use priority of each bus master automatically increases as the bus acquisition waiting time of each bus master increases. And to allow the bus arbitration control suitable for each bus master.

However, in such a configuration, the bus master once connected to the bus 31 may be positioned at the lowest or the lowest priority, and when a request is made again, even if the priority is higher, Immediately bus 3
1 is not controlled by the bus arbitration control device 33.

[0009]

SUMMARY OF THE INVENTION Accordingly, the present invention compensates for the drawbacks of the bus arbitration system described above, and weights at least the operation acquisition time of a bus acquisition request of a bus master configured on a system bus. The purpose is to improve the use efficiency of the system bus.

[0010]

In order to solve the above-mentioned problems, a bus arbiter control device according to the present invention provides a bus acquisition request from a plurality of bus masters, the time when the bus acquisition request is generated, and the priority of the bus master. The bus master is configured to perform weighting based on the rank, and to grant bus acquisition permission to one of the bus masters based on the weighted bus acquisition request.

A bus arbiter control device according to another aspect of the present invention receives a system bus acquisition request signal including priority information and an acquisition request signal including a time signal indicating a time at which the request occurred, and receives a request signal from each bus master. A status signal for each bus master indicating a priority order status is output. Based on the system bus acquisition request signal and the status signal, a system bus acquisition permission is given to the highest priority system bus acquisition request signal at that time. It is configured to output a signal.

[0012]

1 and 2, which show an embodiment of the present invention, a bus arbiter control device 15 includes an AND (AND) 10 for adding generation time information to a transfer request signal from each master. And a pulse transmitter 11 that receives information from the priority setting register and outputs a master transfer request signal to the counter 12.
12 having a function of inputting a master request signal from the controller and changing the priority state of each master by the counter.
And the request signal output from each master counter, determine the priority of the request signal at that time,
A maximum value determination encoder 13 that outputs a transfer permission signal from a request signal having a high priority.

Referring to the block diagram of FIG. 2, which illustrates the bus arbiter control device of FIG. 1 in detail. In FIG. 2, AN
D10 receives a signal a1 indicating the time at which the request occurred, and system bus transfer request signals a2, a3, and a4 from the bus master connected to the hierarchical bus 9, and sends the signal to the maximum value determination encoder 13 and the pulse transmitter 11. Then, the bus transfer request generation time information (how long) has been added to the system bus transfer request, and a bus acquisition request signal a6,
a7, a8, and transfer.

The pulse generator 11 receives the priority information of each bus master from the priority setting register 14 and sends out trigger signals a9 to a11. The counter 12 receives the trigger signals a9, a10, and a11 from the pulse transmitter 11, respectively, and sends state signals a12, a1 indicating the priority state of each bus master to the maximum value determination encoder 13.
3. Send out a14. In the maximum value determination encoder 13, based on the received bus acquisition request signals a6, a7, a8 and the status signals a12, a13, a14, the system bus acquisition permission signals a15, a16,
a17 is output.

FIG. 3 is a characteristic diagram showing the priority order of the system bus transfer requests in FIG. In FIG. 3, the priority of the system bus transfer request a2 at the request time 0 is the lowest, but the priority suddenly increases as time passes. The priority at the time of the request for the system bus transfer request a4 does not change over time. System bus transfer request a3
Is located in the middle.

Next, the operation will be described. At time point a shown in FIG. 3, system bus acquisition requests a2, a3, and a are simultaneously sent from three bus masters on system bus 9.
4 will be described as an example.

In the AND 10 receiving the system bus acquisition request signals a2, a3, a4 from the bus masters 3, 4, 5 in FIG. 1, the system bus acquisition request signals a2, a3, a4 and a time signal a1 indicating the time at which the request was generated, and the respective acquisition request signals a6, a7,... obtained by adding generation time information to the system bus acquisition request signals a2, a3, a4.
a8 is the maximum value determination encoder 13 and the pulse transmitter 11
Output to

In the pulse transmitter 11 which has received the acquisition request signals a6, a7 and a8, the priority setting register 14
Each of the bus masters 3 for which the priority order information is initially set,
4 and 5 receive the signal a5 of the priority information at the time when the bus acquisition request signals a2, a3 and a4 are generated, and trigger signals a9, a10 and a
11 is output. The counter 12 that has received the trigger signals a9, a10, and a11 outputs the individual bus master state signals a12, a14, and a15 indicating the priority state of each bus master at that time to the maximum value determination encoder 13, respectively. .

The maximum value judging encoder 13 has an AND 10
Bus request signals a6, a7, a8 from
Based on the status signals a12, a13, and a14 from the counter 12, the system bus acquisition permission signal a17 is output on the system bus 9 in response to the system bus acquisition request signal a4 having the highest priority at that time.

At this time, the system bus acquisition request signals a2, a of the bus masters 3, 4 to which no bus acquisition permission has been given.
3 respectively, the system bus use permission signal a15
In a and 16, the system bus acquisition permission signal a 16 for the system bus acquisition request signal a 3 of the bus master 4 having the next highest priority is output on the subsystem bus 9 at the same time when the service of the previous bus master 5 ends. Then, the system bus acquisition permission signal a15 of the bus master 3 is output on the system bus 9.

Next, the operation for the system bus acquisition request signals a2, a3 and a4 simultaneously generated from the respective bus masters 3, 4 and 5 at the time point b in FIG. 3 will be described. The AND 10 and the pulse transmitter 11 operate as described above. In the counter 12, each bus master priority state is changed by the internal clock signal of the counter 12 until the priority state at the time point a is shifted to the time point b.

The priority state of the counter 12 at the time point b is as follows: bus master 3> bus master 4> bus master 5. This state is referred to as state signals a12 and a1.
The data is output from the counter 12 as 3, a14. In the priority determination encoder 13, the individual state signal a1
2, a13, and a14, and encodes the previously received system bus acquisition permission signals a6, a7, and a8, and outputs a system bus acquisition permission signal a15.
Hereinafter, in response to the system bus acquisition permission signals a3 and a4 from the bus masters 4 and 5 that are not serviced in this state, as described above, the system bus acquisition permission signals a16 and a17 are arranged in descending order of priority. The data is output on the system bus 9.

As described above, according to this embodiment, the AND1 receiving the bus acquisition request signal from each bus master
At 0, the bus acquisition request signal from each bus master and the time at which the request was generated are recorded, and each bus acquisition request signal is output to the maximum value determination encoder 13 and the pulse generator 11. Upon receiving the bus acquisition request signal, the pulse generator 11 receives priority information at the time when the bus acquisition request of each bus master, which is initially set by the priority setting register 14, occurs, and sends a trigger signal to the counter 12. Output.

The counter 12 receiving the trigger signal outputs a variable request signal at that time to the maximum value determination encoder 13. The maximum value determination encoder section receives the bus acquisition request signal from the AND 10 and the counter 12
And outputs a bus acquisition permission signal to the system bus in response to the bus acquisition request signal having the highest priority at that time. At this time, the bus acquisition request signal of the bus master to which no bus has been given is held, and the bus acquisition request signal of the next higher priority bus master is serviced at the same time when the service of the previous bus master ends.

[0025]

As described above, according to the bus arbiter control device of the present invention, the time of occurrence of a bus acquisition request and the priority are weighted to give one of the bus masters permission to acquire the bus. Therefore, the above-mentioned disadvantages of the prior art can be compensated for and the bus can be used with high system bus use efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a bus arbiter control device according to the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention in detail.

FIG. 3 is a characteristic diagram showing the priority of each bus master over time.

FIG. 4 is a block diagram showing a conventional bus arbiter device.

[Explanation of symbols]

1, 34 Central processing unit 2 Main memory 3 Bus bridge bus arbiter (bus master) 4, 5 Bus master 6, 7 Bus slave 8, 9, 31 Bus 10 AND 11 Pulse generator 12 Counter 13 Maximum value judgment encoder 14 Priority setting Register 15 Bus arbiter control device 32 Main storage device 33 Bus arbitration control device 35, 36 Input / output control device 43, 44, 45 Timer

Claims (2)

[Claims] 1. A bus acquisition request from a plurality of bus masters is weighted based on the time when the bus acquisition request is generated and the priority order of the bus master, and the bus acquisition request is weighted based on the weighted bus acquisition request. One of the bus masters
A bus arbiter control device, wherein a bus arbiter is given permission for bus acquisition. 2. An individual bus master status signal indicating a priority status of each bus master upon receipt of a system bus acquisition request signal including priority information and an acquisition request signal including a time signal indicating a time at which the request occurred. A bus arbiter control device for outputting a system bus acquisition permission signal in response to the highest priority system bus acquisition request signal at that time based on the system bus acquisition request signal and the status signal. .