JPH10271582A - Cross connection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify device constitution and a control method and to improve reliability and maintainability by embedding size information and connection information inside a time switch and condensing cross connection information including the size information to one part. SOLUTION: For time division multiplex signals for which the signals of different sizes are mapped, division into minimum units is respectively performed, the address of a connection destination is written to a leading unit, a fixed pattern not pertinent to any address is written to the remaining minimum units and it is turned to a means for performing recognition as the boundary of service. At the timing when the output of an address control memory 31 is an effective address value, a size counter 35 loads the address value and increases it at each minimum timing of the signals. Thus, for the inquiry of present cross connection information, both of a signal size and connection destination information are simultaneously answered and the control of a control processor 33 is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a TDM (Time Division Multiplexing) digital signal cross-connect device.

[0002]

2. Description of the Related Art In general, in the field of information and communication, due to the rapid development of semiconductor devices and optical communication technology, various types of large-capacity data including voice, data, video, video and the like have been developed from a framework starting from an old telephone network. Information can be handled, and as a result, the communication method has been greatly revised. Among them, even in a digital signal cross-connect device, different sizes of time-division multiplexed signals in which different sizes of signals (various signals) are mapped in one frame format are different. A need has arisen for cross-connecting signals (time switching, switching of the time axis).

First, the configuration and operation of a general time switch will be described with reference to FIG. Referring to FIG. 5, the illustrated time switch includes a data memory 10, an address control memory 11, an address counter 12, and a control processor unit 13. Now, as shown in FIG. 6A, an input signal having a frame of 125 μsec (= 8 kHz) is, for example, an 8-bit parallel PCM.
Data (telephone voice = 64 kbps) is multiplexed by 8 (D0 to D)
7) It is assumed that the signal has been output.

First, the manner in which the input signal 20 is written to the data memory 10 will be described. The input signal 20 is transmitted to the data memory 10 addressed by the address counter 12.
Is written and stored at a location within The address counter 12 outputs a frame signal 22 to the input signal 20.
6 is synchronized with the frame of the input signal 20, and is sequentially incremented for each PCM data within the frame by the clock signal 21 (FIG. 6).
(B)).

As described above, the address counter 12 that performs a periodic operation in accordance with the frame period of the input data 20
, The input signal 20 is periodically written to the data memory 10.

Next, how the data written as described above is read from the data memory 10 and the output data 23 is formed will be described. As an example, it is assumed that data as shown in FIG. 7 is written in advance in the address space of the address control memory 11 by the control processor 13. The address control memory 11
Upon receiving the address specified by the address counter 12, the stored data is output (FIG. 6C). This data is stored in a read address (R
ADD). Therefore, the data memory 10
The output signal 23 output as shown in FIG. 6D shows that the input signal is time-switched in units of 8-bit parallel PCM data (telephone voice).

That is, through the control processor unit 13,
In the address control memory 11, the number of the PCM data (telephone voice = 64 kbps) identified by the multiplexing order in the frame of the input signal 20 (0 to 7 in this example)
), The time switching operation according to the specification is performed.

[0008] Conventionally, when time-division multiplexed signals to which signals of different sizes are mapped are cross-connected as a group of signals of different sizes, the above-described time switch is used. Is being done.

Next, an example of the operation will be described with reference to FIG.

Referring to FIG. 5, input signal 20 is
It is assumed that the signal is a signal in which data having different bands as shown in FIG. In FIG. 2, there are three types of bands of the multiplexed signal, which are assumed to be A, B, and C, respectively. Multiplex signal A
Is a 64 kbps telephone voice similar to that shown in the first example. The multiplexed signal B (B1 to B3) has a size three times as large as A, and is divided into 64 kbps units to
1, B2, and B3. C has a size four times as large as A, and is divided into 64 kbps units to be C1, C2, C
3, C4.

When it is desired to time switch the multiplexed input signal to obtain an output signal as shown in FIG. 2 (d), write data as shown in FIG. It is realized by putting. Then, the write address of the address counter to the data memory is shown in FIG. 2B, and the read address to the data memory is as shown in FIG. 2C.

That is, similarly to the first example described with reference to FIGS. 6 and 7, the minimum size unit (in this case, 64 kbps) regardless of the size of the multiplexed signal.
Cross-connect control is performed every time. Therefore, a large-size signal such as B or C as shown in the example is divided into minimum sizes (64 kbps), and control is performed using 64 kbps as a cross-connect unit.

As the above-mentioned time switches, for example, those described in JP-A-62-155697 and JP-A-5-344087 are known.

[0014]

As described above, when cross-connecting time-division multiplexed signals on which signals of different sizes are mapped as a unit of the signals of different sizes, The cross-connect control information is written in the address control memory for each minimum unit of the multiplex signal. Here, considering the case where the cross-connection information is read from the control processor unit side, the case where the cross-connection information is read is, as a specific prominent example, an inquiry about the current cross-connection information from outside the apparatus. When this is done, there may be a case where a response to the inquiry is created based on information in the address control memory of the time switch unit.

In the conventional time switch, the information written in the address control memory is information for each minimum unit of the multiplexed signal, and does not have information on its size. Therefore, in the examples of FIGS. 2 and 8, whether eight signals of the same size as A are set for the cross-connect,
It cannot be distinguished whether the setting is as shown in FIG. 2 or the setting is for other signal sizes. As a result, in response to the above inquiry, only the information written in the address control memory
There is a problem that an answer such as "what size signal (service) is connected to where" cannot be generated.

However, in order to avoid such a problem,
In order to manage the cross connect information including the size information, it is conceivable to provide a storage unit different from the time switch unit. The "storage means different from the time switch unit" here includes, as a specific example, the internal RAM of the control processor unit in FIG. That is, the control processor unit sets the cross-connect information in the time switch unit, updates the control information in the internal RAM,
If an inquiry about cross-connect information occurs later, a method of generating a response based on the control information of the internal RAM is used.

However, the first means is provided by such means.
If the problem of (1) is avoided, the control information is duplicated (at two locations), and not only the storage area on the internal RAM of the control processor unit in the case of the above example is wasted, but also the information of the internal RAM is lost. And the information in the time switch must be double-managed to ensure the consistency of both data (both data must be consistent), making the internal configuration of the system more complex. There is a problem that becomes.

If the data in the internal RAM is lost for some reason, it is impossible for the device to restore the cross-connect information including the size information. is not.

An object of the present invention is to simplify the device configuration and control method, and as a result, to improve the reliability of the device,
An object of the present invention is to provide a cross-connect device capable of improving maintainability.

[0020]

In a time division multiplexed signal in which a plurality of signals of different sizes are multiplexed, the signal size which can be the minimum unit is X, and the size of the other multiplexed signals is X The cross-connect device according to the present invention performs a characteristic operation when it is an integral multiple of.

When performing a cross-connect setting for a time-division multiplexed signal that satisfies such a condition, an interface between the control processor unit and the address control memory is conventionally provided in a basic time switch configuration as shown in FIG. And means are provided for making it possible to identify the boundary between the multiplexed signal and the signal.

More specifically, as a method of setting data in the address control memory of the control processor unit, for a signal having a size equal to or larger than the unit size, an address corresponding to the head division unit among the minimum units is set as follows. Data is set so as to specify a time slot of an output signal to be connected, and a specific fixed value is written to an address corresponding to a subsequent division unit of the same signal.

Further, a means is provided between the address control memory and the data memory for converting the data set by the above setting method into an address string for reading data from the data memory. By this conversion means, the read control address to the data memory becomes the same format as the conventional one, and functions as a conventional time switch.

[0024] Specifically, in the operation in which the data set in the address control memory is sequentially read out in the frame cycle, this conversion means is used when an effective address other than the specific fixed value is written. It is assumed that a value is loaded at that timing, and thereafter, an operation of incrementing the value for each minimum time slot until the next load timing comes is performed.

The interface between the control processor unit and the address control memory uses means capable of distinguishing between multiplexed signals and signal boundaries, and the cross-connect information (address control memory) provided by this interface is used. Is converted by the control means to convert the setting data into an input address for reading to the data memory.

That is, an interface between the control processor unit and the address control memory which can identify the multiplexed signal and the boundary of the signal can be realized while guaranteeing the same time switch operation as in the prior art. Can be.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Referring to FIG. 1, similarly to the configuration of a general time switch as shown in FIG. 5, the illustrated cross-connect device comprises a data memory 30, an address control memory 31, an address counter 32, And a control processor unit 33. In addition, a size counter 35 is added between the address control memory 31 and the data memory 30. That is,
The output 44 of the address control memory 31 becomes the input of the size counter 35, and the output of the size counter 35 becomes the read address input (R AD
D).

Next, the operation of the cross-connect device shown in FIG. 1 will be described with reference to FIGS. 2, 3, and 4. In addition,
FIG. 3 shows the operation of each unit in FIG.

It is assumed that the input signal 40 is a signal obtained by multiplexing data having different sizes as shown in FIG. In FIG. 2A, there are three types of sizes of the multiplexed signal, which are A, B, and C, respectively. The multiplexed signal A is a signal having a minimum size, B is a signal three times as large, and C is a signal four times the size. Here, for the sake of convenience, the signal of B is divided into minimum units, which are respectively denoted by B1, B2, and B3. Similarly,
The signal of C is also divided in minimum units, and C1, C2,
C3 and C4.

First, the control processor unit 33
When performing the cross-connect setting to obtain the output data as shown in (d), the data is set in the address control memory 31 as shown in FIG. That is, the multiplexed signals (A, B, and C in the example) to be cross-connected are divided into the minimum units, the connection destination address is written in the first unit, and the remaining minimum unit is written in the remaining units. Writes a fixed pattern that does not correspond to any address.

The set data written in the address control memory 31 appears as an output 44 as a data string as shown in the table of FIG. 3 in synchronization with the frame period.

The size counter 35 loads the address value when the output of the address control memory 31 is a valid address value. Thereafter, until the next load timing, the signal is incremented for each minimum unit of the signal.

The above operation is performed for each signal to be multiplexed.
The operation is repeated according to the size of the signal. As a result, the operation of the size counter 35 is as shown in FIG. 3, which is the read address signal 48 of the data memory 30 (FIG. 2).
(See (c)). Therefore, the output signal shown in FIG.
As a result, a data string as shown in (d) is obtained, indicating that a desired cross-connect operation is performed.

Next, the case where the setting data is read from the control processor 33 to the address control memory 31 in the state where the above-mentioned cross-connect setting is performed will be additionally described.

Since the interface between the control processor 33 and the address control memory 31 is in the format as shown in FIG. 4, even when the data is read from the control processor 33, the data is read as a data string as shown in FIG. It is.

At this time, the control processor unit 33 determines that the signal from the point where the effective address value is read to immediately before the address where the next effective address value is stored is a group of signals. Therefore, taking the connection information relating to the multiplexed signal B as an example, "the signal of size 3 mapped to the second time slot of the input signal is set to the line with the fifth time slot of the output signal as the head position ( Cross-connect setting). " That is, instead of the setting information for each minimum unit as in the related art, the signal unit to be set for the cross connect is grouped, and the cross connect information can be reproduced together with the size of the signal. That is, in response to the inquiry about the current cross-connect information, both the signal size and the connection destination information (what size signal is set in which time slot of the output signal) can be returned.

Next, a specific example (particularly, a size counter) of the cross-connect device according to the present invention will be described with reference to FIG.

The cross-connect device shown in FIG. 9 is similar to the cross-connect device described with reference to FIG.
, An address control memory 51, an address counter 52, a control processor unit 53, and a size counter 55. However, in this example, the size counter 55 includes an 8-bit counter circuit 56 that uses the output signal 64 of the address control memory 51 as a load value and a fixed value FF (HEX) that outputs the output signal 64 (8-bit data) of the address control memory 51. ) And EX in bit units
-OR, and the resulting 8 bits are further logically
And a detection unit 57 that generates an R signal. Then, the signal generated by the detection unit 57 is connected to the load control input of the counter circuit 56.

In this example, the fixed pattern which does not correspond to any address described with reference to FIG.
F (HEX) is used.

The information on each address signal and the data length of the memory (address bit width / data bit width of data memory 50, address bit width / data bit width of address control memory 51, and bit width of address counter 52) are all set. It is assumed that it is 8 bits.

Next, the operation will be described with reference to FIGS. 9, 10, 11 and 2. FIG. 10 shows the operation of each unit in FIG.

It is assumed that the input signal 60 is a signal obtained by multiplexing data having different sizes as shown in FIG. In FIG. 2A, there are three types of sizes of the multiplexed signal, which are A, B, and C, respectively. The multiplexed signal A is a signal having a minimum size, B is a signal three times as large, and C is a signal four times the size. Here, for the sake of convenience, the signal of B is divided into minimum units, which are respectively denoted by B1, B2, and B3. Similarly,
The signal of B is also divided in minimum units, and C1, C2,
C3 and C4.

First, the control processor unit 53
When performing the cross-connect setting to obtain the output data as shown in (d), the data is set in the address control memory 51 as shown in FIG.

That is, the multiplexed signal (A, B, C in the example) to be set for the cross-connect is divided into the minimum units, the address of the connection destination is written in the head unit, and the remaining minimum unit is written. On the other hand, FF (HEX) is written as data as a fixed pattern that does not correspond to any time slot.

The setting data written in the address control memory 51 appears as an output 64 as a data string as shown in the table of FIG. 10 in synchronization with the frame period. This data sequence is shown on the time axis in FIG.
become that way.

The counter circuit 56 in the size counter 55
Is detected by the determination unit 57 at a timing when the output of the address control memory 51 becomes a valid address value, and at that timing, the address is loaded with the address value. Thereafter, the signal is incremented by the minimum unit of the signal until the next load timing. The operation of such a counter circuit is shown in the table of FIG.

The above operation is performed for the multiplexed signals A,
The operation is repeated for each of B and C in accordance with the size of the signal. As a result, the operation of the size counter 55 becomes as shown in FIG. 10, which becomes the read address signal 68 of the data memory 50. Therefore, a data string as shown in FIG. 2D is obtained as an output signal, and it can be seen that a desired cross-connect operation is performed.

FIG. 1 shows a case where the setting data is read from the control processor unit 33 to the address control memory 31 while the above operation is being performed under the above-described cross-connect setting state. Is the same as the case described in relation to.

[0050]

As described above, according to the present invention, for a time division multiplexed signal on which signals of different sizes are mapped, the signals of different sizes are cross-connected as a unit. The device is realized, and it becomes possible to obtain both the signal size and the connection destination information in response to an external inquiry about the current cross-connect information. Further, in the present invention, it is not necessary to newly provide a means for storing information relating to the signal size inside the device other than the time switch, so that the storage location of the size information can be saved. Connect information in one place in the device (time switch section)
Since it is possible to deploy cross-connect information only in the system, there is no need to distribute or duplicate the cross-connect information in the device, and there is a problem with assurance of data consistency, which is generally difficult to solve systematically. Can be eliminated.

That is, size information in the time switch,
By embedding connection information and consolidating cross-connect information including size information in one place, the signal lines between the control processor and the time switch and the control from the control processor are simplified without increasing the amount of information. A connecting device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a cross-connect device according to the present invention.

FIG. 2 is a time chart for explaining the operation of the cross-connect device according to the present invention.

FIG. 3 is a diagram showing an operation table for explaining the operation of the cross-connect device according to the present invention.

FIG. 4 is a diagram showing an example of a cross-connect set value used in the cross-connect device according to the present invention.

FIG. 5 is a block diagram showing a conventional cross-connect device.

FIG. 6 is a time chart for explaining the operation of the conventional cross-connect device.

FIG. 7 is a diagram illustrating an example of a cross-connect set value for explaining an operation of a conventional cross-connect device.

FIG. 8 is a diagram illustrating another example of a cross-connect set value for explaining an operation of the conventional cross-connect device.

FIG. 9 is a block diagram showing a specific example of a cross-connect device according to the present invention.

FIG. 10 is a diagram showing an operation table that supplements the operation of the cross-connect device shown in FIG. 9;

FIG. 11 is an example of a cross-connect set value used in the cross-connect device shown in FIG. 9;

[Explanation of symbols]

 10, 30, 50 Data memory 11, 31, 51 Address control memory 12, 32, 52 Address counter 13, 33, 53 Control processor unit 55 Size counter 56 Counter circuit 57 Detection unit

Claims (3)

[Claims] When controlling a time switch for receiving a time division multiplexed signal to which signals of different sizes are mapped and switching the signals of different sizes, each of the different size signals is included in setting information for the time switch. And a means for adding identification information for identifying a boundary between the signal and the multiplexed signal. 2. The cross-connect device according to claim 1, wherein a minimum unit of a plurality of multiplexed signal sizes is X, and all signal sizes are n times X (n is an integer of 1 or more). In some cases, a value indicating the connection destination is set for the head of the n pieces, and a predetermined specific fixed value is set for the remaining (n-1) pieces. And a cross-connect device. 3. The cross-connect device according to claim 1, wherein information for identifying a boundary between each of the multiplexed signal and the signal having the different size is added in the time switch. A cross-connect device comprising a generation unit for generating a control address sequence to be input to a data memory in order to obtain time-switched output data based on setting information.