JPH10271808A - Semiconductor switching device, semiconductor stack device and power conversion device using the same - Google Patents

Abstract

(57) [Problem] To commercialize a semiconductor switching device including a semiconductor switching element having a ring-shaped gate terminal, it is not always necessary to allow a turn-off gate current to flow evenly in a circumferential direction of the gate terminal. It was not easy. SOLUTION: A slit S is provided in a plate-shaped connection conductor BG connecting between a semiconductor switching element GCT and a gate driver BD to form parallel current paths GLP, GCP, GRP. [Effect] The turn-off gate current to the gate terminal RG flows almost uniformly through each parallel current path where the impedance is almost equal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switching device having a gate electrode and a gate driver for supplying a turn-off current between a gate electrode and a cathode electrode of the semiconductor switching device via a current path. The present invention relates to a switching device, a semiconductor stack device using the semiconductor switching device, and a power conversion device.

[0002]

2. Description of the Related Art An example of a circuit configuration of a conventional semiconductor switching device is shown in FIG. In FIG.
P is a semiconductor switching element, here it is a GTO (gate turn-off thyristor). GT
Between the gate and cathode of O3P, gate driver 4P to generate the gate turn-on control current I _GP is connected, the driver 4P, by applying the gate turn-on control current I _GP to the gate of GTO3P, GT
Turn on O3P. Furthermore, the driver 4P
Current change rate dI _GQP / dt is energized toward the cathode from the gate of the gate reverse current I _GQP given by 20 to 50 A / .mu.s. The gate reverse current I _GQP are those diverted from the anode current I _AP. At this time, the turn-off gain becomes a value within the range of 2 to 5, and the GTO3P turns off.

Further, a voltage V between an anode electrode and a cathode electrode is
In order to suppress the increase rate of the _AKP and (dV _AKP / dt) and a surge voltage, generally a snubber circuit is used. Here, the snubber circuit is configured as follows. That is, the snubber capacitor Cs and the snubber diode D _S is connected in parallel to GTO3P, also to discharge the electric charge charged in the snubber capacitor Cs at turn-off of GTO3P, snubber resistor R _S snubber diode It is connected in parallel to D _S.

[0004] Also, inductance 1P is rising rate of the anode current I _AP flowing when GTO3P is turned on dI
_The feedback diode 2P connected in parallel to the inductance 1P is for returning the energy generated in the inductance 1P when the GTO 3P is turned off.

The inductance Ls is the stray inductance of the snubber circuit wiring.

The measured waveform obtained by performing a turn-off test on the circuit of the semiconductor switching device is
As shown in FIG. In the figure, waveforms C1P, C2P and C3P are waveforms respectively showing the anode current I _AP , the voltage V _AKP between the anode electrode and the cathode electrode and the gate reverse current _IGQP , and the horizontal axis is the time axis.

In FIG. 41, at time tP1, GTO3
P is in a turned-on state, and the gate reverse current _IGQP is in a state of zero. At this time, the rate of rise d of the gate reverse current _IGQP
The absolute value of I _GQP / dt launch gate reverse current I _GQP as 20 to 50 A / .mu.s, (absolute value of the ratio given by the anode current I _AP / gate reverse current I _GQP) turn-off gain with the GTO3P own bookmarks the turn-off gain threshold and reaches (time tP2), the anode current I _AP starts decreasing, between the anode electrode and the cathode electrode of GTO3P voltage V
_AKP starts to rise. At this time, the current I _S also flows to the above-described snubber circuit side, and a voltage is generated by the rise rate of the current I _S and the inductance (snubber inductance) Ls of the snubber circuit, and this voltage is generated between the anode electrode and the cathode electrode. As a result of being superimposed on the voltage V _AKP , a spike voltage V _DSP is generated (time tP3). This spike voltage V _DSP causes power loss. For example, about 40
When a current of 00 A flows, the power loss becomes several MW. Therefore, it is necessary to keep the spike voltage V _DSP as low as possible, and efforts have been made to reduce the snubber inductance L _S conventionally.

Further, the rate of increase dV _AKP / d of the voltage V _AKP between the anode electrode and the cathode electrode after the generation of the spike voltage V _DSP.
t is changed sharply, the anode current I _AP maximum value is generated (time TP4), is thereafter it, the tail current is generated. Therefore, the product of this tail current and the voltage V _AKP gives
Further power losses occur. The voltage V _AKP is
At time tP5, the peak voltage is reached. After that,
The voltage V _AKP reaches the power supply voltage V _DD .

Therefore, such a rate of increase dV _AKP / dt
To suppress, is required snubber capacitor C _S already described. Capacitance value is represented by _{I AP / (dV AKP / dt} ), usually it is selected to satisfy the dV _AKP / dt ≦ 1000V / μs relationship.

FIGS. 42 and 43 show a GTO3P used in the conventional semiconductor switching device shown in FIG.
(The structure is roughly divided into a GTO element package and two stack electrodes.) Both figures include the gate driver 4P. 42 shows a side view of the GTO 3P viewed from the arrow direction DP2 shown in FIG. 43, but only a part of the GTO 3P is shown in a sectional view form. FIG. 43
43 is a plan view of a portion excluding the stack electrode 27Pa when the GTO3P is viewed from the arrow direction DP1 shown in FIG. 42.

In both FIGS. 42 and 43, reference numerals indicate the following members. That is, 20P is a GTO element, 4PL is an internal inductance of the gate driver 4P, and 21P and 22P are a gate external lead (gate lead-out line) and a cathode external lead (coaxially shielded or twisted lead, respectively). (Cathode take-out line). Then, by welding or soldering or fitting the gate terminal 25P of the GTO element 20P and one end of the gate external lead 21P to the metallic connecting member 23P, the two 25P and 21P are integrated, The cathode terminal 26P and one end of the cathode external lead 22P are welded, soldered, or fitted to the metal connecting member 24P to integrate the two 26P, 22P. As a result, both terminals 25P and 26P are connected to the gate driver 4P via the leads 21P and 22P, respectively.

Reference numerals 27Pa and 27Pb denote stack electrodes for pressing the GTO element 20P.

Reference numeral 28P denotes a semiconductor substrate on which a GTO segment is formed, and an A1 (aluminum) gate electrode 2 is formed on the outermost peripheral portion of the upper surface of the semiconductor substrate 28P.
9Pa is formed, and a cathode electrode 29Pb is formed corresponding to each segment on the upper surface inside the gate electrode 29Pa. Also, 30P and 31P
Are a cathode strain buffer plate and a cathode post electrode, which are sequentially mounted on the upper surface of the cathode electrode 29Pb on the upper surface of the semiconductor substrate 28P, respectively.
32P and 33P are anode electrodes (not shown) formed on the back surface of the semiconductor substrate 28P, respectively (in the back surface,
The cathode electrode 29Pb corresponds to a surface located on the opposite side), and is an anode strain buffer plate and an anode post electrode sequentially stacked on the cathode electrode 29Pb.

A ring-shaped gate electrode 34P is in contact with the upper surface of the gate electrode 29Pa of the semiconductor substrate 28P.
5P is a ring-shaped gate electrode 3 via a ring insulator 36P.
Disc spring pressing 4P against gate electrode 29Pa, 37P
Connects the ring-shaped gate electrode 34P to the cathode strain buffer plate 30.
38P is an insulating sheet for insulating from the post electrode 31P.
P is a gate lead fixed to the gate terminal 25P by brazing or welding and the other end is electrically connected to the gate terminal 25P. The other end of the gate lead 39P is fixed to the cathode post electrode 31P and the other end is a cathode terminal 26P. 40P is a second flange having one end fixed to the anode post electrode 33P, and 41P is a gate flange 25P on which the gate terminal 25P is provided on the inner surface of the opening. End portions 43P protruding from the upper and lower surfaces of the insulating tube 41P.
a and 43Pb are the first and second flanges 39P, respectively.
And 40P are hermetically fixed with the GTO
The element 20P has a sealed structure.

[0015]

The conventional semiconductor switching devices generally have two problems.

(1) First, as shown in FIG. 43, for example, as shown in FIG. 43, the lead 21P for taking out a gate reverse current is taken out from a local portion of the ring-shaped gate electrode 34P. is there. Therefore, the gate reverse current is extracted in one direction. As a result, at turn-off,
Non-uniformity of the cathode current occurs, and the above-mentioned power loss such as the spike loss and the loss due to the tail current is all locally concentrated on a part of the cathode surface inside the GTO, and each element of the GTO is caused by the occurrence of a local temperature rise. In addition, there is a problem in that each segment is broken and becomes conductive, and as a result, there is a high probability that a turn-off failure will occur, which has caused a problem in the reliability of the device.

FIG. 44 is a plan view of the GTO element, and FIG. 45 is a sectional view of the GTO element. FIG. 45 is a longitudinal sectional view of the line CSA-CSB shown in FIG. That is, among the GTO elements formed in the columnar wafer, the ring-shaped gate electrode 34P
, For example, in a region REO, the gate reverse current of the region formed in the region REI is larger.
Will be pulled out more quickly than in the case of the GTO element in FIG. On the other hand, the GTO segments formed in the central region REC of the wafer require a long time to turn off most, and the segments of the GTO are directed toward the cathode electrode of each segment in the central region REC. Since the cathode current I _K flows in from each of the surrounding segments, current concentration occurs in a part of the GTO inside the wafer.

(2) The second problem is caused by the presence of a snubber circuit, particularly a snubber capacitor. That is, as described above, at the time of turn-off, the snubber capacitor Cs
The charge charged up in FIG. 40 needs to be completely discharged before the next turn-off. Therefore, when the GTO3P is turned on, the charge is discharged through the snubber resistor R _S , which causes a large power loss. At this time, the power consumption capacity generated in the snubber resistor R _S is PW =＝ * Cs * f (V _DD ² + (V
_DM− V _DD ) ² ) Here, _VDD is a power supply voltage, and _VDM is a voltage when the snubber capacitor CS is charged up at the time of turning off. Therefore, it becomes necessary to provide a cooling device for cooling the entire device.

Connecting a snubber resistor having such a power capacity as described above results in that only the power generated by the snubber resistor becomes a loss in the power to be transmitted, resulting in a reduction in efficiency and This necessitates the installation of a cooling device, which has been a very serious problem in simplifying and miniaturizing the entire device.

In order to solve these problems, first, second and third electrodes are provided. When the first electrode is turned on in response to a turn-on control current applied to the third electrode, the first electrode is turned off. A semiconductor switching element that allows a main current flowing into the first electrode to flow directly from the first electrode to the second electrode, and is connected between the third electrode and the second electrode, and generates the turn-on control current to generate the second current. Drive control means for applying to the three electrodes, when turning off, all of the main current is commutated from the first electrode to the drive control means via the third electrode in a direction opposite to the turn-on control current. We devised a semiconductor switching device that was designed to solve the problem. However, further studies have been made in order to achieve actual commercialization, and when a turn-off current is supplied from a gate driver to a semiconductor switching element via a current path,
It has been found that how uniform the current can be applied to the gate terminal is a very important issue in sufficiently exhibiting the performance as a semiconductor switching device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to prevent power loss from being locally concentrated on some semiconductor switching elements in a semiconductor wafer and to prevent element destruction. In a semiconductor switching device or the like that prevents and thereby improves the reliability of the device, a semiconductor switching device in which current supply to a gate terminal is made with a uniform distribution, a semiconductor stack device and a power conversion device using the same. The purpose is to gain.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor switching device including a semiconductor switching element having a gate terminal extending in a circumferential direction, a current path having a turn-off current at a plurality of positions of the gate terminal. And a parallel current path flowing in parallel to the current path.

According to a second aspect of the present invention, the semiconductor switching device includes a gate terminal extending in a circumferential direction of the semiconductor switching element. Are parallel current paths flowing in parallel at a plurality of locations.

According to a third aspect of the present invention, there is provided a semiconductor switching device according to the second aspect, wherein the current path includes a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path. Are formed by laminating via an insulating layer, the two conductive layers are used as conductive regions, and a slit of a predetermined pattern is formed in the wiring substrate to form an insulating region.

According to a fourth aspect of the present invention, in the semiconductor switching device, the semiconductor switching element is provided with a gate terminal extending in a circumferential direction, and a current path includes a parallel current through which a turn-off current flows in parallel at a plurality of locations of the gate terminal. And a means for reducing a difference in impedance between the gate terminal and the gate driver in each current path of the parallel current path.

According to a fifth aspect of the present invention, in the semiconductor switching device, the semiconductor switching element is provided with a gate terminal extending in a circumferential direction, and a current path includes a parallel current in which a turn-off current flows in parallel at a plurality of locations of the gate terminal. And the gate driver is composed of a plurality of gate drivers, and the voltage applied to the semiconductor switching element of each of the gate drivers is set to a different voltage so as to reduce the difference between the currents of the parallel current paths. It is what it was.

According to a sixth aspect of the present invention, a semiconductor switching device includes a semiconductor switching element having a gate terminal extending in a circumferential direction, a gate driver including a plurality of gate drivers, and each of the gate drivers is composed of the semiconductor driver. A gate driver close to the semiconductor switching element is disposed before and after the switching element, and a gate driver far from the gate terminal is located at a location far from the gate terminal, and a gate driver far from the semiconductor switching element is located at a location near the gate terminal via a current path. Connected.

According to a seventh aspect of the present invention, in the semiconductor switching device according to the sixth aspect, the current path includes a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path. And a wiring board formed by laminating via an insulating layer, and a slit of a predetermined pattern is formed in the wiring board so that the turn-off current flows in parallel at a plurality of locations of the gate terminal through the current path. A gate driver near the semiconductor switching element is a current path connected to a part near the gate terminal through a current path connected to a part far from the gate terminal. Are connected to each other.

The semiconductor switching device according to claim 8 is the semiconductor switching device according to claim 6, wherein the current path comprises a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path. A plurality of pairs, the above-mentioned two conductive layers are alternately laminated via an insulating layer, a wiring board is formed, and the gate driver close to the semiconductor switching element is connected to the gate terminal via the plurality of partial conductive layers. The gate driver far from the semiconductor switching element is connected to a portion near the gate terminal via the plurality of pairs of the remaining conductive layers.

A semiconductor stack device according to a ninth aspect uses the semiconductor switching device according to any one of the first to eighth aspects, and includes a semiconductor switching element and a cooling member for radiating heat generated from the semiconductor switching element. Are arranged in a stacking mounting frame.

A power converter according to a tenth aspect uses the semiconductor switching device according to any one of the first to ninth aspects, and includes a gate control device that performs power conversion by gate-controlling the semiconductor switching element. It is a thing.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor switching device or semiconductor switching element of the present invention is used for various power converters such as a vehicle power converter, a UPS (uninterruptible power system), and an industrial power converter. , Power devices.

The core of the novel method for controlling a semiconductor switching element proposed by the present invention is that all of the main current flowing through the semiconductor switching element in the ON state is diverted to the drive circuit, thereby switching the semiconductor switching element. The point is to turn off.

Hereinafter, as such a semiconductor switching element, a gate turn-off thyristor (hereinafter referred to as G
An example using “TO” is shown. In this case, GTO
The first, second and third electrodes are respectively an anode electrode,
They correspond to a cathode electrode and a gate electrode. The semiconductor switching element is not limited to a semiconductor switching element having a four-layer structure such as GTO, and a transistor having a three-layer structure can be used as the semiconductor switching element of the present invention. In this case, when the NPN transistor is used, the first, second, and third electrodes correspond to a collector electrode, an emitter electrode, and a base electrode, respectively.
When a PNP transistor is used, the first, second, and third electrodes correspond to an emitter electrode, a collector electrode, and a base electrode, respectively.

Embodiment 1 FIG. 1 shows a circuit configuration of a semiconductor switching device 10 according to Embodiment 1 of the present invention. In the figure, each reference numeral indicates the following circuit element. That is, reference numeral 3 denotes a GTO as a semiconductor switching element, and a gate driver 4 is provided between the gate electrode 3G of the GTO 3 and the node 13 of the cathode electrode 3K.
(Drive control means) is connected.

The gate driver 4 has a driving power supply 4a
(Power supply voltage V _GD (for example, 20 V)), capacitor 4b,
It has an inductance 4C and a transistor 4d. still,
The detailed configuration is shown in FIG.

[0037] The gate driver 4 generates a turn-on control current I _G for turning on the GT03, wiring path or via the line L1 is applied to the current I _G to the gate electrode 3G. In response, GTO3 is turned on. Reference numeral 11 denotes a node, and 9 denotes a power supply for driving the device 10, that is, a main circuit power supply (power supply voltage V _DD ) of the device 10.

[0038] On the other hand, 1, increase rate of the main current to the anode current I _A flows when the GTO3 is turned on dI _A / dt
Is the inductance for suppressing the GTO, and 2 is the GTO
Reference numeral 3 denotes a return diode for returning the energy generated in the inductance 1 when the turn-off occurs.

5 is connected in parallel with the GTO 3 between the node 11 of the anode 3A and the node 12 of the cathode 3K, and increases the voltage V _AK between the anode and the cathode when the GTO 3 is turned off. Is a peak voltage suppression circuit for suppressing only the peak voltage generated with the above. The circuit 5, as described later, has a function of the voltage V _AK is held or clamped only the voltage V _AK predetermined time to a predetermined voltage value determined in accordance with the voltage blocking capacity of GTO3 during turn-off.

[0040] Here, when the turn-off, a conventional, rate of change or rate of rise of the gate reverse current I _GQ had flowed to the gate driver 4 side shunts from the main current I _A (slope) dI _GQ /
Make the absolute value of dt as large as possible (ideally, |
dI _GQ / dt | is ∞), and flowing all the main current I _A through the gate driver 4 as the gate reverse current I _GQ to node 12. That is, determined by the absolute value of the ratio of the main current I _A and the gate reverse current I _GQ turnoff gain G (= | I _A /
I _GQ |) to set it to 1 or less (G ≦ 1), the main current I all _A, and turn-on control current I _G in the reverse direction, the gate driver 4 from the anode electrode 3A via the gate electrode 3G And, it is commutated to the node 12 side, thereby turning off the GTO3. At this time, the cathode current I _K flowing through the GTO 3 directly from the anode electrode 3A to the cathode electrode 3K immediately stops flowing at all. In that sense, this method, rather than the shunt of the main current I _A, with each other to achieve a "commutation of the main current I _A."

Here, depending on the relationship between the power supply voltage value V _GD of the drive power supply (main power supply) 4a of the gate driver 4 and the inductance value of the loop R1, the value of the rise rate dI _GQ / dt may be changed. It is possible to set the rise rate | dI _GQ / dt | to an extremely large value close to the ∞ value by setting the values of both 4 (4a) and R1 appropriately.
Can be very short time it flows the main current I _A rolling a to all gate driver 4 side.

On the other hand, it is easy to realize such a commutation of the gate reverse current _IGQ by the gate driver 4 alone because the power supply voltage value V _GD that can be taken by the drive power supply 4a of the driver 4 is limited. However, on the other hand, the driving power supply voltage V _GD of the gate driver 4 is set to a practical value that can be set, and the absolute value of the rate of rise dI _GQ / dt required to set the gate turn-off gain G to 1 or less is set. Realizable loop R
It is actually possible to set the value of the internal inductance of 1.

Accordingly, a line L1 from the gate electrode 3G to the gate driver 4, a gate driver 4, a line L2 from the gate driver 4 to the cathode electrode 3K via the node 13, and a GTO3 between the gate and the cathode electrode
It is required that the value of the (floating) internal inductance in the loop or the path R1 including the internal path be reduced to a value necessary for setting the turn-off gain G to 1 or less.

[0044] However, the gate driver 4, so as to have a capacitance enough to carry the gate reverse current I _GQ of the main current I _A more values must be set.

For example, when the power supply voltage V _GD of the main power supply 4 _a of the gate driver 4 is set to 20 V and the absolute value of the rate of rise dI _GQ / dt is set to about 8000 A / μs, the inductance of the loop R 1 Preferably, the value is 2.5 nH or less, and the internal inductance value of the gate driver 4 is 1 nH or less.

FIG. 2 shows a specific circuit diagram of the gate driver 4 having such a capacitance. In the figure, a driving power supply 50 is a main power supply for driving the gate driver 4, a sub-power supply 51 is a power supply for turn-on gate current, and a sub-power supply 52 is a turn-on transistor Tr.
1, a power supply for a drive circuit 56 for driving Tr2, and a sub power supply 53 are a power supply for a turn-off gate current and a sub power supply 54.
Is a power supply for a drive circuit 57 for driving the turn-off transistor Tr3, and a sub-power supply 55 is a circuit section 58 for generating a turn-on signal and a turn-off signal from a control signal 62.
A power supply for driving a transistor Tr1 is a switch for supplying a turn-on Highgate current I _G1 shown in FIG. 3, a switch for the transistor Tr2 is to supply turn-constant gate current I _G2, the transistor Tr3 Is a switch for supplying a turn-off gate current _IGQ (gate reverse current). Incidentally, it was collectively the currents I _G1, I _G2 is a turn-on control current I _G. C1 is a capacitor for turn-on gate current I _G, C2 is a capacitor for turn-off gate current I _GQ.

In the above gate driver circuit 4, when a control signal 62 is given from outside, a noise cut circuit 59 is provided.
Removes noise components included in the control signal 62 from the control signal 62, receives the control signal from which the noise has been removed, and receives a turn-on signal generation circuit 60 and a turn-off signal generation circuit 61.
Generates a turn-on signal 63 and a turn-off signal 64, respectively, and supplies the signals 63, 64 to the corresponding drive circuits 56, 57.

The drive circuits 56 and 57 that have received the signals 63 and 34 operate as follows. That is, at time t ₀₁ , the drive circuit 56 generates a signal capable of driving the transistor Tr1 and supplies the signal to the base of the transistor Tr1. Here, both capacitors C1 and C2
Since it is charged, respectively and the sub power source 51 by the auxiliary power supply 53, turn-Highgate current I _G1 flows into GTO3 through the transistor Tr1 from the capacitor C1. Then, at time _t02 , the drive circuit 56 stops supplying the base current of the transistor Tr1, and this time,
A base current sufficient to drive the transistor Tr2 is generated and supplied to the base of the transistor Tr2. Thus, the transistor Tr1 is turned off, instead of the transistor Tr2 is turned on, turn-constant gate current I _G2 flows into GTO3 through the transistor Tr2 from the capacitor C1.

At time t ₁ , the drive circuit 56 stops supplying the base current of the transistor Tr2 and the drive circuit 5
7 generates a base current required to turn on the transistor Tr3 in response to the signal 64, and supplies the base current to the base of the transistor Tr3. Thus, the transistor Tr2 is turned off, a result of the transistor Tr3 is turned on instead, becomes the electric charge charged in the capacitor C2 is discharged to GTO3 side via the transistor Tr3, therefore, is turn-off gate current I _GQ GTO3
From the transistor Tr3 to the node 13 of the cathode electrode 3K of the GTO3. Moreover, the current I _GQ is equal to the absolute value of the main current I _A during a very short time, or becomes more values, conversely, the cathode current decreases during a very short time to zero value.

As described above, in order to realize the rise rate dI _GQ / dt such that the turn-off gain G becomes 1 or less, the loop R1 including the wiring path inside the gate driver 4 is required.
It is necessary to reduce the overall inductance value.
It is desired to realize this point by improving the mechanical parts such as the wiring or the package structure of the GTO element.

However, since the conventional GTO3P package structure has a structure as shown in FIGS. 42 and 43, the internal inductance of the GTO element 20P (lead 21P to ring-shaped gate electrode 34P to cathode electrode 30P). ~ Inductance of the path to the lead 22P)
Was a large value, for example, about 50 nH. This value, hardly, about 8000 A / .mu.s stuff increase rate dI _GQ / d
t cannot be achieved. Therefore, in order to reduce the internal inductance value of the GTO element 20P to a desired value such as 2 nH or less, for example, the gate-side connection part 23P and the cathode-side connection part 24P and the gate terminal 25P of the GTO element 20P Loss caused by each coupling with the cathode terminal 26P and the gate external lead 2
1P and cathode external lead 22P and gate driver 4
Loss caused by each coupling with P, gate lead 3
It is necessary to reduce the inductance value of 8P, and furthermore, the inductance value of each of the external lead wires 21P and 22P of the gate and the cathode occupying as much as 90% of the total inductance value in the loop R1.

Therefore, the applicant of the present application examined the package structure of the GTO element from the above viewpoint and made improvements, and as a result, realized a press-contact type semiconductor element having the following structure.

That is, FIG. 4 shows a press-contact type GTO element 20,
Stack electrodes 27a, 27 pressurizing it from above and below
FIG. 5 is a front view (excluding the stack electrode 27a) of the GTO element 20 viewed from the arrow direction D1 shown in FIG. Therefore, the line SA-S in FIG.
FIG. 4 is a longitudinal sectional view of B.

In FIGS. 4 and 5, each reference numeral indicates the following member. That is, 20 is a pressure contact type semiconductor element, that is,
Here, the entire GTO element is shown. Reference numeral 28 denotes a semiconductor substrate on which each segment of the GTO is formed.
8, an Al (aluminum) gate electrode 29a is formed on a surface located on the outer peripheral side of the upper surface of the upper surface of the semiconductor substrate 28. Further, each segment is formed on the upper surface of the semiconductor substrate 28 inside the gate electrode 29a. Each cathode electrode 29b is formed corresponding to the position. The structure of each segment or the wafer structure of the GTO element is the same as the structure shown in the sectional view of FIG.

Reference numerals 30 and 31 denote semiconductor substrates 28, respectively.
A cathode strain buffer plate and a cathode post electrode sequentially mounted on the upper surface of the cathode electrode 29b on the upper surface of the semiconductor substrate 8;
An anode strain buffer plate and an anode post electrode which are sequentially stacked on the front surface (the surface opposite to the cathode electrode 29b) of the anode electrode (not shown) formed on the back surface of
Reference numeral 34 denotes a ring-shaped gate electrode in contact with the upper surface of the gate electrode 29a of the semiconductor substrate 28, and reference numeral 38 denotes a ring-shaped gate terminal made of a ring-shaped metal plate.
Are slidably contacted with and disposed on the ring gate electrode 34. Reference numeral 35 denotes an elastic body such as a disc spring or a wave spring for pressing the ring-shaped gate electrode 34 against the gate electrode 29a together with the ring-shaped gate terminal 38 via the annular insulator 36.
An insulator made of an insulating sheet or the like for insulating the ring-shaped gate electrode 34 from the cathode strain buffer plate 30 and the cathode post electrode 31. Reference numeral 26 denotes a first flange having one end fixed to the cathode post electrode 31. And
Reference numeral 40 denotes a second flange one end of which is fixed to the anode post electrode 33. Reference numeral 41 denotes an insulating cylinder made of ceramic or the like and divided into upper and lower portions with the ring-shaped gate terminal 38 interposed therebetween and having a projection 42. is there. The outer peripheral portion 23 of the ring-shaped gate terminal 38 protrudes outward from the side surface of the insulating cylinder 41, and a plurality of mounting holes 21 are provided at predetermined intervals at a position on the inner peripheral side of the other end 38E. . The portion 43a protruding above the upper surface of the upper insulating cylinder 41 is the other end 2 of the first flange 26.
6E, and a portion 43b protruding downward from the back surface of the lower insulating cylinder 41 is hermetically fixed to the other end of the second flange 40, whereby the press-contact type semiconductor element 20 is hermetically sealed. Package structure.
The interior is replaced with an inert gas.

FIG. 6 is a plan view showing a mechanical portion of the gate driver 4. FIG. It is a longitudinal cross-sectional view showing a state where (pressurized) is mounted. 6 and 7, reference numeral 4A
Denotes a case for covering the gate driver main body 4C, 4B denotes a case serving as a seat for the gate driver main body 4C, and 70 denotes a gate driver main body 4 and a GTO.
1 shows an entire substrate on which a circuit pattern for electrically connecting to an element 20 is formed. The substrate 70 is formed of the gate lead wires 21P, 22P of the conventional package.
It is an alternative to (FIG. 42) and has sufficient strength to support the weight of the GTO element 20. Reference numeral 71 denotes a cathode electrode connected by pressure to the cathode electrode 29b of the GTO element 20, and corresponds to the stack electrode 27a. 21
A is a substrate 7 for connecting the GTO element 20 through the mounting hole 21 corresponding to the substrate 70 of the gate driver 4.
For example, about six mounting holes 21A are required to connect the gate driver 4 and the GTO element 20.

The above-described substrate 70 has the following two circuit pattern substrates facing each other with an insulator interposed therebetween. That is, the substrate 70 includes a gate lead substrate 72, a cathode lead substrate 73, and an insulator 74 for insulating the two substrates 72 and 73 from each other.
And The reason why such a multilayer substrate structure is provided is to reduce the internal inductance on the gate driver 4 side. The GTO element body 20 includes screws 75 and 76
Alternatively, it is connected to the gate driver main body 4C by welding, caulking, or the like.

As described above, the hermetic package of the present GTO3 uses the internal gate electrode 29 formed on the semiconductor substrate.
a ring-shaped or disk-shaped gate electrode 38 extending from the side a toward the gate driver main body 4C;
In addition, the package (20) directly connects the outer peripheral portion of the ring-shaped gate electrode 38 to the main body 4C of the gate driver 4.
Connected to the extended substrate 70 via the mounting hole 21A.
Just by fixing, it is connected to the gate driver 4. Therefore, no gate lead wire is used in the connection. Therefore, all the problems in the conventional configuration are improved. That is, the coupling loss that has conventionally occurred due to the coupling between the internal gate lead of the GTO element and the gate terminal and cathode terminal of the GTO element,
As described above, the take-out of the gate lead is greatly reduced by the disk-shaped structure, and the power loss corresponding to the coupling loss that has conventionally occurred due to the coupling between the external gate lead wire and the gate driver is reduced by the present invention. In this case, since the disk-shaped gate lead portion or the entire gate electrode 38 is directly connected to the substrate 70 for supplying the gate current of the gate driver 4, the number is greatly reduced. Furthermore, the inductance of the external gate leads themselves, which conventionally accounted for as much as 90% of the total inductance of loop R1, does not exist in the present invention, since they are not used themselves.

As described above, it is possible to reduce the internal inductance of the GTO element 20 (3) and the internal inductance of the gate driver 4. In addition to these improvements, by further contriving the connection between the GTO element 20 and the gate driver 4 as described above (FIG. 7), the GTO element 3 is turned on under the condition that the turn-off gain G ≦ 1. Rate of increase d that can be turned off
It is now possible to actually generate an area of _IGQ / dt.

The gate current may be taken out in two or four diagonally located directions using the substrate 70A shown in the plan view of FIG. Current may be taken out.

The operation of the semiconductor switch device having the above-described circuit configuration and mechanism will be described with reference to FIGS. 9 and 10. FIG. 9 shows the operation waveform, and FIG.
An equivalent model when TO3 is replaced by a circuit configuration including a PNP transistor 80 and an NPN transistor 81 is shown.

[0062] In FIG. 9, in a state where GTO3 is anode current I _A flows turned (time t _1), the control signal 62 rapidly gate driver 4 a gate reverse current I _GQ according to (Fig. 2) increasing Te than at Do increase rate or gradient, the gate reverse current I _GQ is the absolute value of a very short time reach the absolute value equal to the current value of the anode current I _a (I _GQ =
-I _A) (time T _2). In this state, the anode current I _A All gate electrode 3 flowing into the anode electrode 3A of GTO3
G, commutates to the gate driver 4 via the wiring path L1,
The relational expression of | GTO3 anode current I _A | ≦ | gate reverse current I _GQ | is satisfied, and the cathode current I _K = 0.
Thereafter, the gate reverse current I _GQ until GTO3 is completely turned off, | I _A | ≦ | maintains the state | I _GQ.

The current difference ΔI _GQ shown in FIG. 9 is considered to be a recovery current of the NPN transistor 81 shown in FIG. This is caused by the following phenomenon. That is, in FIG. 10, in the state where GTO3 is turned on anode current I _A is flowing through the semiconductor substrate, its current I _A, the cathode electrode 3K divided into the loop 82 and the loop 83 from the anode electrode 3A of GTO3 Flowing to When GTO3 turns off from this state,
All of the anode current I _A is strongly pulled toward the gate driver 4, and flows into the loop 84 and loop 85. At this time, the base current of the NPN transistor 81 is reversed from the positive direction to the negative direction, and the NPN transistor 81 is rapidly turned off, so that its internal carrier flows as a recovery current in a superimposed manner. This increase in the recovery current is expressed as the above-described current difference ΔI _GQ, and at this time, | gate reverse current I _GQ |> | anode current I _A |.

As described above, the gate reverse current | I _GQ |> | the anode current I _A |
When 1 is turned off, the PNP transistor 80
The base current becomes zero (I _B = 0), PNP transistor 80 will shift to the turn-off.

[0065] the voltage blocking capability and starts to recover (time T ₃₎ of the PNP transistor 80, the voltage V _AK between the anode and cathode electrode shown in FIG. 9 begins to rise, the anode-cathode voltage V _AK is the power supply voltage upon reaching equal to V _DD value (time T _4), the anode current I _a starts to decrease, GT03
Shifts to the turn-off state. The rate of increase dV _AK / dt of the voltage V _AK between the anode and the cathode at this time is G
It is determined only by the speed at which the voltage blocking function of the TO3 recovers, and not by an external connection circuit or the like. In this regard, the prior art that the rate of increase in the anode-cathode voltage depending on the snubber capacitor C _S has been determined, the present invention is clearly different.

[0066] In FIG. 9, the peak voltage (surge voltage) V _P of the present invention, GT03 main circuit when turned off (the power supply 9 node 11, GT03, loop up to the power supply 9 via the node 12) of the Stray inductance L
The electromotive voltage generated due to (the energy is E = 1 /
2 * L * I ² ) is a voltage obtained by being superimposed on the power supply voltage V _DD . If this peak voltage _VP is GTO
If the voltage blocking capability exceeds 3, the GTO3 will be destroyed. Therefore, the anode-cathode voltage V _AK continues to rise toward the peak voltage V _P at the time of turn-off of GTO3, the peak voltage suppressing circuit 5 for suppressing so as not to exceed the voltage blocking capability of GTO3, node 1 GTO3
It is necessary to connect GTO3 in parallel between 1 and 12. The peak voltage suppression circuit 5 in FIG. 1 has such a function, and is a voltage clamp circuit including, for example, a Zener diode, a varistor, a celestor, and an arrester. After the voltage V _AK, which continues to rise when the GTO is turned off, reaches a predetermined voltage value V _SP set within a range not exceeding the voltage blocking capability of the GTO 3,
If If there is no same circuit 5 the voltage V _AK reaches the peak voltage V _P, a predetermined time Delta] t (Fig. 9) is the time required for the returns to a predetermined voltage value V _SP, the voltage V _AK It is kept at the peak voltage V _SP after suppression. Therefore, without generating the peak voltage V _P, there is no possible GTO3 element is destroyed.

As described above, in the present invention, the GTO 3 is turned off by controlling the GTO 3 in the region RA of the rising rate dI _GQ / dt shown in FIG. 11 at the time of turning off. In the figure, a point PA on the curve CA, main current I _A
Is a commutation point where commutation to the gate driver 4 side occurs.
In this case, it is in an ideal state when it is considered that there is no recovery current. In reality, since the recovery current is superimposed on the commutated main current, the turn-off gain G <1
GTO3 is turned off in the region of FIG.

[0068] FIGS. 12 and 13, respectively, a diagram shows flow a relatively turn-off of the main current I _A in the prior art and the present invention. Conventional technology, for example,
No. 111262 (Swiss application no. 9110619)
19) and Japanese Patent Application Laid-Open No. 6-188411 (German Patent Application No.
As shown in (2), even at the time of turn-off, the cathode current I _K flows in the GTO3P. In other words, the main current I _A,
At the time of turn-off, the current is _{divided into} the cathode currents I _K and _IGQP . However, in this case, even if the cathode current I _K flowing in each segment is a small value, they flow intensively into some segments, so that the GTO
The problem of element destruction is inherent.

[0069] In contrast, in the present invention, as shown in FIG. 13, during turn-off, the cathode current I _K stops flowing at all, the main current I _A is commutated to the path of all the gate driver 4 side, the recovery current generation Gate reverse current _IGQ
Is the sum of the absolute value of the main current I _{A and} the absolute value of the recovery current, and the relational expression | I _GQ | ≧ | I _A | holds (in the prior art, | I _GQP | <| I _A |).

[0070] As described above, in the present invention, over in the turn-off mode period | anode current I _A | ≦ | gate reverse current I _GQ | become, because it uses a new gate commutation, the time of turning off the cathode The current I _K = 0,
A state in which a cathode current flows into the cathode surface inside the GTO3P does not occur at all, and local current concentration on the cathode surface which has conventionally caused a turn-off failure cannot occur at all. Therefore, there is no danger of element destruction due to turn-off failure in the present invention, and the reliability of the device is remarkably improved. This effect is a core effect of the present invention, and can be said to be an advantage that cannot be obtained even by the combination of the techniques shown in the above-mentioned documents.

In addition, the anode-cathode electrode voltage V
_{Since the} circuit 5 for suppressing the surge voltage by suppressing the rise of the _AK is provided, the spike voltage is cut off by the circuit 5 and no spike voltage is generated. Therefore, conventionally, the snubber capacitor C _S was required to discharge the charges accumulated during the turn-off can be eliminated. That is, the snubber circuit, which is indispensable in the prior art, can be made unnecessary, thereby realizing the miniaturization, simplification, low cost, and high efficiency of the device.

FIG. 14 shows a circuit configuration of a semiconductor switching device employing a peak voltage protection circuit different from that of FIG. In the figure, the same reference numerals as those in FIG. 1 indicate the same components. The package structure of the GTO 3 and the mechanism of the gate driver 4 are the same as those described with reference to FIG. Each of the reference numerals 6 to 8 represents G
An element constituting a protection circuit for suppressing or reducing power loss due to a spike voltage or a peak voltage (surge voltage) generated when the TO3 is turned off, and indicates a diode, a resistance element, and a capacitor in order. Especially,
Here, one end 15 of capacitor 8 (capacitance element) included in bypass line BL arranged in parallel with GTO 3 between nodes 11 and 12 includes resistance element 7 and is connected to power supply 9 at node 14. There is a feature in that the power supply 9 is connected to the power supply 9 via the wiring path R4.

The semiconductor switching device 10A as described above
The operation of the GTO 3 will be described with reference to FIG.

The operation of the GTO 3 in this case is described in FIG.
The operation is the same as that of the device of FIG. 1, and only the peak voltage suppressing operation of the anode-cathode electrode voltage V _AK is different from that of FIG. The measured waveform in FIG. 15 is I _A = 1000 (A /
d), V _AK = 1000 (V / d), I _GQ = 1200 (A
/ D), V _GD = 20 (V / d), and t = 2 (μs / d). In the figure, curves C1, C2, C3,
C4 respectively show the anode current I _A, the voltage V _AK between the anode and cathode electrodes, the gate reverse current I _GQ, the measured waveform of the gate voltage V _G.

[0075] In FIG. 14, the capacitor 8 is always being charged to the power supply voltage V _DD through a resistor element 7, at the time of turn-off operation, it exceeds the power supply voltage V _DD from the generator to the spike voltage V _DSP and the peak voltage V _P Only the current due to the voltage portion (V _DSP -V _DD , V _P -V _DD ) is absorbed by the capacitor 8 through the diode 6. Therefore, only the excess portion is newly charged in the capacitor 8 only for the excess time.

The above points will be described with reference to FIG.
Until the anode-cathode electrode voltage V _AK reaches the power supply voltage V _DD , the capacitor 8 does not function, and during this period (t ₂
Rise rate _dV AK / dt of -t ₁₎ is determined by the ability of GT03 (this time, all the main current I _A is commutated to the gate driver 4 side). The anode-cathode interelectrode voltage V _AK is the anode current I _A reaches the power supply voltage V _DD starts to decrease (time t _2), at the same time, node 1
The main current flowing into 1 starts flowing through the diode 6 to the capacitor 8 side, that is, to the bypass path BL. At this time, the rate of rise di / dt of the bypass current i flowing in and G
An electromotive voltage is generated by a closed circuit including the TO3, the diode 6, and the capacitor 8 or an inductance ( _Lf1 ) floating in the first loop R2. This is shown in FIG.
A spike voltage V _DSP shown in (time t _3). Since then, until the time t _5, the anode-cathode electrode voltage V
The difference between the peak voltage V _P and the power supply voltage V _DD of _AK is absorbed in the capacitor 8. At this time, the overcharged amount absorbed by the capacitor 8 is equal to or less than the voltage blocking capability of the GTO 3.
The capacitance value of the capacitor 8 is appropriately determined. In other words, the peak value V _P of the anode-cathode voltage V _AK rise to from time t ₄ to time t ₅ is to be equal to or less than the voltage blocking capability of the GT03, it is determined by the capacitance value of the capacitor 8.

The overcharge of the peak voltage absorbed by the capacitor 8 is discharged to the power supply 9 through the resistance element 7 until the next turn-off. On the other hand, even when the GTO 3 is turned on, the voltage or charge charged in the capacitor 8 is prevented from discharging by the diode 6 even if it tries to discharge, so that it is not discharged. Therefore, the capacitor 8 is always charged to a voltage equal to the power supply voltage V _DD .

The peak voltage V _P from time t ₄ to time t ₅ is based on the electromotive force generated by the stray inductance (L _A2 ) in the second loop R3 and the capacitance of the capacitor 8.

As described above, all of the energy stored in the capacitor 8 of the peak voltage suppression circuit or protection circuit of the semiconductor switching device 10A is reduced to zero value by the snubber resistor like the snubber capacitor in the prior art. Rather than being discharged, only the overcharged portion of it is discharged, and the discharge loss of the snubber circuit, which has conventionally been a problem, can be significantly reduced. Moreover, this semiconductor switching device 10A
In the above, the protection circuit is implemented by simply using the members used in the snubber circuit of the prior art as it is, and directly connecting the wiring of the resistance element used as the snubber resistance to the node 14 of the power supply 9 as the wiring path R4. Since the configuration can be simplified, that is, it is possible to sufficiently reduce the discharge loss by using the conventional snubber circuit as it is, and there is an advantage that a highly feasible device can be realized. Of course, also in the device 10A, the device destruction of the GTO 3 at the time of turn-off can be completely prevented as in the device 10 of FIG.

As mentioned in the previous section, the semiconductor switching device described with reference to FIGS.
Although the conventional problems are basically solved, in order to achieve actual commercialization, not only the structure, but also the workability during manufacturing and maintenance, etc. Consideration is needed and the issues raised in these embodiments must be resolved.

That is, when the turn-on current is supplied to the ring-shaped gate terminal, it is necessary to make the current distribution in the circumferential direction uniform. However, in the examples shown in FIGS. The terminals are connected by a board 70 which is a wide plate-shaped conductor. Therefore, the distance to the gate driver changes depending on the position of the gate terminal in the circumferential direction, and also in relation to the arrangement of the gate driver, a good and uniform current distribution cannot always be obtained. In the following, a description will be given of a semiconductor switching device which solves the above-mentioned problems newly appearing when these products are embodied. In the following, since the main points of interest are different from the contents described in FIGS. 1 to 15, the same or corresponding parts will be described with the new reference numerals.

Here, since the current paths to the gate driver and the semiconductor switching element are centered, attention is paid to them, and the above-mentioned FIG.
Will be described with reference to FIG. In the figure, GCT is a flat semiconductor switching element whose on / off is controlled by gate control of a gate turn-off thyristor or a transistor having a ring-shaped gate terminal RG shown in FIGS.
Is the cathode electrode. GD is a gate driver, G
TF is a turn-off gate driver, GTN is a turn-on gate driver, VDN and VDP are turn-off and turn-on power supplies, CF, respectively.
And CN are turn-off and turn-on capacitors, respectively, TrF is a turn-off transistor,
Tr1 and R1 are transistors and resistors for a turn-on high gate, and Tr2 and R2 are transistors and resistors for a turn-on steady gate.

The operation is not described in detail, but the transistors Tr1, Tr2, TrF are sequentially turned on and off in a series of timing sequences determined from the one-shot circuit and the buffer by the input of the control signal. For example, as shown in FIG. That is, the turn-on high gate current, the turn-on steady gate current, and the turn-off gate current are supplied between the gate terminal RG and the cathode electrode K.

FIG. 17 is a plan view showing a semiconductor switching device according to the first embodiment of the present invention which has solved the above-mentioned new problem. In the figure, newly appearing symbols will be described as follows. That is, BG is a plurality of output terminals P of the gate driver GD.
, P2,... Pn and a plate-shaped connection conductor for electrically and mechanically connecting the gate terminal RG, an annular portion BGR surrounding the gate terminal RG, and from the annular portion BGR to the gate driver GD. Straight part BGD extending toward
It is composed of In the annular portion BGR, an annular current path RP surrounding the gate terminal RG is formed between the annular portion BGR and the gate terminal RG. K is the above-described cathode electrode, and is located on the back side of the anode electrode A in FIG.

.., In are turn-off gate currents flowing from the gate terminal RG to the gate driver GD to turn off the semiconductor switching element GCT. These turn-off gate currents i1, i2,.
in is configured to flow between the gate driver GD and the ring-shaped gate terminal RG in a number of parallel circuits. That is, the current path width IW of the linear portion BGD of the plate-like connection conductor BG is made larger than the diameter D of the gate terminal RG of the semiconductor switching element GCT, and the current path width I of the linear portion BGD is increased.
W and the length GDTL of the current receiving end GDT from the gate terminal RG of the gate driver GD are substantially the same. Therefore, the turn-off gate currents at the end of the linear portion BGD of the plate-like connection conductor BG, for example, i1 and i2, flow out from the portion of the gate terminal RG far from the gate driver GD via the annular current path RP. is there. That is, in the annular gate terminal RG, the turn-off gate current flows out from the entire outer periphery of the gate terminal RG, and does not intensively flow out from one lead wire unlike the conventional one. Is distributed over the entire area of the internal gate electrode, and the current per unit area is small, so that a large turn-off gate current can flow. As a result, the turn-off time can be reduced, for example, by about 1/10 compared to the conventional one. Becomes extremely short. Further, the life of the gate region of the semiconductor switching element GCT, that is, the life of the semiconductor switching element GCT is increased, and the reliability is improved.

FIG. 18 is a circuit diagram for realizing the parallel current path shown in FIG. That is, in order to form a large number of parallel current paths, the gate driver GD is composed of n transistors and capacitors arranged sequentially along the direction of the current path width IW. Note that in FIG.
Of these, only the first, second, and n-th are extracted and shown. In the drawing, C1, C2, and Cn are capacitors, TrF1, TrF2, and TrFn are turn-off transistors, P1, P2, and Pn are output terminals of turn-off gate currents from the transistors, G1P, G2P, and G1.
nP is a parallel current path on the gate side in the plate-shaped connection conductor BG of FIG. 17, and K1P, K2P and KnP are respective parallel current paths on the cathode side of the plate-shaped connection conductor BG in FIG.

In FIG. 18 (the same applies to the same type of drawings described later), the turn-on gate driver GT
Although the illustration of N is simplified, the turn-on gate current is usually several tens of times smaller than the turn-off gate current in the semiconductor switching element of the present invention, and there is no particular problem with the current supply. This is because the description is omitted. However, since both the gate drivers GTF and GTN supply current to the gate terminal RG through a common current path, the presence of the turn-on gate driver GTN adversely affects the current distribution in the parallel current path of the turn-off gate current. However, as shown in FIG.
Since the resistor R is inserted on the output side of TN, there is no need to worry.

FIG. 19 shows the capacitors C1, C2, Cn and the turn-off transistor TrF in the circuit diagram of FIG.
1, TrF2, TrFn, semiconductor switching element GC
It is the top view which showed planarly the example of mounting arrangement | positioning to the plate-shaped connection conductor BG of T, and the structure of connection to the plate-shaped connection conductor BG. In the figure, the illustration of the turn-on gate driver GTN is omitted.

FIG. 20 shows the capacitors C1, C2, Cn and the turn-off transistor TrF in the circuit diagram of FIG.
1, TrF2, TrFn, semiconductor switching element GC
It is sectional drawing which showed the example of mounting arrangement | positioning to the plate-shaped connection conductor BG of T, and the structure of the connection to the plate-shaped connection conductor BG in cross section.
In the drawing, GR1 is a gate holding ring, KR1 is a cathode spacer ring, B1 is a conductor plate, and the gate holding ring GR1 and the conductor plate B are connected by a screwing mechanism (not shown).
1, the gate terminal RG is formed on the surface of the plate-shaped connection conductor BG by pressing and holding the plate-shaped connection conductor BG and the cathode spacer ring KR1 therebetween. The cathode electrode K is electrically connected to a cathode-side conductive layer (cathode-side current path) KP formed on the back surface of the plate-shaped connection conductor BG. The portion indicated by (1) in the drawing shows the connection structure between the plate-shaped connection conductor BG of the transistor Tr and the capacitor C, which constitute the unit unit of the gate driver, and the power supply VDN is included in FIG. FIG. Further, FIG. 21 is an enlarged view of (1) of FIG.
22 (1) and (2) show a cross section taken along line X1-X1 and a cross section taken along line X2-X2, respectively.

The cathode side terminal CK of the capacitor C is electrically insulated from the gate side conductive layer GP and has a through hole H1.
Is electrically connected to the cathode-side conductive layer KP on the lower surface. Also, the gate side terminal TG of the transistor Tr
Are electrically insulated from the cathode-side conductive layer KP and are electrically connected to the gate-side conductive layer GP on the upper surface by through holes H4. The negative terminals CN and TN of the capacitor C and the transistor Tr are connected to through holes H2 and H3, respectively, which are electrically insulated from both the gate conductive layer GR and the cathode conductive layer KP. The leads of the terminals CK, CN, TN, and TG are inserted into the through holes H1 to H4 from the upper surface, and are joined by soldering or the like from the lower surface.

As can be seen from FIGS. 20 to 22, the gate-side conductive layer GP (the current paths G1P, G2P,
GnP) and the cathode-side conductive layer KP (corresponding to the current paths K1P, K2P, and KnP shown in FIG. 18)
Since it is formed on the front and back of the plate-shaped connection conductor BG via a thin insulating layer, the turn-off gate current flows in the current paths on these front and back sides in opposite directions, and the inductance in this portion can be suppressed to an extremely small value. In combination with the above-described measures for forming a plurality of parallel current paths in a plane, the supply of a desired steep turn-off gate current based on the above-described principle can be easily and reliably performed.

FIG. 23 shows that the turn-off gate current in the embodiment shown in FIGS.
It is detected and shown at 16 locations around G, and in the figure, the horizontal axis represents each of the 16 locations around the gate terminal RG.
The vertical axis is the detected value, i is the turn-off gate current (however, the scale is a relative ratio), and Z is the time differential value di / dt of the turn-off gate current (however, the scale is a relative ratio). As shown in FIG. 23, it can be seen that the turn-off gate current i flows from the entire periphery of the gate terminal RG toward the gate driver GD. Therefore,
It can also be seen that the turn-off gate current at the gate terminal RG is distributed to the entire region of the internal gate electrode, and the current per unit area is reduced.

Embodiment 2 FIG. 24 is devised to further reduce the turn-off gate current value near the central portion in FIG. 23, that is, near the gate terminal RG closest to the gate driver GD, and thus increase the current value at other locations. FIG. 10 is a plan view of the embodiment, in which a pair of slits as shown in FIG.
That is, the insulating region S is provided. This insulating region S
It may be a long hole penetrating the straight portion BGD across the front and back, may be a groove with a bottom, or may be a slit in which an insulator is embedded. In any case, the insulating region S is, for example, a pair of linear insulating regions SD extending linearly in parallel from the gate driver GD to the semiconductor switching element GCT, and a pair of linear insulating regions SD Further, the semiconductor switching element GCT
And an inclined insulating region SE extending obliquely along the outer periphery of the gate terminal RG. These paired insulating regions S are located near the central portion in FIG. 24, that is, the gate driver GD of the gate terminal RG.
Since the turn-off gate current near the side closest to the above is led from the wide current path GCWP between the pair of inclined insulating regions SE to the narrow current path GCNP between the pair of linear insulating regions SD, it becomes difficult for the current to flow. 24, the current value of the central current path GCP decreases, and the current path GL other than the central current path GL
The current values of P and GRP increase, and the distribution of the turn-off gate current flowing in the gate terminal RG becomes more uniform.

FIG. 25 shows an example in which the insulating region S has only a simple linear shape, and the interval between the pair of insulating regions S, S is narrower as it is closer to the gate terminal RG.
Since the shape of the insulating region S is simple, it can be manufactured at low cost. It should be noted that also in the example of FIG.
The current value of CP decreases, and the current paths GLP and GR other than the center
The current value of P increases, and the distribution of the turn-off gate current flowing in the gate terminal RG becomes more uniform.

Embodiment 3 FIG. 26 shows a method for further reducing the turn-off gate current value near the central part in FIG. 23, that is, near the side closest to the gate driver GD of the gate terminal RG. In the connection diagram showing another embodiment, three equivalent gate-side current paths GLP, GCP, and GRP from the gate terminal RG to the gate driver GD are provided, and the respective gate-side current paths GLP, GCP, and GRP are provided. Inductances LL, LC, LR, and resistance R constituting the impedance
The size of L, RC, and RR is set at the center G of the gate terminal RG.
Both end portions GL and GR of the gate terminal RG separated from the gate driver GD from the gate side current path GCP connected to C.
Are smaller than the gate-side current paths GLP and GRP. The inductance LC and the resistance RC of the gate side current path GCP connected to the central part GC of the gate terminal RG are the inductances L of the gate side current paths GLP and GRP connected to the end parts GL and GR other than the central part GC.
L, LR and resistances RL, RR, the vicinity of the central portion in FIG. 23, that is, the vicinity of the gate terminal RG on the side closest to the gate driver GD, ie, the central current path G
The turn-off gate current value of the CP can be further reduced. Therefore, the current values of the current paths GLP and GRP other than the center increase, and the distribution of the turn-off gate current flowing in the gate terminal RG is made more uniform.

In the drawing, KP is a cathode side current path connecting between the cathode electrode K and the gate driver GD, but is actually shown separately from KLP, KCP and KRP. Therefore, it is indicated by one KP put together. CL, CC and CR are capacitors, S
L, SC, and SR are turn-off transistors whose illustrations are simplified in the form of a single-pole switch.
As shown in FIG. 7, each of n capacitors and transistors is divided into three groups corresponding to the current paths GLP, GCP, and GRP.

FIG. 27 shows a specific example in which the circuit shown in FIG. 26 is mounted and arranged on a plate-like connection conductor BG, and a gate driver for turn-on is not shown. First to n-th (n = 6 in this example) six transistors TrF
1 to TrF6 and the like are arranged. The first and second driver outputs are connected to a current path GLP via a resistor RL and an inductance LL, and the third and fourth driver outputs are connected to a current path GCP via a resistor RC and an inductance LC. And the sixth driver output are sent to the current path GRP via the resistor RR and the inductance LR.

Embodiment 4 FIG. 28 is devised in order to further reduce the turn-off gate current value near the central portion in FIG. 23, that is, near the side closest to the gate driver GD of the gate terminal RG, and thus increase the current value at other points. In a connection diagram showing another embodiment, a gate terminal R
Equivalently, three gate-side current paths GLP, GCP, and GRP from G to the gate driver GD are provided, and each power supply voltage of each of the gate-side current paths GLP, GCP, and GRP is connected to the central part GC of the gate terminal RG. Gate-side current path G connected to both ends GL, GR of the gate terminal RG farther from the gate driver GD than the gate-side current path GCP thus set.
LP and GRP are higher. In the figure,
CL, CC, and CR are capacitors, SL, SC, and SR are turn-off transistors in the form of single-pole switches. VDN1 is, for example, a -18V turn-off DC power supply, and VDN2 is, for example, a -2V turn-off DC power supply. , KP are cathode-side current paths connecting between the cathode electrode K and the gate driver GD, and are simplified and shown in FIG.

The voltage between the gate-side current path GCP and the cathode-side current path KP connected to the central part GC of the gate terminal RG is 18 V, and the gate-side current paths GLP and GLP connected to both ends GL and GR are provided. The voltage between the GRP and the cathode side current path KP is 18 + 2 = 20V. As described above, the voltage between the gate-side current path GCP connected to the central part GC of the gate terminal RG and the cathode-side current path KP is higher than that of the gate-side current path GLP connected to both ends GL and GR. G
Since the voltage is lower than the voltage between RP and the cathode side current path KP, the vicinity of the central part in FIG. 23, that is, the vicinity of the gate terminal RG on the side closest to the gate driver GD, ie,
The turn-off gate current value of the central current path GCP can be further reduced. Therefore, current paths GLP, GRP other than the center
And the distribution of the turn-off gate current flowing in the gate terminal RG becomes more uniform.

FIG. 29 shows a specific example in which the circuit shown in FIG. 28 is mounted and arranged on a plate-like connection conductor BG, and a gate driver for turn-on is not shown. First to n-th (n = 6 in this example) six transistors TrF
1 to TrF6 and the like and DC power supplies VDN1 and VDN2 are arranged. The first and second drivers are connected to a power supply V.
A turn-off gate current output by the sum voltage (20 V) of DN1 and VDN2 is supplied to the current path GLP, and the third and fourth drivers supply a turn-off gate current output by the voltage (18 V) of the power supply VDN1 to the current path GCP. The fifth and sixth drivers send out a turn-off gate current, which is output by the sum voltage (20 V) of the power supplies VDN1 and VDN2, to the current path GRP.

Embodiment 5 FIG. FIG. 30 shows a semiconductor switching device having a gate driver for flowing a turn-off gate current between a gate terminal RG of a semiconductor switching element GCT and a cathode electrode K via current paths GLP, GRP, and GCP. Driver GT
F1 and GTF2, and each of these gate drivers GT
F1 and GTF2 are disposed before and after the semiconductor switching element GCT, and the semiconductor switching element GC
The gate driver GTF2 near T is connected to the current paths GLP and GR.
The semiconductor switching element G is located at a position (left, right, and front ends in the drawing) far from the gate terminal RG via P.
A gate driver GTF1 far from CT is located at a position near the gate terminal RG via the current path GCP (the central part in the drawing).
Are connected to each other.

In the figure, C1, C2 and S1, S2
Is a turn-off transistor represented by a capacitor and a single-pole switch of the gate driver GTF1, respectively, C
L1, CL2, CR1, CR2 and SL1, SL2,
SR1 and SR2 are turn-off transistors represented by capacitors and single-pole switches of the gate driver GTF2, respectively. In the figure, the gate driver for turn-on is not shown except the power supply VDP for convenience.

FIG. 31 shows a specific example in which the circuit shown in FIG. 30 is mounted and arranged on a plate-like connection conductor BG, and a turn-on gate driver is not shown. FIG. 1A is a plan view thereof, and FIG. 2B is a side view thereof. 32 is a sectional view taken along line X3-X3 of FIG. 31, and FIG.
It is sectional drawing of the X4 line. Here, the first conductive layers CC1 forming the gate-side current paths and the second conductive layers CC2 forming the cathode-side current paths as the plate-shaped connection conductors BG are alternately stacked via an insulating layer. Furthermore, this first
The first conductive layer CC1 has two layers, and the second conductive layer CC2 has two layers, that is, two pairs of conductive layers.

Then, as shown in FIG.
4, etc., so that a turn-off gate current is supplied from the gate driver GTF1 to the central portion GC of the gate terminal RG, and the left portion GL and the right portion GR are turned off from the gate driver GTF2. The current paths are separated in a plane so that a gate current is supplied. Further, as shown in FIG.
2 uses the uppermost layer and the second conductive layer among the four conductive layers of the plate-shaped connection conductor BG as the first conductive layer CC1-2 and the second conductive layer CC2-2, respectively. To the gate terminal TG and the cathode terminal CK. Then, the second conductive layer CC2-2 and the fourth conductive layer CC2-2 are formed by a through hole TH1 formed at a portion far from the gate terminal RG.
The layer is electrically connected to the conductive layer. As a result, the gate driver GTF2 near the semiconductor switching element GCT is pressed against and electrically connected to the gate terminal RG and the cathode electrode K at a position far from the gate terminal RG.

As shown in FIG. 33, the gate driver GTF1 includes the third conductive layer and the fourth conductive layer among the four conductive layers of the plate-shaped connection conductor BG, and the first conductive layer CC1.
-1 and the second conductive layer CC2-1, and their gate-side terminal TG and cathode-side terminal CK, respectively.
Connect. Then, the through hole TH2 formed at a position near the gate terminal RG causes the first conductive layer CC1-
1 is electrically connected to the first conductive layer. As a result,
A gate driver GTF1 far from the semiconductor switching element GCT is connected to a gate terminal RG at a position near the gate terminal RG.
And the cathode electrodes K are respectively pressed and electrically connected.

In the embodiment of FIGS. 32 and 33, the gate drivers GTF1 and GTF2 use upper and lower pairs of conductive layers of the plate-shaped connection conductors BG. Thorough isolation ensures that any of the gate drivers GTF1, GTF2
In both cases, four conductive layers may be used to connect to a portion near and far from the gate terminal RG.

As described above, in the fifth embodiment, the slits S are formed in the plate-like connection conductor BG to form current paths GCP, GLP, and GRP parallel to each other, so that the gate driver close to the semiconductor switching element GCT GTF2 is connected to the gate terminal R via the current paths GLP and GRP.
Since the gate driver GTF1 far from the semiconductor switching element GCT is connected to a portion near the gate terminal RG via the current path GCP at a portion far from G, the vicinity of the center portion in FIG. Near the side closest to the gate driver GD, that is,
The turn-off gate current value of the central current path GCP can be further reduced. Therefore, current paths GLP, GRP other than the center
And the distribution of the turn-off gate current flowing in the gate terminal RG becomes more uniform.

Embodiment 6 FIG. FIG. 34 shows the fifth embodiment.
In the same manner as described above, the gate driver is composed of two gate drivers GTF1 and GTF2 arranged in front and behind and connected to a portion near the gate terminal RG and a portion far from the gate terminal RG, respectively. Is different from the fifth embodiment. That is, in the sixth embodiment, the parallel current paths are formed by distinguishing the conductive layers used of the plate-shaped connection conductor BG, and will be described below with reference to FIGS.

FIG. 35 shows a specific example in which the circuit shown in FIG. 34 is mounted and arranged on a plate-like connection conductor BG, and a turn-on gate driver is not shown. FIG. 1A is a plan view thereof, and FIG. 2B is a side view thereof. FIG. 36 is a sectional view taken along line X5-X5 of FIG. Here, the first conductive layer CC1 forming the gate-side current path and the second conductive layer CC forming the cathode-side current path are used as the plate-shaped connection conductors BG.
2 are alternately stacked with an insulating layer interposed therebetween. Further, the first conductive layer CC1 is composed of two layers,
2 has two layers, that is, two pairs of conductive layers.

As shown in FIG. 36, gate driver GT
The gate terminal TG of F2 is electrically connected to the first conductive layer CC1-2 of the second layer of the plate-shaped connection conductor BG, and the cathode terminal CK of the gate driver GTF2 is connected to the second conductive layer of the third layer. It is electrically connected to CC2-2. And the first
Conductive layer CC1-2 is connected to the first conductive layer by a through hole TH3 formed at the tip of the gate terminal RG, and the first conductive layer is connected to the semiconductor switching element G.
It is pressed into contact with the gate terminal RG of the CT and is electrically connected. Although not shown, the first and fourth conductive layers are electrically insulated and separated from each other near a line connecting the left part GL and the right part GR of the semiconductor switching element GCT.

The second conductive layer CC2-2 is connected to the fourth conductive layer by a through hole TH4 formed at the tip of the gate terminal RG, and the fourth conductive layer is connected to the semiconductor switching element GCT. And is electrically connected to the cathode electrode K.

On the other hand, the gate terminal TG of the gate driver GTF1 is connected to the first conductive layer C of the first layer of the plate-shaped connection conductor BG.
C1-1 is electrically connected to the gate driver GTF1.
Is connected to the fourth conductive layer CC2- of the fourth layer.
1 electrically. Then, both conductive layers CC1-1
And CC2-1 are directly in pressure contact with the gate terminal RG and the cathode electrode K, respectively, and are electrically connected.

As described above, in the sixth embodiment, a plurality of pairs of conductive layers on the gate side and the cathode side are divided without providing a slit S or the like. In this example, of the four conductive layers, The current path FP for the gate driver GTF1 is formed by the first and fourth outer conductive layers, and the current path B for the gate driver GTF2 is formed by the second and third inner conductive layers.
P, the gate driver GTF2 close to the semiconductor switching element GCT passes through the current path BP to the gate terminal RG
23, the gate driver GTF1 far from the semiconductor switching element GCT is connected to a portion near the gate terminal RG via the current path FP. The turn-off gate current value in the vicinity of the side closest to the driver GD, that is, in the central current path GCP can be further reduced. Therefore, the current values of the current paths GLP and GRP other than the center increase, and the distribution of the turn-off gate current flowing in the gate terminal RG is made more uniform.

The method of forming a parallel current path group by providing slits according to the fifth embodiment and the method of dividing a plurality of pairs of conductive layers stacked in the sixth embodiment are equivalently used. The current distribution may be homogenized.

Embodiment 7 FIG. FIG. 37A shows a further decrease in the turn-off gate current value in the vicinity of the central portion in FIG. 23, that is, in the vicinity of the gate terminal RG near the side closest to the gate driver GD. FIG. 2B is a plan view showing another embodiment devised for the purpose, and FIG. 2B is a side view thereof, in which two turn-off gate drivers GTF1 and GTF2 are provided.
A semiconductor switching element GCT between TF1 and GTF2;
, The turn-off gate current flowing through the gate terminal RG is reduced by the gate drivers GTF1 and GT2.
Divide and flow into F2. 24, between the gate terminal RG and one gate driver GTF1 and between the gate terminal RG and the other gate driver GTF2.
An insulating region S similar to the embodiment of FIG. 25 is provided. Therefore, the current value is also suppressed at the gate terminal central portion GC on either side of the gate drivers GTF1 and GTF2, and the turn-off gate current is reduced by the both gate drivers GTF1 and GTF2.
The distribution of the turn-off gate current flowing in the gate terminal RG is more reliably equalized in combination with the shunting into two. The turn-on gate driver GTN1,
GTN2 is also the gate driver GTF1, GTF2 described above.
The arrangement is similar to that of the above.

Embodiment 8 FIG. FIG. 38 shows a case where a plurality of the semiconductor switching devices described above are used and assembled together with other peripheral parts as a semiconductor stack device. FIG. 1A is a structural diagram thereof, and FIG. 2B is a circuit block diagram thereof. In the figure, GCT is a semiconductor switching element, GD is a gate driver, FD is a freewheeling diode, SD is a snubber diode, FIN is a cooling fin as a cooling member, ST is a stack electrode, and IS is an insulating spacer. Among them, the cooling fin FIN is provided with a water cooling pipe PW.
Is connected, and radiates heat generated from the semiconductor switching element GCT and the free-wheeling diode FD to the cooling water. The FLM is a mounting frame for stacking the above components, tightening the components from above and below, and storing the components in a pressed state. Although the gate terminal RG in each of the above embodiments has been described as having a ring shape extending in the circumferential direction of the semiconductor switching element GCT, as shown in FIG. 39, the gate terminal RG extends in the circumferential direction of the semiconductor switching element GCT. A plurality of terminal pieces TS are provided at equal intervals along the same direction. In other words, the present invention can be similarly applied to a gate terminal RG1 extending discontinuously in the circumferential direction. It is effective. Further, by applying the semiconductor switching elements according to the present invention, and further including a gate control device that performs power conversion by gate-controlling these semiconductor switching elements, the distribution of the turn-off gate current flowing to the gate terminal is uniform as described above. Thus, it is possible to obtain a high-performance power converter such as an inverter capable of flowing a large turn-off gate current.

[0117]

As described above, the semiconductor switching device according to the first aspect is provided with the semiconductor switching element having the gate terminal extending in the circumferential direction. Since the parallel current path flows in parallel at the location, the turn-off current can flow in a uniform distribution over the circumferential direction of the gate terminal.

According to a second aspect of the present invention, in the semiconductor switching device, the semiconductor switching element is provided with a gate terminal extending in a circumferential direction, and a current path is formed by a conductor region and an insulating region so that a turn-off current is reduced by the gate terminal. Are formed in parallel at a plurality of locations, so that the parallel current paths can be simply and reliably formed.

In the semiconductor switching device according to the third aspect, the current path is formed by connecting the first conductive layer forming the gate side current path and the second conductive layer forming the cathode side current path via an insulating layer. Since both conductive layers are used as conductive regions and slits of a predetermined pattern are formed in the wiring substrate to form insulating regions, a low-impedance parallel current path can be easily and reliably obtained. Can be

According to a fourth aspect of the present invention, in the semiconductor switching device, the semiconductor switching element is provided with a gate terminal extending in a circumferential direction, and a current path includes a parallel current through which a turn-off current flows in parallel at a plurality of locations of the gate terminal. And a means for reducing the difference in impedance between the gate terminal and the gate driver in each current path of the parallel current path, so that the turn-off current of each parallel current path flowing in parallel to the gate terminal can be more reliably determined. A uniform state can be obtained.

According to a fifth aspect of the present invention, in the semiconductor switching device, the semiconductor switching element is provided with a gate terminal extending in a circumferential direction, and a current path includes a parallel current through which a turn-off current flows in parallel at a plurality of locations of the gate terminal. And the gate driver is composed of a plurality of gate drivers, and the voltage applied to the semiconductor switching element of each of the gate drivers is set to a different voltage so as to reduce the difference between the currents of the parallel current paths. Therefore, the turn-off current of each parallel current path flowing in parallel to the gate terminal can be more reliably made uniform.

A semiconductor switching device according to a sixth aspect of the present invention includes a semiconductor switching element having a gate terminal extending in a circumferential direction, a gate driver comprising a plurality of gate drivers, and each of the gate drivers being formed of the semiconductor driver. A gate driver close to the semiconductor switching element is disposed before and after the switching element, and a gate driver far from the gate terminal is located at a location far from the gate terminal, and a gate driver far from the semiconductor switching element is located at a location near the gate terminal via a current path. Connection, the turn-off current of each parallel current path flowing in parallel to the gate terminal can be more reliably made uniform.

Further, in the semiconductor switching device according to claim 7, the current path is formed by connecting the first conductive layer forming the gate side current path and the second conductive layer forming the cathode side current path via an insulating layer. And a wiring board formed by laminating the wiring board, and forming a slit of a predetermined pattern in the wiring board to make the current path a parallel current path in which the turn-off current flows in parallel to a plurality of positions of the gate terminal. A gate driver close to the semiconductor switching element is via a current path connected to a portion far from the gate terminal, and a gate driver far from the semiconductor switching element is via a current path connected to a portion near the gate terminal,
Since they are connected to each other, the impedance of each parallel current path becomes substantially uniform, and the distribution of current becomes more surely uniform.

Further, in the semiconductor switching device according to claim 8, the current paths are formed by a plurality of pairs of a first conductive layer forming a gate side current path and a second conductive layer forming a cathode side current path. A gate driver close to the semiconductor switching element is formed on a wiring substrate formed by alternately laminating both conductive layers via an insulating layer, and a portion far away from the gate terminal via the plurality of pairs of conductive layers, A gate driver far from the semiconductor switching element is connected to a portion near the gate terminal via the remaining conductive layers of the plurality of pairs, so that the impedance of each parallel current path is substantially uniform without providing a slit. , And the current distribution becomes more surely uniform.

The semiconductor stack device according to the ninth aspect and the power conversion device according to the tenth aspect are provided with the above-described semiconductor switching element, and in particular, the distribution of the turn-off current flowing to the gate terminal is uniform and a large turn-off current can flow. A high-performance semiconductor stack device and power conversion device that can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor switching device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of a gate driver circuit.

FIG. 3 is a diagram showing a waveform of a current flowing to a gate side.

FIG. 4 is a sectional view showing a GTO element package of the present invention.

FIG. 5 is a plan view showing the appearance of the GTO element package of the present invention.

FIG. 6 is a plan view showing the appearance of the gate driver of the present invention.

FIG. 7 is a cross-sectional view showing a method of connecting a GTO element package of the present invention to a gate driver.

FIG. 8 is a plan view showing a gate driver when extracting a gate reverse current from multiple directions.

FIG. 9 is a diagram showing an operation of the semiconductor switching device according to the first embodiment of the present invention.

FIG. 10 is a diagram showing an equivalent model of GTO.

FIG. 11 is a diagram showing the relationship between the rate of increase of the voltage between the anode and the cathode and the turn-off gain.

FIG. 12 is a diagram showing a flow of a main current at the time of turn-off according to the related art.

FIG. 13 is a diagram showing a flow of a main current at the time of turn-off in the present invention.

FIG. 14 is a circuit diagram of the semiconductor switching device according to the first embodiment of the present invention, which is different from FIG.

FIG. 15 is a diagram showing an actually measured waveform in the apparatus of FIG.

FIG. 16 is a diagram showing a gate driver circuit of the present invention, which is a simplified version of FIG. 2;

FIG. 17 is a diagram illustrating a schematic configuration of a semiconductor switching device according to the first embodiment of the present invention;

18 is a circuit configuration diagram for realizing the parallel current path shown in FIG.

19 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 18 on a plate-like connection conductor.

FIG. 20 is a cross-sectional view showing an example of mounting arrangement of the circuit configuration of FIG. 18 on a plate-like connection conductor.

21 is an enlarged view of a portion (1) in FIG.

FIG. 22 is a sectional view taken along line X1-X1 and X2-X2 of FIG. 21;

FIG. 23 is a view showing an actual measurement result of a turn-off gate current in a circumferential direction of a gate terminal.

FIG. 24 is a configuration diagram showing a semiconductor switching device according to a second embodiment of the present invention.

FIG. 25 is a configuration diagram showing a semiconductor switching device different from FIG. 24 in the second embodiment of the present invention.

FIG. 26 is a circuit diagram showing a semiconductor switching device according to a third embodiment of the present invention.

27 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 26 on a plate-like connection conductor.

FIG. 28 is a circuit diagram showing a semiconductor switching device according to a fourth embodiment of the present invention.

29 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 28 on a plate-like connection conductor.

FIG. 30 is a circuit diagram showing a semiconductor switching device according to a fifth embodiment of the present invention.

31 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 30 on a plate-like connection conductor.

32 is a sectional view taken along line X3-X3 of FIG.

FIG. 33 is a sectional view taken along line X4-X4 of FIG.

FIG. 34 is a circuit diagram showing a semiconductor switching device according to a sixth embodiment of the present invention.

35 is a diagram showing an example of mounting arrangement of the circuit configuration of FIG. 34 on a plate-like connection conductor.

36 is a sectional view taken along line X5-X5 of FIG.

FIG. 37 is a configuration diagram illustrating a semiconductor switching device according to a seventh embodiment of the present invention.

FIG. 38 is a configuration diagram showing a semiconductor stack device according to an eighth embodiment of the present invention.

FIG. 39 is a view showing a modification of the gate terminal RG extending in the circumferential direction.

FIG. 40 is a diagram showing a circuit of a conventional device.

FIG. 41 is a diagram showing measured waveforms by a conventional circuit.

FIG. 42 is a cross-sectional view of a conventional GTO element package.

FIG. 43 is a plan view showing the appearance of a conventional GTO element package.

FIG. 44 is a view for pointing out a conventional problem.

FIG. 45 is a view for pointing out a conventional problem.

[Explanation of symbols]

3 GTO, 3A anode electrode, 3K cathode electrode, 3G gate electrode, 4 a gate driver, 5 peak voltage suppression circuit, R1 path, I _A main current, I _G turn control current, I _GQ gate reverse current, GCT semiconductor switching element, RG, RG1 gate terminal, A anode electrode, K cathode electrode, GD gate driver, GTF turn-off gate driver, VDN1,
VDN2 DC power supply, BG plate-shaped connection conductor as wiring board, CC1 first conductive layer, CC2 second conductive layer,
S slit, GLP, GCP, GRP, FP, BP
Current path, FIN cooling fin, FLM mounting frame, TS
Terminal strip.

Claims (10)

[Claims] 1. A semiconductor switching device comprising: a semiconductor switching element having a gate electrode; and a gate driver for supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. A semiconductor switching device including a gate terminal extending in a circumferential direction, wherein the current path is a parallel current path in which the turn-off current flows in parallel at a plurality of locations of the gate terminal. . 2. A semiconductor switching device comprising: a semiconductor switching element having a gate electrode; and a gate driver for supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. The semiconductor switching element is provided with a gate terminal extending in a circumferential direction, the current path is formed of a conductor region and an insulating region, and the turn-off current flows in parallel at a plurality of positions of the gate terminal. A semiconductor switching device comprising: 3. A first current path forming a gate side current path.
And a second conductive layer forming a cathode-side current path is laminated with an insulating layer interposed therebetween, and the two conductive layers are used as conductive regions, and a predetermined pattern is formed on the wiring substrate. 3. The semiconductor switching device according to claim 2, wherein the slit is formed as an insulating region. 4. A semiconductor switching device comprising: a semiconductor switching element having a gate electrode; and a gate driver for supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. The semiconductor switching element has a gate terminal extending in a circumferential direction, and the current path is a parallel current path in which the turn-off current flows in parallel at a plurality of locations of the gate terminal. A means for reducing a difference in impedance between the gate terminal and the gate driver. 5. A semiconductor switching device comprising: a semiconductor switching element having a gate electrode; and a gate driver for supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. The semiconductor switching element is provided with a gate terminal extending in a circumferential direction, the current path is a parallel current path in which the turn-off current flows in parallel at a plurality of locations of the gate terminal, and the plurality of gate drivers are provided. Wherein the applied voltage to the semiconductor switching element of each of the gate drivers is set to a different voltage so as to reduce a difference between currents in the respective current paths of the parallel current paths. . 6. A semiconductor switching device comprising: a semiconductor switching element having a gate electrode; and a gate driver for supplying a turn-off current between the gate electrode and the cathode electrode of the semiconductor switching element via a current path. The semiconductor switching element is provided with a gate terminal extending in a circumferential direction, the gate driver is composed of a plurality of gate drivers, and each of these gate drivers is disposed before and after the semiconductor switching element, A gate driver close to the semiconductor switching element is located far from the gate terminal, and a gate driver far from the semiconductor switching element is located near the gate terminal.
A semiconductor switching device, wherein the semiconductor switching devices are connected via the current paths. 7. A first current path forming a gate side current path.
And a second conductive layer forming a cathode-side current path is laminated with an insulating layer interposed therebetween. Path is a parallel current path in which the turn-off current flows in parallel to a plurality of locations of the gate terminal,
A gate driver close to the semiconductor switching element is connected via a current path connected to a portion far from the gate terminal,
7. The semiconductor switching device according to claim 6, wherein the gate drivers far from the semiconductor switching element are connected to each other via a current path connected to a portion near the gate terminal. 8. The first current path forming a gate side current path.
A plurality of pairs of conductive layers and a second conductive layer forming a cathode-side current path, and a wiring board formed by alternately laminating the two conductive layers via an insulating layer, and a gate close to the semiconductor switching element. The driver is located at a position far from the gate terminal via the plurality of pairs of conductive layers, and the gate driver far from the semiconductor switching element is located at a position near the gate terminal via the remaining conductive layers of the pairs. 7. The semiconductor switching device according to claim 6, wherein each is connected. 9. The semiconductor device according to claim 1, wherein the semiconductor switching element and a cooling member for radiating heat generated from the semiconductor switching element are arranged in a stacked mounting frame.
A semiconductor stack device using the semiconductor switching device according to any one of claims 8 to 8. 10. A power conversion device using a semiconductor switching device according to claim 1, further comprising a gate control device for performing power conversion by gate-controlling the semiconductor switching device.