JPH1027191A - Logic circuit generator - Google Patents

Abstract

(57) [Problem] To generate a logic circuit diagram based on a file described in HDL (hardware description language), only a part of a specified part is required without a complete description. Provided is a logic circuit generation device capable of generating a partial logic circuit diagram. SOLUTION: When a "partial circuit generation mode" is selected from a keyboard 11, a processing mode discrimination unit 12 activates a partial circuit generation unit 16. In the statement extractor 16a of the partial circuit generator 16, the HDL file 17
Are extracted from the specified range command PF. In the local signal extraction unit 16b, the specified range statement P
An input signal and an output signal in F are extracted, and an intermediate file IF in which an intermediate language is converted is generated. The partial circuit generation unit 16c generates a partial logic circuit diagram from the intermediate file IF, assuming that the extracted input signal and output signal are all external signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit diagram for performing a logical operation equivalent to logic circuit information based on logic circuit information described in a hardware description language (HDL). The present invention relates to a logic circuit generation device such as a CAD (Computer Aided Design) device for generating a logic circuit.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional logic circuit generator for designing a logic circuit using HDL. This logic circuit generation device is, for example, a CA configured using a computer such as a workstation.
D device, which has an input device such as a keyboard 1. The keyboard 1 is an input device for a designer who designs a logic circuit to specify a processing mode and input data to the logic circuit generating device. Have been. The processing mode determination unit 2 determines whether or not “file input /
Processing mode designation information such as "edit mode", "logic circuit generation mode", and "simulation mode" is determined, and the corresponding processing function unit is started. The file generation unit 3 and the logic circuit generation unit 4 and a processing function unit of the simulation unit 5 are connected.

A file generation unit 3 is started in a file input / edit mode, inputs logic circuit information described in HDL, generates an HDL file 6, and generates an HDL file 6 based on the contents of the HDL file 6 already generated. And has a function of editing such as change / addition / deletion. The logic circuit generation unit 4 is activated in the logic circuit generation mode,
It has a function of generating a logic circuit diagram based on the L file 6. The logic circuit generation unit 4 includes an HDL file 6
A word analysis unit 4a for analyzing words described therein by a word dictionary (not shown), a syntax analysis unit 4b for checking whether or not a description method in the HDL file 6 conforms to a prescribed grammar; A circuit diagram generator 4c for generating an equivalent logic circuit diagram according to the syntax. The circuit diagram generation unit 4c outputs a circuit diagram file 7. The simulation unit 5 is activated in the simulation mode, and obtains the relationship between the state of each input signal and each output signal on the logic circuit diagram based on the logic circuit diagram of the circuit diagram file 7 and performs the operation of the logic circuit. It has a function to calculate the accompanying delay time. The HDL file 6, the circuit diagram file 7, and the simulation unit 5 are connected to the output unit 8, and the contents of the files 6, 7 and the result of the simulation unit 5 are displayed via the output unit 8. It is configured to be displayed on the unit 9.

The logic circuit design by this logic circuit design device is performed as follows. First, the designer specifies “file input / edit mode” by pressing, for example, a specific function key from the keyboard 1. When the processing mode discrimination unit 2 detects this designation, the file creation unit 3 is activated and enters the file input / edit mode. The designer uses the keyboard 1 to input / edit logic circuit information by HDL. The HDL file 6 being input / edited is displayed on the display unit 9 via the output unit 8. When the input / edit of all the logic circuit information to be designed is completed, a completed HDL file 6 is created. FIG.
Is a diagram showing an example of the contents of an HDL file 6 described in HDL. The HDL file 6 in FIG. 3 is a Cadence simulation language Verilog-HDL.
And is described in a complete format from the module declaration statement on line L1 to the module end statement on line L5.

When the creation of the HDL file 6 is completed, the designer next designates a “logic circuit generation mode” from the keyboard 1. When the processing mode determination unit 2 detects this designation, the logic circuit generation unit 4 is activated, and enters the logic circuit generation mode. The HDL file 6 is read by the word analysis unit 4a of the logic circuit generation unit 4, the words described in the HDL file 6 are extracted, collated with a word dictionary, and classified into command words, input / output signals, and the like. This analysis result is converted into an intermediate language suitable for the logic circuit diagram generation processing, and is provided to the syntax analyzer 4b as an intermediate file IF. The syntax analysis unit 4b checks whether or not the intermediate file IF is described according to the syntax of the simulation language Verilog-HDL. If there is no error as a result of the check by the syntax analysis unit 4b, the intermediate file IF
Is supplied to the circuit diagram generation unit 4c. The circuit diagram generation unit 4 generates a logic circuit diagram based on the intermediate file IF by referring to a component dictionary or the like (not shown) and outputs the circuit diagram file 7. The circuit diagram file 7 is displayed on the display unit 9 via the output unit 8.

The designer can know the configuration and scale of the designed logic circuit by looking at the circuit diagram file 7 displayed on the display unit 9 in the form of a drawing. Further, the designer can confirm the operation of the designed logic circuit by designating the “simulation mode” from the keyboard 1. When the processing mode determination unit 2 detects the “simulation mode” designation, the simulation unit 5
Is started and the simulation mode is entered. The designer inputs parameters necessary for the simulation of the logic circuit from the keyboard 1. The simulation section 5 simulates the operation of the logic circuit based on the input parameters and the logic circuit diagram read from the circuit diagram file 7. The result of this simulation is
The information is displayed on the display unit 9 via the output unit 8.

[0007]

However, the conventional logic circuit generator has the following problems. In the conventional logic circuit generation device, the syntax analyzer 4b uses H
It is checked whether or not the DL file 6 is described according to a certain grammar, and only in the case of a complete description without errors, the circuit diagram generation unit 4c generates a logic circuit diagram. The complete description here means the following (A) to (C)
It is a description that satisfies all the conditions such as. (A) The start and end of the file must be clearly indicated in the declaration statement determined by the HDL grammar. (A) The signal name in the logic circuit information is defined and the input / output destination is specified. (C) Be described in a format determined by the HDL grammar.

[0008] For this reason, a designer using a conventional logic circuit generation device cannot perform analysis by generation of a logic circuit diagram, simulation, or the like until the HDL file 6 is completely described. However, particularly when designing a large-scale logic circuit, it may be necessary to analyze some of the logic circuits while the designer is describing the logic circuit information. In such a case, a new H of only some of the logic circuits is used for analysis of some of the logic circuits.
It is necessary to create a DL file, which may reduce design efficiency. The present invention solves the problem of the prior art, and provides a logic circuit generation device capable of generating a logic circuit diagram based only on a description of a specified part even if an HDL description is not complete. Is what you do.

[0009]

In order to solve the above-mentioned problems, according to the present invention, a plurality of statements composed of a logical operation and an input signal and an output signal for the logical operation are fixed in an order of a target logical processing. Input logic circuit information described in units of rows according to grammar, analyze the plurality of command statements, and based on the analysis result, connect the input signal and output signal to a logic circuit corresponding to the logic operation, The following means is provided in a logic circuit generation device for generating a logic circuit diagram for realizing the target logic processing. That is, the logic circuit generating device of the present invention includes a designation unit that designates a first row and a last row corresponding to the partial logic circuit diagram in order to create a partial logic circuit diagram of a part of the logic circuit diagram; A command sentence extracting means for extracting a command sentence described between the first line and the last line as a specified range command from the logic circuit information; and Local signal extraction means for extracting an input signal and an output signal, and the extracted input signal and output signal,
A partial circuit generating means for performing word analysis and syntax analysis described in the designated range command statement assuming that the signals are all externally connected, and generating the partial logic circuit diagram based on the analysis result; Have been.

According to the present invention, since the logic circuit generator is configured as described above, the following operation is performed. According to a certain grammar, the first line and the last line are specified by the specifying means in order to generate a part of the logical circuit diagram from the logical circuit information described in the order of the target logical processing in the order of the logical processing. The specified range command specified by the first and last lines in the logic circuit diagram information is extracted by the command extraction unit. Further, all input signals and output signals described in the designated range command are extracted by the local signal extracting means. In the partial circuit generating means, the extracted input signal and output signal are all regarded as signals connected to the outside, and word analysis and syntax analysis described in the specified range statement are performed. A partial logic circuit diagram is generated based on the result.

[0011]

FIG. 1 is a configuration diagram of a logic circuit generation device showing an embodiment of the present invention. This logic circuit generation device is, for example, a CAD device, and has input / designation means (for example, a keyboard) 11. Keyboard 11
Is an input device used by a designer who designs a logic circuit to specify a processing mode and input data to the logic circuit generation device. The processing mode determining unit 12 is connected to the keyboard 11. Processing mode determination unit 12
Determines the processing mode specification information such as “file input / edit mode”, “logic circuit generation mode”, “simulation mode”, and “partial circuit generation mode” specified by the keyboard 11 and determines the corresponding processing function unit. It is something that starts. The processing mode determination unit 12 includes the file generation unit 1
3. The processing function units of the logic circuit generation unit 14, the simulation unit 15, and the partial circuit generation unit 16 are connected.

The file generation unit 13 is activated in the file input / edit mode, inputs logic circuit information described in HDL, generates an HDL file 17, and
It has a function of editing, such as changing / adding / deleting, the contents of the HDL file 17 that has already been generated. The logic circuit generation unit 14 is activated in the logic circuit generation mode, and has a function of generating a logic circuit diagram based on the HDL file 17. The logic circuit generation unit 14
A word analyzer 14a for analyzing words described in the L file 17 with reference to a word dictionary (not shown);
It has a syntax analyzer 14b for checking whether the description method in the L file 17 conforms to a prescribed grammar, and a circuit diagram generator 14c for generating an equivalent logic circuit diagram according to the analyzed syntax. The circuit diagram generation unit 14c outputs a circuit diagram file 18. The simulation unit 15 is activated in the simulation mode, and obtains the relationship between the state of each input signal on the logic circuit diagram and the state of each output signal on the basis of the logic circuit diagram in the circuit diagram file 18. It has a function of calculating a delay time associated with the operation of the circuit.

The partial circuit generator 16 generates a logical circuit diagram of a designated portion, and includes a command sentence extracting means (for example, a command sentence extracting unit) 16a and a local signal extracting means (for example, a local signal extracting unit). ) 16b and a partial circuit generating means (for example, a partial circuit generating unit) 16c. The command sentence extraction unit 16a is started in the partial circuit generation mode, and is described between the first line and the last line specified by the keyboard 11 to generate a partial logical circuit diagram of a part in the HDL file 17. It has a function to extract a command sentence. The command sentence extracted by the command sentence extraction unit 16a is provided to the local signal extraction unit 16b as a designated range command sentence PF. The local signal extraction unit 16b outputs the specified range statement PF
It has a function of extracting all input signals and output signals described therein, converting a command sentence into an intermediate language suitable for logic circuit diagram generation processing, and outputting it as an intermediate file IF. The intermediate file IF is stored in the partial circuit generator 16c.
Given to. The partial circuit generator 16c performs word analysis and syntax analysis on the basis of the intermediate file IF, assuming that all the extracted input signals and output signals are externally connected signals. Further, the partial circuit generation unit 16c has a function of generating a partial logic circuit diagram based on these analysis results. The configuration is such that the partial circuit diagram file 19 is output from the partial logic circuit generation unit 16c.

These simulation units 15, HDL
An output unit 20 for outputting the simulation result and the contents of the file is connected to the file 17, the circuit diagram file 18, and the partial circuit diagram file 19. Further, a display unit 21 for displaying output contents is connected to the output unit 20. Next, an operation of the logic circuit generation device when generating a partial logic circuit diagram will be described. First, the designer designates “file input / edit mode” from the keyboard 11 and creates, for example, an HDL file 17 as shown in FIG. The operation in inputting / editing the HDL file 17 is the same as the operation when the HDL file 6 is created by the conventional logic circuit generator of FIG.
However, in the HDL file 17 created here,
The description of the part that is not to be generated in the partial logic circuit diagram need not be complete.

Next, the designer designates a “partial circuit generation mode” from the keyboard 11. Processing mode determination unit 12
Detects this designation, the command sentence extraction unit 16a of the partial circuit generation unit 16 is activated and enters the partial circuit generation mode.
The designer specifies, from the keyboard 11, an HDL file 17 for which a partial logic circuit diagram is to be generated. Based on this designation, the contents of the HDL file 17 as shown in FIG. The designer uses the keyboard 11 and moves the cursor of the display unit 21 to the first row (for example, row L2 in FIG. 3) and the last row (for example, row L3 in FIG. 3) of the partial logic circuit diagram to be generated.
And. When the first line L2 and the last line L3 are specified, the instruction statement extracting unit 16a causes the lines L1 and L2 in FIG.
The intervening statement is extracted as a specified range statement PF. The extracted specified range statement PF is transmitted to the local signal extraction unit 16b.
Given to. In the local signal extraction unit 16b, an input signal and an output signal (for example, CLK and COUNT) are extracted from the words described in the specified range command sentence PF. Further, it is collated with a word dictionary (not shown), classified into command words, input / output signals, and the like, and converted into an intermediate file IF in an intermediate language. This intermediate file IF is provided to the partial circuit generator 16c. Partial circuit generator 16
In c, all the input signals and output signals in the given intermediate file IF are interpreted as externally connected signals, and a part dictionary or the like (not shown) is referred to based on the intermediate file IF, and A logic circuit diagram is generated. The generated partial logic circuit diagram is output as a partial circuit diagram file 19. The contents of the partial circuit diagram file 19 are displayed on the display unit 21 via the output unit 20, for example, as shown in FIG.
It is displayed as shown in (b).

FIGS. 4A and 4B are partial logic circuit diagrams generated by the logic circuit generator of FIG. 4A is a partial logic circuit diagram corresponding to lines L2 to L3 in the HDL file of FIG. 3 generated by the partial circuit generation unit 16, and FIG. Statement PF
FIG. 4 is a partial logic circuit diagram when lines L2 to L4 of the HDL file in FIG. 3 are selected. In addition, in the “logic circuit generation mode” and the “simulation mode”,
The operations of the logic circuit generator 14 and the simulation unit 15 are the same as the operations of the logic circuit generator 4 and the simulation unit 5 in the conventional logic circuit generator of FIG. 2, respectively. As described above, the logic circuit generation device according to the present embodiment includes:
The HDL file 17
A partial logic circuit diagram can be generated only for a designated part in the inside. For this reason, even before the description of the HDL file 17 is completed, there is an advantage that a partial logic circuit diagram of only the described portion can be generated and whether or not it is as intended can be confirmed.

Furthermore, the simulation of the partial logic circuit can be performed by the simulation unit 15 based on the partial circuit diagram file 19 generated by the partial circuit generation unit 16. This makes it possible to check whether or not the partial logic circuit has a function as expected by the designer. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(A) In the logic circuit generation device shown in FIG. 1, the functions of the processing mode discriminating unit 12, the file generating unit 13, and the like are configured as individual processing units. Alternatively, the configuration may be such that these functions are realized by program control. By the program control, it is possible to easily add functions other than the illustrated functions. (B) The HDL file 17 of FIG.
Although it is a file described in HDL, it is not limited to this language, and it is also possible to use a language such as VHSIC-HDL. (C) In the statement extractor 16a, the cursor is used to specify the first line and the last line for which the partial logic circuit is to be generated from the HDL file 17 displayed on the display unit 21, but the cursor is limited to the cursor. Instead, for example, it is also possible to use a method such as specifying using a mouse or inputting a line number from the keyboard 11.

[0019]

As described above in detail, according to the present invention, a partial logic circuit diagram is generated from a part of instructions and a part of input / output signals even when there is no complete description in HDL. Therefore, there are the following effects (1) to (3). (1) Even when a file is being described in HDL, a partial logic circuit diagram can be sequentially generated by specifying a location where a partial logic circuit diagram can be generated. By examining the actually generated partial logic circuit diagram, it is possible to determine whether or not the function considered by the designer is appropriate, and to reflect it in the HDL description thereafter. (2) By simulating the generated logic circuit, it can be determined whether or not the delay time of the logic circuit falls within an expected range, and this can be reflected in the description thereafter. (3) Since the scale of the logic circuit can be estimated during the description of the HDL, it is possible to determine whether it is necessary to divide the logic circuit before completing the complete description of the HDL.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a logic circuit generation device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional logic circuit generation device.

FIG. 3 is a diagram illustrating an example of the contents of an HDL file.

FIG. 4 is a partial logic circuit diagram generated by the logic circuit generation device of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Keyboard 12 Processing mode discrimination part 13 File generation part 14 Logic circuit generation part 14a Word analysis part 14b Syntax analysis part 14c Circuit diagram generation part 15 Simulation part 16 Partial circuit generation part 16a Command sentence extraction part 16b Local signal extraction part 16c Partial circuit Generation unit 17 HDL file 18 Circuit diagram file 19 Partial circuit diagram file 20 Output unit 21 Display unit

Claims (1)

[Claims] 1. A logic circuit information in which a plurality of command statements composed of a logical operation and an input signal and an output signal for the logical operation are described in units of rows according to a predetermined grammar in the order of a target logical process, and A plurality of command statements are analyzed, and based on the analysis result, the input signal and the output signal are connected to a logic circuit corresponding to the logic operation, and a logic circuit diagram for implementing the target logic processing is generated. In the logic circuit generation device, designating means for designating a first row and a last row corresponding to the partial logic circuit diagram to create a partial logic circuit diagram of a part of the logic circuit diagram; A statement extracting means for extracting a statement described between the first line and the last line as a specified range statement, and all input signals and output signals described in the specified range statement. Local signal extracting means for extracting the input signal and the output signal, and performing word analysis and syntax analysis described in the specified range command statement assuming that all of the extracted input signal and output signal are externally connected signals, A partial circuit generating means for generating the partial logical circuit diagram based on the analysis result.