JPH10274951A - Display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an optimum clock phase without performing complicated operation by providing on a clock pulse generation part with a delay amount adjusting part for adjusting the delay amount of a clock signal based on a luminance value from a judging part of received light value. SOLUTION: The clock pulse generation part 2 is provided with the delay amount adjusting part 6 for adjusting the delay amount of the clock signal based on the luminance value output from the judging part of received light value 11. A photodetector 10 receives a video displayed on a display device 52 and the judging part 11 outputs the luminance value of the received video and the adjusting part 6 adjusts the delay amount of the internal clock based on the luminance value. When the phase difference is made between the time signal of an analog video signal and the internal clock signal reproduced by the display device 52, the phase of the clock signal is automatically adjusted. Since the delay amount is adjusted based on the luminance value of received light at the photodetector 10, the clock phase is automatically optimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device, and more particularly, to an LCD (Liquid Crystal Display) and a PDP.
The present invention relates to a display control device that displays a video signal having no pixel clock signal on a pixel fixed display device such as a (plasma display panel). The display control device according to the present invention automatically adjusts the phase of the sampling clock.

[0002]

2. Description of the Related Art In a display device using a pixel fixed display element such as an LCD or PDP, an analog video signal from an analog interface such as a personal computer does not have a clock signal. Generates a clock signal corresponding to the horizontal synchronizing signal of the analog video signal.

FIG. 3 is a block diagram showing a configuration of a conventional display control device. As shown in FIG. 3, the display control device includes:
Video signal input terminal 57 to which an analog video signal is input
And input terminals 58 and 59 to which the horizontal synchronization signal and the vertical synchronization signal of the analog video signal are input, respectively. Further, a clock pulse generating circuit 55 for generating an internal clock, a frequency dividing circuit 53 for dividing this internal clock signal into a cycle of a horizontal yellow signal input to an input terminal 58, and a frequency dividing circuit 53 A phase comparison circuit 54 that compares the phase of the horizontal synchronization signal thus input with the phase of the horizontal synchronization signal input to the input terminal 58 and feeds back the comparison result to the clock pulse generation circuit. Thereby, the horizontal synchronization signal input to the horizontal synchronization signal input terminal 58 and the internal clock signal generated by the clock pulse generation circuit 55 are synchronized. further,
The display control device includes a sampling circuit 5 for sampling an analog video signal input to the video signal input terminal 7 based on the internal clock signal synchronized with the horizontal synchronization signal.
1 is provided.

In the conventional example shown in FIG. 2, there is a phase difference between an analog video signal timing of an input signal and an internal clock signal reproduced by a display device, so that a sampling error reduces the sharpness of an image. was there. Conventionally, in order to solve this problem, an operation of switching the clock phase by visual observation of the user's naked eye 60 and using a manual switch 61 or the like is performed.
Delay amount adjusting circuit 56 for adjusting the delay amount according to the operation of
And the adjustment was performed so as to obtain the optimum clock phase.

[0005]

However, when a conventional user visually changes the clock phase with a manual switch or the like, first, the adjustment becomes intuitive, and which point is the optimum clock phase for the user is determined. Second, the higher the resolution, the higher the resolution, the higher the resolution, and the more difficult it is for the user to know which point is the optimal clock phase.

A technique for automatically adjusting the phase of a data signal and a clock signal is disclosed in Japanese Patent Application Laid-Open Nos. 8-163117 and 228840/1990. According to this, assuming that a synchronization pattern equivalent to a clock signal is added to a data signal, the added synchronization pattern is extracted and fed back to the phase adjustment circuit. However, when a synchronization pattern equivalent to a clock signal is not added to an input video signal, it is not possible to optimize the phase adjustment by applying the method described in these publications.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the disadvantages of the prior art, and in particular, to provide a display control device capable of realizing an optimum clock phase without performing complicated operations. I do. That is, the first object is to eliminate the need for the user to visually switch the clock phase with a manual switch or the like, and to improve operability. A second object is to prevent variations in adjustment points due to intuitive adjustment, always realize an optimal clock phase, and improve characteristics and performance.

[0008]

Therefore, according to the present invention, there is provided a video signal input section to which an analog video signal and a synchronizing signal are input, and an internal clock signal synchronized with the synchronizing signal input to the video signal input section. And a sampling unit that samples an analog video signal in synchronization with the clock signal generated by the clock pulse generation unit and outputs the sampling data to a display device. In addition, the light receiving unit includes a light receiving unit that receives an image displayed on the display device, and a light receiving value determining unit that outputs a luminance value of the image received by the light receiving unit. Further, a configuration is adopted in which the clock pulse generation unit is provided with a delay amount adjustment unit that adjusts the delay amount of the clock signal based on the luminance value output from the received light value determination unit. This aims to achieve the above-mentioned object.

In the present invention, the light receiving section receives an image actually displayed on the display device, and the received light value judging section outputs a luminance value of the image. If there is a phase difference between the analog video signal timing and the internal clock signal reproduced by the display device, the luminance value of the video of the display device decreases, so that the delay amount adjustment unit is output from the received light value determination unit. The delay amount of the clock signal is specified based on the luminance value. Therefore, the phase adjustment of the clock signal is automated.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a display control device according to the present invention. The display control device includes: a video signal input unit 4 to which an analog video signal and a synchronization signal are input;
A clock pulse generator 2 that generates an internal clock signal in synchronization with the synchronization signal input to the video signal input unit 4
And a sampling unit 51 that samples an analog video signal in synchronization with the clock signal generated by the clock pulse generation unit 2 and outputs the sampling data to a display device.

In addition, the display control device according to the present embodiment comprises a light receiving section 1 for receiving an image displayed on the display device 52.
0 and a light receiving value judging unit 11 that outputs a luminance value of an image received by the light receiving unit 10. Further, the clock pulse generator 2 is provided with a delay amount adjuster 6 for adjusting the delay amount of the clock signal based on the luminance value output from the received light value determiner 11.

When a phase difference occurs between the timing of the analog video signal and the internal clock signal reproduced by the display device, the brightness of the video displayed on the display device 52 decreases.
When 0 receives an image displayed on the display device 52 and the received light value determination unit 11 outputs the luminance value of the received image, the phase of the internal clock being displayed can be evaluated. When the delay amount adjustment unit 6 adjusts the delay amount of the internal clock based on the luminance value, for example, based on a change in the luminance value output from the light reception value determination unit when the delay amount of the clock signal is increased or decreased, When the delay amount is specified (delay amount specifying function), the optimum delay amount can be automatically adjusted based on the output of the light receiving unit 10.

More specifically, the delay amount specifying function may specify the delay amount at which the luminance value output from the received light value judging unit 11 becomes the maximum value as the delay amount of the clock pulse. When the phase of the internal clock is optimized, the image becomes clearer,
Then, since the luminance increases, the delay amount when the luminance value becomes highest becomes the optimal delay amount.

In the present embodiment, since the delay amount of the internal clock signal is optimized by utilizing the fact that the luminance value decreases when the image becomes unclear, the image received by the light receiving unit is, for example, white and white. The effect is greater when the image is a pattern image such as a checkered pattern or a stripe composed of black. At this time, a checkered pattern or a stripe is set for each pixel of the display device. When optimizing the delay amount of the internal clock using the pattern image, the pattern image is generated by a personal computer or the like which is a higher-level device of the video display control device. In this case, the pattern image is output to the display device 52, and the pattern is received by the light receiving unit 10. A delay amount adjusting unit 6 adjusts a delay amount based on an output of the light receiving unit when a pattern image whose luminance value changes for each pixel of the display device is input to the video signal input unit. Is provided. As a result, the luminance value clearly changes due to the phase shift of the internal clock, and the delay amount can be optimized satisfactorily.

This pattern image is preferably a pattern image that becomes a stripe or checkerboard pattern for each pixel of the display device 52. Further, this pattern image may be a pattern image created with a combination of colors having greatly different luminance values such as white and black. When the display device 52 displays colors, the present invention is not limited to white and black, and a large number of colors having different luminance values may be combined.

As described above, in the present embodiment, when stripe or checkerboard display is performed on the display device in the unit of one pixel in the horizontal direction, the clock phase is higher than when sampling is performed at the optimum clock phase. In the case where sampling is performed with a shift, the screen luminance is reduced, the screen luminance is converted into an electric signal by the light receiving unit 10, and the optimum value is determined by the light receiving value determination circuit 11 by the delay amount adjusting unit 6.
, The clock phase can always be automatically adjusted to the optimal clock phase.

The light receiving section is one in the pixel fixed display device in the horizontal direction.
When stripe or checkerboard display is performed on a per-gauge basis, it is detected that the screen brightness increases when sampling is being performed at the optimal clock phase, and by feeding back to the delay adjustment unit, the optimal clock phase is obtained. Adjust automatically. Therefore, it is not necessary for the user to perform an operation of switching the clock phase visually and with a manual switch or the like. This clarifies the optimal adjustment point.

[0019]

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. In the example shown in FIG. 2, the display device is a fixed pixel display device, for example, an LCD or PDP. The video signal input unit 4 includes a video signal input terminal 57 to which an analog video signal is input, a horizontal synchronization signal input terminal 58 to which a horizontal synchronization signal of the analog video signal is input, and a vertical synchronization signal to which a vertical synchronization signal is input. And a signal input terminal 59.

The clock pulse generating section 2 includes a clock pulse generating circuit 55 for generating an internal clock, and a frequency dividing circuit 53 for dividing the internal clock signal into a cycle of a horizontal moving yellow signal input to an input terminal 58. , This frequency dividing circuit 53
And a phase comparing circuit 54 for comparing the phase of the horizontal synchronizing signal obtained by frequency division with the phase of the horizontal synchronizing signal input to the input terminal 58 and feeding back the comparison result to the clock pulse generating circuit. Thereby, the horizontal synchronization signal input to the horizontal synchronization signal input terminal 58 and the internal clock signal generated by the clock pulse generation circuit 55 are synchronized.

In this embodiment, the light receiving unit 10 is
A light receiving element (for example, a photodiode) 10 that receives the pattern image displayed on the pixel fixed vote own device 52 at one point.
Is adopted. The received light value determination circuit 11
Is converted to digital data. In the present embodiment, the delay amount adjusting unit is realized by the delay amount adjusting circuit 6.

Next, the operation will be described. The internal clock signal generated by the clock pulse generation circuit 5 is divided by the frequency dividing circuit 3 into the cycle of the horizontal synchronizing signal, and is divided by the horizontal synchronizing signal input to the horizontal synchronizing signal input terminal 8 and the frequency dividing circuit 3. The phase of the horizontal synchronizing signal is compared by the phase comparing circuit 4, and a feedback as to whether or not they match is given by:
The clock pulse generation circuit 5 synchronizes the horizontal synchronization signal input to the horizontal synchronization signal input terminal 8 with the internal clock signal generated by the clock pulse generation circuit 5.

Next, the clock signal at the time when the horizontal synchronizing signal input to the horizontal synchronizing signal input terminal 8 was generated, that is, the clock signal at the video signal output side device and the clock pulse generating circuit 5 of the present apparatus. In order to synchronize the internal clock signal, display from the video signal output side device repeats white and black in the form of vertical stripes on a per-screen basis,
Alternatively, a display in which white and black are repeated in a checkered pattern in pixel units is output and input to the video signal input terminal 57 of the present apparatus. In this case, the optimal clock phase is compared with the non-optimal clock phase. Applying that the screen brightness of the pixel fixed display device 2 increases by about ten and several cd / m 2, the delay amount adjusting circuit 6 raises and lowers the clock pulse phase delay by several steps, and the light receiving element 10 reduces the brightness. The received light is converted into an electric signal, and the electric signal converted from the luminance is determined by the received light value determination circuit 11, and the result is fed back to the delay amount adjustment circuit 6 so that the point at which the luminance finally received by the light receiving element 10 becomes maximum is obtained. The delay amount of the delay amount adjustment circuit 6 is set based on the data determined by the received light value determination circuit 11, and the clock phase is automatically adjusted.

As described above, according to the present embodiment, the pixel fixed display device 2 is visually checked with the naked eye as in the conventional example, and the delay amount adjusting circuit 6 is not manually and intuitively adjusted. A clear clock phase adjustment point can perform clear adjustment.

[0025]

According to the present invention, the light receiving section receives an image actually displayed on the display device, and the light receiving value judging section outputs the luminance value of the image. The delay amount adjusting unit determines the amount of delay of the clock signal based on the luminance value output from the received light value determining unit, so that the timing of the analog video signal and the internal clock signal reproduced by the display device are determined. If there is a phase difference,
It is possible to automatically adjust the phase of the clock signal by utilizing the property that the luminance value of the image of the display device decreases, and to adjust the delay amount based on the luminance value obtained by the light receiving unit. The objective and stable adjustment can be performed, and the clock phase can be automatically optimized regardless of the high resolution. As described above, it is possible to provide an unprecedented excellent display control device that can realize an optimal clock phase without performing a complicated operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 Reference Signs List 2 Clock pulse generator 4 Video signal input unit 6 Delay amount adjustment unit (delay amount adjustment circuit) 10 Light reception unit 11 Light reception value determination circuit 51 Sampling unit 52 Display device (fixed pixel display device) 53 Divider circuit 54 Phase comparison circuit 55 Clock pulse generation circuit 57 Video signal input terminal 58 Horizontal synchronization signal input terminal 59 Vertical synchronization signal input terminal

Claims (6)

[Claims] A video signal input unit to which an analog video signal and a synchronization signal are input; a clock pulse generation unit that generates an internal clock signal in synchronization with the synchronization signal input to the video signal input unit; A display control device comprising: a sampling unit that samples the analog video signal in synchronization with the clock signal generated by the clock pulse generation unit and outputs the sampled data to a display device. A light receiving unit that receives an image; and a light receiving value determining unit that outputs a luminance value of the image received by the light receiving unit. The clock pulse generator includes a light receiving unit based on the luminance value output from the light receiving value determining unit. A display control device, further comprising a delay amount adjusting unit for adjusting a delay amount of the clock signal. 2. A delay amount specifying function for specifying a delay amount based on a change in a luminance value output from the received light value determination unit when the delay amount of the clock signal is increased or decreased. The display control device according to claim 1, further comprising: 3. The delay amount specifying function includes a function of specifying a delay amount at which a luminance value output from the received light value determination unit has a maximum value as a delay amount of the clock pulse. Item 3. The display control device according to Item 2. 4. The delay amount adjusting unit adjusts a delay amount based on an output of the light receiving unit when a pattern image whose luminance value changes for each pixel of the display device is input to the video signal input unit. The display control device according to claim 1, further comprising a function of using a pattern image to be adjusted. 5. The method according to claim 1, wherein the pattern image is one of the display devices.
5. The display control device according to claim 4, wherein the image is a pattern image having a stripe or checkerboard pattern for each pixel. 6. The pattern image according to claim 4, wherein the pattern image is a pattern image created in white and black.
The display control device according to the above.