JPH10275865A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A function of a MOS transistor required for a peripheral circuit and an internal circuit of a semiconductor device or for a memory cell is realized by a simple method. In a method of manufacturing a semiconductor device including a heterogeneous N-channel MOS transistor formed on a semiconductor substrate, a method of manufacturing a first N-channel MOS transistor among the heterogeneous N-channel MOS transistors is provided. First, a gate electrode and a diffusion layer for source / drain are formed. In this step, the second N-channel MOS
The transistor or P-channel MOS transistor is protected by a polysilicon film. Then, after the formation of the first N-channel MOS transistor, a gate electrode and a source / drain diffusion layer of the second N-channel MOS transistor are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of an insulated gate field effect transistor (hereinafter, referred to as a MOS transistor) and a method of forming the same.

[0002]

2. Description of the Related Art In a semiconductor device mounted on a silicon semiconductor substrate, miniaturization and high density of a semiconductor element are still being energetically advanced.
Ultra-high-integration or ultra-high-speed semiconductor devices such as memory devices or logic devices designed on the basis of a size of 25 μm have been developed and prototyped. For high integration or ultra-high speed of such a semiconductor device, miniaturization of a semiconductor element constituting the semiconductor device is indispensable.

[0003] Among them, N channel type and P type
It is particularly important to miniaturize a channel type MOS transistor. Therefore, a shallow junction of a diffusion layer in a source / drain region of a MOS transistor or a short channel in a channel region of a MOS transistor has been vigorously performed. This is true for both P-channel MOS transistors and N-channel MOS transistors.

[0004] In addition to such a shallow junction of the diffusion layer of the MOS transistor, silicidation of the surface of the diffusion layer with a refractory metal or salicidation including the surface of the gate electrode improves the performance of a fine MOS transistor. It has become mandatory. In particular, in a logic device, such silicidation and salicidation are indispensable.

Further, in a memory device, it is required to reduce a leak current of a diffusion layer in a source / drain region. In particular, in a DRAM memory cell including one MOS transistor and one capacitor, the leakage current of the diffusion layer of the MOS transistor serving as a transfer gate is directly related to the retention time of stored information in the memory cell. As the semiconductor element becomes finer and the DRAM becomes highly integrated, the required holding time becomes longer.
Therefore, the impurity concentration of the diffusion layer of such a MOS transistor is reduced. Alternatively, silicidation of this region is omitted. This is because such a method is effective in reducing the leak current at the junction of the diffusion layer.

[0006] As the semiconductor elements become finer, memory devices and logic devices are mixedly mounted on one semiconductor chip. That is, various kinds of system-on-chip semiconductor devices are developed. However, in this case, it is necessary to match the manufacturing process of the memory device with that of the logic device.

Hereinafter, the latest memory devices, for example, 64
A manufacturing process of a MOS transistor used in a mega or 256 mega DRAM will be described with reference to FIGS. 5 and 6 are schematic sectional views in the order of manufacturing steps for explaining such a conventional technique. In this description,
The steps up to the formation of the basic structure of the MOS transistor and the structure are shown.

As shown in FIG. 5A, an N well 102 is formed in a predetermined region on a P-type silicon substrate 101. Then, the element isolation insulating film 103 is selectively formed on the surface of the silicon substrate 101. Here, the element isolation insulating film 103 is formed by a recess LOCOS (Local O
It is formed by an xidation of silicon method or a trench isolation method.

Next, a gate insulating film 104 is formed in the active region on the surface of the silicon substrate 101. Here, the gate insulating film 104 is a silicon oxide film having a thickness of about 8 nm. Then, a polycrystalline silicon film containing a high concentration of phosphorus impurities is deposited, and the polycrystalline silicon film is finely processed by a photolithography technique and a dry etching technique using the resist mask 105 as an etching mask. Thus, the gate electrodes 106 and 10 of the MOS transistor
7, 108 are formed.

Next, as shown in FIG. 5B, phosphorus ions 109 are implanted into the entire surface. Here, the energy of ion implantation is about 50 keV, and the dose is 1
Each is set to about × 10 ¹⁴ ions / cm ² . Then, an N-type low concentration diffusion layer 110 is formed on the surface of the silicon substrate 101 so as to be self-aligned with the element isolation insulating film and the gate electrodes 106 and 107. Similarly, on the surface of the N-well 102, an N-type low-concentration diffusion layer 110 is formed in self-alignment with the element isolation insulating film 103 and the gate electrode 108.

Next, as shown in FIG. 5C, a spacer insulating film 111 is deposited on the entire surface. Here, the spacer insulating film 111 is a silicon oxide film having a thickness of about 100 nm.

Next, the spacer insulating film 111 is etched back by anisotropic dry etching. here,
The reaction gas for dry etching is a mixed gas of C ₂ H ₂ F ₂ and CO. Thus, the spacer insulating film 112 is formed on the side walls of the gate electrodes 106, 107 and 108 as shown in FIG. In this etch-back process, the surface of the element isolation insulating film 103 has a thickness of 50 nm to 100 n.
about m. This is because about 100% over-etching is performed in the manufacturing process due to variations in the thickness of the spacer insulating film 111 and variations in the etching within the wafer.

Next, a resist mask 113 is formed as shown in FIG. This resist mask 113
Exposes the gate electrode 106 and the spacer insulating film 112. Arsenic ions 114 are implanted using the resist mask 113 as a mask. Here, the implantation energy is set to about 70 keV, and the dose is set to about 5 × 10 ¹⁵ ions / cm ² . In this way,
The N-type high-concentration diffusion layer 11
5 are formed.

Next, a resist mask 116 is formed as shown in FIG. This resist mask 116
Exposes the gate electrode 108 and the spacer insulating film 112 on the N well 102. This resist mask 1
Boron ions 117 are implanted using 16 as a mask. Here, the implantation energy is set to about 20 keV, and the dose is set to about 1 × 10 ¹⁵ ions / cm ² . Thus, a P-type high concentration diffusion layer 118 is formed in the region of the N-type low concentration diffusion layer 110.

Next, the resist mask 116 is removed. Then, cleaning and heat treatment of the silicon substrate are performed. By this heat treatment, the P-type high-concentration diffusion layer 118 on the N-well 102 is spread by thermal diffusion, and the N-type low-concentration diffusion layer 110 formed first is included in the P-type high-concentration diffusion layer 118a.

As described above, as shown in FIG. 6C, the LD composed of the N-type low-concentration diffusion layer 110 and the N-type high-concentration diffusion layer 115 formed on the silicon substrate 101.
A first N-channel MOS having a source / drain diffusion layer having a D (Lightly Doped Drain) structure, a gate insulating film 104 and a gate electrode 106;
A transistor is formed. Then, the N-type low-concentration diffusion layer 110 becomes a diffusion layer for source / drain, and a second N-channel MOS transistor having the gate insulating film 104 and the gate electrode 107 is also formed. Furthermore, the P formed in the N well 102 region on the silicon substrate 101
The high-concentration diffusion layer 118a is a diffusion layer for source / drain, and a P-channel MOS transistor having the gate insulating film 104 and the gate electrode 108 is formed.

Incidentally, such a first N-channel type MO
The S transistor, the second N-channel type MOS transistor, and the P-channel type MOS transistor are insulated from each other by an element isolation insulating film 103.

[0018]

As described above, in the conventional semiconductor device manufacturing method, the gate electrodes of a plurality of types of MOS transistors are formed by the same photolithography step and dry etching step.

For this purpose, an N-type low-concentration diffusion layer for the source / drain of the first N-channel MOS transistor constituting a peripheral circuit of the semiconductor device, and an internal circuit or a memory cell of the semiconductor device are constituted. The N-type low-concentration diffusion layers for the source and drain of the second N-channel MOS transistor are formed in the same structure. In this case, the film thickness of the element isolation insulating film in the region where the second N-channel MOS transistor is formed is reduced by the etch-back step of forming the spacer insulating film as described in the related art. I will do it. In addition, the etch back causes damage due to dry etching on the surface of the source / drain diffusion layer of the second N-channel MOS transistor.

This decrease in the thickness of the element isolation insulating film causes an increase in channel leakage current. Also, damage to the surface of the diffusion layer increases the leakage current of the diffusion layer. Then, due to these leak currents, the retention time of the stored information of the memory cell is reduced, and the function of the memory cell unit is reduced. Here, the first N-channel MOS transistor used in the peripheral circuit has no problem with such a leakage current.

In order to improve the performance of the first N-channel MOS transistor by using a conventional technique, the source / drain diffusion layer is silicided. The surface of the source / drain diffusion layer of the transistor is also silicided. However, silicidation of the surface of the source / drain diffusion layer of the second N-channel MOS transistor also increases the leakage current of the diffusion layer. For this reason, it is difficult to mix a memory device and a logic device on a semiconductor chip with the conventional technology.

An object of the present invention is to provide a semiconductor device with peripheral circuits and internal circuits or MO cells used for memory cells.
An object of the present invention is to provide a semiconductor device capable of optimizing the function of an S transistor by a simple method and a method of manufacturing the same.

[0023]

SUMMARY OF THE INVENTION To this end, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device including different types of N-channel insulated gate field effect transistors formed on a semiconductor substrate. And after first forming a gate electrode and a source / drain diffusion layer of the first N-channel insulated gate field-effect transistor among the different types of N-channel insulated gate field-effect transistors, The gate electrode and the source / drain diffusion layers of the second N-channel insulated gate field effect transistor are formed.

That is, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film in an active region on a semiconductor substrate and depositing a polysilicon film so as to cover the gate insulating film; A gate electrode of the N-channel insulated gate field effect transistor is formed, and the polysilicon film is left in a region where the second N-channel insulated gate field effect transistor or the P-channel insulated gate field effect transistor is formed. Patterning the polysilicon film;
Channel type insulated gate field effect transistor or P
An impurity is ion-implanted using a polysilicon film remaining in a region where a channel-type insulated gate field-effect transistor is formed as a mask, and a spacer insulating film is formed on a side wall of the gate electrode. Forming source / drain regions of the gate field effect transistor.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film in an active region on a semiconductor substrate and depositing a polysilicon film so as to cover the gate insulating film; A gate electrode of the N-channel insulated gate field effect transistor is formed, and the polysilicon film is left in a region where the second N-channel insulated gate field effect transistor or the P-channel insulated gate field effect transistor is formed. Patterning the polysilicon film;
Channel type insulated gate field effect transistor or P
Impurities are ion-implanted using the polysilicon film remaining in the formation region of the channel type insulated gate field effect transistor as a mask, and a spacer insulating film is formed on the side wall of the gate electrode to form the first N channel type insulated gate field effect transistor. Forming a source / drain diffusion layer; and forming the source electrode / drain diffusion layer and the second N-channel insulated gate field-effect transistor or the P-channel insulated gate field-effect transistor. Selectively forming a silicide layer on the polysilicon film remaining in the region.

Further, in the method of manufacturing a semiconductor device according to the present invention, the polysilicon film remaining in the formation region of the second N-channel insulated gate field effect transistor or the P-channel insulated gate field effect transistor or the polysilicon film Patterning the upper silicide layer to form a gate electrode of the second N-channel insulated gate field effect transistor; and ion-implanting impurities again to form a source / drain of the second N-channel insulated gate field effect transistor. Forming a diffusion layer.

In the semiconductor device of the present invention, the peripheral circuit of the semiconductor device is constituted by the first N-channel insulated gate field effect transistor as described above, and the internal circuit or the memory cell of the semiconductor device is constituted by the second circuit. It is composed of an N-channel insulated gate field effect transistor.

As described above, according to the present invention, the gate electrode of the first N-channel insulated gate field effect transistor is formed and the second N-channel insulated gate field effect transistor or the P-channel insulated gate field effect transistor is formed. The polysilicon film is patterned so that the polysilicon film remains in the formation region of.
Then, the polysilicon film remaining in the formation region of the second N-channel insulated gate field-effect transistor or the P-channel insulated gate field-effect transistor forms a source / drain region of the first N-channel insulated gate field-effect transistor. In the step of forming
Of the N channel type insulated gate field effect transistor or the P channel type insulated gate field effect transistor. Note that the number of photolithography steps in the manufacturing process according to the present invention is not different from that in the manufacturing process described in the related art.

As described above, a high-performance insulated gate field effect transistor can be formed for a peripheral circuit and an insulated gate field effect transistor having a low leak current can be formed for an internal circuit or a memory cell by a simple method. Become like

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. These drawings are cross-sectional views in the order of manufacturing steps for describing the method for manufacturing a semiconductor device of the present invention. Hereinafter, the manufacturing method of the present invention will be described. The structure of the semiconductor device of the present invention is shown in this description.

As shown in FIG. 1A, an N-well layer 2 of N-type conductivity is formed in a predetermined region of a silicon substrate 1 of P-type conductivity as described in the prior art. You. Then, the element isolation insulating film 3 is selectively formed on the surface of the silicon substrate 1.

Next, a gate insulating film 4 is formed in the active region on the surface of the silicon substrate 1. Here, the gate insulating film 4 is a silicon oxide film or a silicon oxynitride film having a thickness of about 6 nm. And 1 × 10 ²⁰ atoms /
A polysilicon film 5 containing a phosphorus impurity of about cm ³ is deposited by a chemical vapor deposition (CVD) method. Here, the thickness of the polysilicon film 5 is set to about 300 nm.

Next, as shown in FIG. 1B, the polysilicon film 5 is finely processed by dry etching using the resist mask 6 as an etching mask. Thus, first, the gate electrode 7 of the first N-channel MOS transistor for the peripheral circuit is formed. Thereafter, the resist mask 6 is removed.

Next, as shown in FIG. 1C, phosphorus ions 8 are implanted into the entire surface. Here, the energy of the ion implantation is about 40 keV, and the dose is 1 × 1.
0 ¹⁴ ions / cm ² about the respective set. Then, heat treatment is performed to form a first N-type low concentration diffusion layer 9.

Here, the region of the second N-channel MOS transistor and the P-channel MOS transistor which constitute the internal circuit or the memory cell is covered with the polysilicon film 5a. For this reason, the phosphorus ions 8 are not implanted into such a region.

Next, as shown in FIG. 2A, a spacer insulating film 10 is deposited so as to cover the entire surface of the polysilicon film 5a, the gate electrode 7, and the like. Here, the spacer insulating film 10 is a silicon oxide film having a thickness of about 150 nm.

Next, as described in the background art, the spacer insulating film 10 is etched back by anisotropic dry etching. Here, the reaction gas for the dry etching is a mixed gas of C ₄ F ₈ and CO. In this way, as shown in FIG. 2B, the spacer insulating films 11 and 11a are formed on the side walls of the gate electrode 7 and the polysilicon film 5a.
Is formed. Here, the element isolation insulating film 3 in the internal circuit or the memory cell region is covered with the polysilicon film 5a. For this reason, the surface of the element isolation insulating film 3 in this region is not etched at all in this etch back process.

Subsequently, as shown in FIG. 2C, arsenic ions 12 are implanted over the entire surface. Then, a heat treatment is performed. Here, the implantation energy is set to about 70 keV, and the dose is set to about 5 × 10 ¹⁵ ions / cm ² . Thus, the N-type high-concentration diffusion layer 13 is formed in a self-aligned manner with the gate electrode 7 and the spacer insulating film 11 and in the region of the first N-type low-concentration diffusion layer 9.

Here, the polysilicon film 5a is formed of the second N
Channel type MOS transistor and P channel type MO
Arsenic ions 12 are prevented from entering the region of the S transistor.

Next, as shown in FIG. 3A, the polysilicon film 5a is finely processed by dry etching using the resist mask 14 as an etching mask. Thus, the gate electrode 15 and the polysilicon film 5b of the second N-channel MOS transistor for the internal circuit or the memory cell are formed. Next, arsenic ions 16 are ion-implanted over the entire surface as shown in FIG. here,
The ion implantation energy is set to about 50 keV, and the dose is set to about 5 × 10 ¹³ ions / cm ² . Then, heat treatment is performed to form a second N-type low concentration diffusion layer 17.

Here, the regions of the first N-channel MOS transistor and the P-channel MOS transistor which constitute the peripheral circuit are covered with a resist mask 14. As a result, arsenic ions 16 will not be implanted into such regions.

Next, a resist mask 18 is formed as shown in FIG. The polysilicon film 5b is dry-etched using the resist mask 18 as an etching mask. Then, a gate electrode 19 of the P-channel MOS transistor is formed. Further, boron ions 20 are ion-implanted using the resist mask 18 as a mask. Here, the implantation energy is set to about 20 keV, and the dose is set to about 1 × 10 ¹⁵ ions / cm ² . Thus, the gate electrode 1 on the surface of the N well 2
9, a P-type high concentration diffusion layer 21 is formed in a self-aligned manner, and the resist mask 18 is removed. As described above, as shown in FIG. 3C, the LDD structure of the first N-type low concentration diffusion layer 9 and the N-type high concentration diffusion layer 13 formed on the silicon substrate 1 is formed. A first N-channel MOS having a source / drain diffusion layer, a gate insulating film 4, a gate electrode 7, and a spacer insulating film 11
A transistor is formed. Then, the second N-type low-concentration diffusion layer 17 becomes a diffusion layer for source and drain, and a second N-channel MOS transistor having the gate insulating film 4 and the gate electrode 15 is formed. Further, a P-type high-concentration diffusion layer 21 formed in the N-well 2 region on the silicon substrate 1 is a source / drain diffusion layer, and has a P-channel type MO having a gate insulating film 4 and a gate electrode 19.
An S transistor is formed.

In the first embodiment of the present invention, the step of forming the spacer insulating film 11 on the side wall of the gate electrode of the MOS transistor forming the peripheral circuit of the semiconductor device, ie, the first N-channel MOS transistor, A region where an internal circuit or a memory cell is formed is covered with a polysilicon film 5a. Therefore, the film loss due to the etch back of the surface of the element isolation insulating film in this region is completely eliminated. Further, the first N-type low concentration diffusion layer 9 of the first N-channel type MOS transistor and the second N-type low concentration diffusion layer 17 of the second N-channel type MOS transistor are formed independently. For this reason, it becomes possible to change the kind of impurities of the second N-type low concentration diffusion layer 17 or to make the impurity concentration lower than that of the first N-type low concentration diffusion layer.

For this reason, it is easy to manufacture a high-performance MOS transistor for peripheral circuits, for example, having high hot electron resistance, and a high-performance MOS transistor for internal circuits or memory cells, for example, a MOS transistor with low leakage current. Become. Note that the number of photolithography steps in this embodiment is not different from that in the manufacturing steps described in the related art.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a sectional view illustrating a semiconductor device of the present invention in the order of manufacturing steps. Hereinafter, the manufacturing method of the present invention will be described. The structure of the semiconductor device of the present invention is shown in this description. The second embodiment is a case where the present invention is applied to silicidation of a MOS transistor. Here, the same components as those described in the first embodiment are denoted by the same reference numerals.

Since the semiconductor device of the present invention is formed in the same manner as in the first embodiment up to the step of FIG. 2C, the description of the step is omitted.

Subsequently, a refractory metal film is formed on the entire surface and is subjected to a heat treatment to form a first N-type low concentration diffusion layer 9 and an N-type high concentration diffusion layer 9 on the gate electrode 7 as shown in FIG. The concentration diffusion layer 13 and the polysilicon film 5a are silicided. Thus, the gate silicide layer 22 is formed on the gate electrode 7, and the source / drain silicide layer 2 is formed on the first N-type low concentration diffusion layer 9 and the N-type high concentration diffusion layer 13.
3 is formed. At the same time, a silicide film 24 is formed on the polysilicon film 5a. Here, titanium is used as such a silicide material.

Next, in the same manner as described in the first embodiment, as shown in FIG.
Is used as an etching mask. In this dry etching, the silicide film 24 and the polysilicon film 5a are finely processed in order. Thus, the gate electrode 15 and the gate silicide layer 25 of the internal circuit or the second N-channel MOS transistor for the memory cell are formed. At the same time, a polysilicon film 5b and a silicide film 24a are formed.
Then, arsenic ions 16 are ion-implanted over the entire surface. Here, the energy of the ion implantation is set to about 50 keV, and the dose is set to about 1 × 10 ¹³ ions / cm ² . Then, heat treatment is performed to form a second N-type low concentration diffusion layer 17.

Next, as shown in FIG. 4C, a resist mask 18 is formed. Using the resist mask 18 as an etching mask, the polysilicon film 5b and the silicide film 24 are used.
a is dry-etched. And the P channel type M
The gate electrode 19 of the OS transistor and the gate silicide layer 26 are formed.

Further, boron ions 20 are ion-implanted using the resist mask 18 as a mask. Here, the implantation energy is about 20 keV and the dose is 1 × 10 ¹⁵
Each is set to about ion / cm ² . Thus, the P-type high concentration diffusion layer 21 is formed.

As described above, as shown in FIG. 4D, the first N-type low concentration diffusion layer 9 and the N-type high concentration diffusion layer 13 formed on the silicon substrate 1 are formed. A first N-channel MOS transistor including a source / drain diffusion layer having an LDD structure, a source / drain silicide layer 23, a gate insulating film 4, a gate electrode 7, and a gate silicide layer 22 is formed.

The second N-type low-concentration diffusion layer 17 serves as a source / drain diffusion layer and has a gate insulating film 4, a gate electrode 15, and a gate silicide layer 25.
Is formed. Further, the P formed in the N well 2 region on the silicon substrate 1
The high-concentration diffusion layer 21 becomes a diffusion layer for source / drain, and a P-channel MOS transistor having the gate insulating film 4, the gate electrode 19 and the gate silicide layer 26 is formed.

In the second embodiment of the present invention, a MOS transistor constituting a peripheral circuit of a semiconductor device, that is, a gate electrode of a first N-channel MOS transistor, a silicide layer on a source / drain diffusion layer, and another Are formed independently of the MOS transistors of the type.

For this reason, in the step of forming the spacer insulating film 11, the region where the internal circuit or the memory cell is formed is covered with the polysilicon film 5a. Then, the film loss due to the etch back of the surface of the element isolation insulating film in this region is completely eliminated. The first N-type low concentration diffusion layer 9 of the first N-channel type MOS transistor and the second N-type low concentration diffusion layer 17 of the second N-channel type MOS transistor
And is formed independently. For this reason, it becomes possible to change the kind of impurities of the second N-type low concentration diffusion layer 17 or to make the impurity concentration lower than that of the first N-type low concentration diffusion layer.

In this way, the speed of the MOS transistor for the peripheral circuit is increased and the performance is further improved. Then, the MOS transistor for the internal circuit or the memory cell is
A MOS transistor with low leakage current is obtained.

In the embodiment described above, the second N
The case where a P-channel MOS transistor is formed after the formation of a channel MOS transistor is shown.
However, the present invention is not limited to this, and it should be noted that the second N-channel MOS transistor may be formed after the formation of the P-channel MOS transistor.

The present invention can be similarly applied to a semiconductor device composed of N-channel MOS transistors having different structures.

[0058]

As described above, according to the present invention, when different types of N-channel MOS transistors are formed on a semiconductor substrate, the first N-channel type MOS transistor among the different types of N-channel type MOS transistors can be used. After first forming the gate electrode and the diffusion layer for the source / drain, the gate electrode of the second N-channel MOS transistor and the diffusion layer for the source / drain are formed.

Specifically, a gate insulating film is formed in an active region on a semiconductor substrate, and a polysilicon film is deposited so as to cover the gate insulating film. Next, a gate electrode of a first N-channel MOS transistor is formed, and the polysilicon is formed so that the polysilicon film remains in a formation region of the second N-channel MOS transistor or the P-channel MOS transistor. Pattern the film. Then, using the polysilicon film remaining in the formation region of the second N-channel MOS transistor or the P-channel MOS transistor as a mask, ion implantation or silicidation of impurities is performed to form a source / drain region of the first N-channel MOS transistor. To form

The MOS transistor forming the peripheral circuit of the semiconductor device is formed of a first N-channel MOS transistor, and the MOS transistor forming the internal circuit of the semiconductor device or the memory cell is formed of a second N-channel MOS transistor. Are formed independently.

In this manner, the performance of the MOS transistors constituting the peripheral circuit can be easily improved, and the leakage current of the internal circuit, particularly, the MOS transistors constituting the memory cells can be greatly reduced. Then, the retention time of the stored information of the memory cell is greatly increased.

Further, according to the present invention, the MOS transistors constituting the peripheral circuit of the semiconductor device can be salicided independently of the MOS transistors constituting the internal circuit or the memory cell. As described above, according to the present invention, it becomes easy to mix a memory device and a logic device on a semiconductor chip.

As described above, according to the present invention, it becomes very simple to mix a memory device and a logic device on a semiconductor chip, and a system LS having a new function is provided.
I development will be promoted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a sectional view illustrating a second embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a cross-sectional view of a semiconductor device for explaining a conventional technique in a manufacturing process order.

FIG. 6 is a cross-sectional view of a semiconductor device for explaining a conventional technique in a manufacturing process order.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1,101 Silicon substrate 2,102 N well 3,103 Element isolation insulating film 4,104 Gate insulating film 5,5a, 5b Polysilicon film 6,14,18,105,113,116 Resist mask 7,15,19, 106, 107, 108 Gate electrode 8, 109 Phosphorus ion 9 First N-type low concentration diffusion layer 10, 111 Spacer insulating film 11, 11a, 112 Spacer insulating film 12, 16, 114 Arsenic ion 13, 115 N-type high concentration Diffusion layer 17 Second N-type low-concentration diffusion layer 20,117 Boron ions 21,118,118a P-type high-concentration diffusion layer 22,25,26 Gate silicide layer 23 Source / drain silicide layer 24,24a Silicide film 110 N-type Low concentration diffusion layer

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 21/336

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device including a heterogeneous N-channel insulated gate field-effect transistor formed on a semiconductor substrate, the method comprising: The first N
After the gate electrode of the channel-type insulated-gate field-effect transistor and the diffusion layer for the source / drain are formed first, the diffusion of the gate electrode and the source-drain of the second N-channel insulated-gate field-effect transistor are then performed. A method for manufacturing a semiconductor device, comprising forming a layer. 2. A step of forming a gate insulating film in an active region on a semiconductor substrate and depositing a polysilicon film so as to cover the gate insulating film; and a step of forming a gate of the first N-channel insulated gate field effect transistor. Forming an electrode and patterning the polysilicon film such that the polysilicon film remains in a formation region of the second N-channel insulated gate field effect transistor or the P-channel insulated gate field effect transistor; Impurities are ion-implanted using a polysilicon film remaining in a region where the second N-channel insulated gate field-effect transistor or P-channel insulated gate field-effect transistor is formed as a mask, and a spacer insulating film is formed on a side wall of the gate electrode. A first N-channel insulated gate electrode having an LDD structure; 2. The method according to claim 1, further comprising the step of forming source / drain regions of the field effect transistor. 3. A step of forming a gate insulating film in an active region on a semiconductor substrate and depositing a polysilicon film so as to cover the gate insulating film; and a step of forming a gate of the first N-channel insulated gate field effect transistor. Forming an electrode and patterning the polysilicon film such that the polysilicon film remains in a formation region of the second N-channel insulated gate field effect transistor or the P-channel insulated gate field effect transistor; Impurities are ion-implanted using a polysilicon film remaining in a region where the second N-channel insulated gate field-effect transistor or P-channel insulated gate field-effect transistor is formed as a mask, and a spacer insulating film is formed on a side wall of the gate electrode. And said first N-channel insulated gate field effect transistor. Forming a source / drain diffusion layer; and forming the source / drain diffusion layer on the gate electrode, the source / drain diffusion layer and the second N-channel insulated gate field-effect transistor or the P-channel insulated gate field-effect transistor. 2. The method according to claim 1, further comprising the step of selectively forming a silicide layer on the polysilicon film remaining in the formation region. 4. A method of patterning a polysilicon film or a silicide layer on the polysilicon film remaining in a region where the second N-channel insulated gate field effect transistor or the P-channel insulated gate field effect transistor is formed. Forming a gate electrode of the N-channel insulated gate field effect transistor, and forming a source / drain diffusion layer of the second N-channel insulated gate field effect transistor by ion-implanting impurities again. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 5. The semiconductor device according to claim 1, wherein the peripheral circuit of the semiconductor device comprises a first N-channel insulated gate field-effect transistor, and an internal circuit of the semiconductor device comprises: A semiconductor device comprising the second N-channel insulated gate field effect transistor according to any one of the preceding claims.