JPH10275916A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a transistor having an excellent electrical characteristic, by eliminating surface contamination and lattice defects from the channel area of a semiconductor layer. SOLUTION: After a gate electrode 11 formed on a substrate 10 is covered with a gate insulating film 12, a-Si 13a, and an SiO2 protective film 14 which are successively formed on the substrate 10, and the protective film 14 is formed in the same pattern as that of the electrode 11, p-Si 13 is formed by crystallizing the a-Si 13a into a polycrystalline state by excimer laser annealing(ELA). Since the upper and the lower surfaces of the p-Si 13 are in contact with the continuously formed insulating layers in a channel area, the surface contamination of the channel area is prevented and the shift of a flat band voltage caused by impurity ions can be prevented. At the same time, since lattice defects are reduced from both the upper and the lower surfaces of the p-Si 13, a transistor which has smaller number of traps and a high on/off ratio can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, to a liquid crystal display (LCD).
The present invention relates to a method of manufacturing a peripheral drive circuit integrated type LCD in which a thin film transistor (TFT) using a polycrystalline semiconductor layer is formed in a display portion and a peripheral portion.

[0002]

2. Description of the Related Art The technique of forming a semiconductor film on a substrate is used to increase the degree of integration of an integrated circuit to increase the capacity, or to form a matrix pixel on one of a pair of substrates sandwiching a liquid crystal. TFT to be the switching element of the unit
The development of mass production of active matrix type LCDs capable of displaying high-definition moving images has been carried out.

In particular, MOSF fabricated on a silicon substrate
If TFTs having characteristics close to ET can be formed on an insulating substrate, not only switching elements in a matrix pixel portion of an LCD, but also a CMOS formed in the periphery to supply a desired drive signal voltage to the matrix pixel portion Peripheral drive circuit can be integrally formed, and mass production of a so-called driver built-in LCD can be performed.

[0004] The LCD with a built-in driver eliminates the need for externally attaching a driver element to the liquid crystal panel.
The number of processes can be reduced and the frame can be narrowed. In particular, narrowing the frame can reduce the size of the product itself in applications such as a portable information terminal or a monitor of a handy video camera in recent years. As such a TFT, a polycrystalline semiconductor in which a large number of single crystal grains (grains) having a grain size of several hundreds to several thousands of mm are in contact with each other is used for a channel layer so that a driver portion can be formed. It can be an applicable high-speed element. In particular, polycrystalline silicon or polysilicon (p
-Si) has a mobility of about several tens to several hundreds cm2 / Vs, and is two orders of magnitude higher than amorphous silicon, that is, amorphous silicon (a-Si). Therefore, N-chT
By forming the FT and the P-ch TFT, a CMOS having a sufficient speed as an LCD driver is formed.

[0005] In particular, the applicant has previously set a process temperature of at most about 600 ° C. or less in order to reduce the cost, and as a substrate, it is possible to use an inexpensive alkali-free glass substrate or the like having low heat resistance. Has been developed. Such a manufacturing process of the p-Si TFT LCD in which the entire process is suppressed to a temperature lower than the limit temperature of the heat resistance of the substrate is called a low temperature process.

FIG. 9 shows a sectional structure of such a p-Si TFT. The left side of the figure is an N-ch TFT, and the right side is P
-Ch TFT. A gate electrode (51) made of a metal such as Cr is formed on a substrate (50), and a gate insulating film (52) made of SiNx or / and SiO2 is formed so as to cover the gate electrode (51). On the gate insulating film (52), p-Si (53) is formed. p-Si
(53) uses an implantation stopper (54) such as SiO2 patterned on the gate electrode (51) to form an N-type impurity at a low concentration in the N-ch (N-). 2.) Lightly doped (LD) regions (LD) and source and drain regions (S, D) containing N-type impurities at a high concentration are formed outside thereof. In the P-ch, the (P +) source and drain regions (S,
D) is formed. Immediately below the injection stopper (54) in each of the N-ch and the P-ch is an intrinsic layer containing substantially no impurities, and serves as a channel region (CH). SiNx covering these p-Si (53)
A source electrode (56) and a drain electrode (57) made of metal are formed on the interlayer insulating film (55), and each is opened on the interlayer insulating film (55). Via the contact hole provided, the source region (S) and the drain region (D). Although omitted here, in the pixel portion, further,
A display electrode for driving a liquid crystal made of a transparent conductive film such as ITO (indium tin oxide) is formed on the interlayer insulating film covering the source and drain electrodes (56, 57), and is connected to the source electrode (56).

In the N-ch, a structure in which an LD region (LD) is formed between a source / drain region (S, D) and a channel region (CH) is formed by an LDD (lightly dope).
peddrain). In an LCD, such an LDD structure is adopted for the purpose of suppressing off current. Further, the channel region (CH) may be of a channel-doped type by injecting impurities having the opposite conductivity types before injecting the above-described impurities in advance.

The manufacture of this TFT is performed as follows.
First, after a gate electrode (51) is formed by sputtering and etching of Cr, SiNx, SiO2 and a-Si, which become a gate insulating film (52), are continuously formed by plasma CVD without breaking the vacuum. After that, a-Si is subjected to laser annealing to be polycrystallized, thereby forming p-Si (53). Furthermore, p-
After forming SiO2 on the Si (53), a positive resist is formed thereon, and this is irradiated with light from the substrate (50) side, that is, by so-called backside exposure, to form the gate electrode (51).
The pattern shape is inverted to expose. Subsequently, after developing the resist, the insulating film is etched using the resist as a mask to form the implantation stopper (54) in the same shape as the gate electrode (51). Then, using the implantation stopper (54) (resist) as a mask, phosphorus (P)
Or the like, which is lightly doped with impurity ions exhibiting N-type conductivity, such as a channel region (C) immediately below the implantation stopper (54).
H) and LD regions (LD) are formed on both sides thereof. Thereafter, a resist is formed in a shape larger than the implantation stopper (54), and using this as a mask, N-type impurity ions are doped at a high concentration to form source and drain regions (S, D). Accordingly, with respect to the N-ch, the LDD in which the LD region (LD) is interposed between the channel region (CH) and the source and drain regions (S, D)
The structure is completed.

Similarly, the P-ch reflects the shape of the gate electrode (51) and reflects the shape of the channel region (CH).
, Source and drain regions (S, D) doped with a P-type impurity at a high concentration are formed. However, the P-ch does not employ the LDD structure. Thereafter, an interlayer insulating film (55) covering the N-ch and P-ch TFTs is formed, a contact hole (CT) is opened, and a source and drain electrode ( 56, 57) are formed and connected to the source and drain regions (S, D) via the contact holes (CT), respectively.

[0010]

The p-Si film is made of aS
i is formed by laser annealing,
After the -Si film is formed, the vacuum is broken. At this time, a-S
When impurities such as Na are adsorbed on the film surface of i or p-Si, and these impurity ions are taken into the device,
As a movable ion, the flat band voltage is changed, and the threshold value is changed. Also, since the p-Si (53) and the underlying gate insulating film (52) are formed by continuous CVD, the lattice condition at the interface is relatively good.
Since the upper surface of p-Si (53) is exposed after film formation, it has lattice defects and a high interface state density.
These interface states generate energy levels in the band gap and become traps, which take in electrons in the conduction band and emit them to the valence band, and also absorb electrons in the valence band to the conduction band. And causes a problem of lowering the on / off ratio.

The present invention has been made to solve these problems, and has devised a method of manufacturing an element exhibiting good electric characteristics.

[0012]

According to the present invention, there is provided a method of manufacturing a semiconductor device using at least a part of a semiconductor layer as an active layer, wherein the insulating layer is formed on the semiconductor layer continuously with the semiconductor layer. Is formed only on the active layer region,
This is a configuration in which annealing is performed. This prevents the semiconductor layer, particularly the active layer region, from being exposed and contaminated, and prevents the occurrence of lattice defects at the interface and the generation of interface states, thereby producing a semiconductor device having excellent characteristics. .

In a method for manufacturing a semiconductor device in which an electrode is formed on a substrate and a semiconductor layer including an area on the electrode sandwiching an insulating layer as an active layer, a step of forming the electrode on the substrate; An insulating layer covering the electrode, a semiconductor layer on the insulating layer, and a step of forming an insulating protective film on the semiconductor layer; and forming the insulating protective film on a region to be an active layer of the semiconductor layer. And a step of annealing the semiconductor layer formed on a region where the insulating protective film is to be an active layer.

Thus, the semiconductor layer is continuously formed on both the upper and lower insulating films with respect to the region to be the active layer, thereby preventing the semiconductor layer from being contaminated, In addition, good electrical characteristics can be obtained without lattice defects on the front and back surfaces of the semiconductor layer. Also,
Forming a first conductive layer on a substrate, forming a first electrode by patterning the first conductive layer, and forming a first insulating layer covering the first electrode; Forming an amorphous semiconductor layer on the first insulating layer and an insulating protective film on the amorphous semiconductor layer; and patterning the insulating protective film to form the amorphous semiconductor layer. Leaving on an active layer region above the first electrode, and performing crystallization annealing on the amorphous semiconductor layer in which the insulating protective film is left on the active layer region. Forming a polycrystalline semiconductor layer, forming a region containing impurities on both sides of the active layer of the polycrystalline semiconductor layer, covering the polycrystalline semiconductor layer, and Forming a second insulating layer having an opening on the region containing the impurity; Forming a second conductive layer on the second insulating layer, and patterning the second conductive layer to remove the impurities of the polycrystalline semiconductor layer through the opening. And forming a second electrode connected to the region containing the semiconductor device.

Thus, since the active layer region of the polycrystalline semiconductor layer is in contact with the upper and lower surfaces by the insulating films formed continuously, contamination or lattice defects are prevented, and the electrical characteristics are improved. You. A step of forming a first conductive layer on the substrate; a step of forming a first electrode by patterning the first conductive layer; and a first insulating layer covering the first electrode. Forming an amorphous semiconductor layer on the first insulating layer, and a material film serving as an insulating protective film on the amorphous semiconductor layer; and patterning the material film to form the amorphous film. Forming the insulating protective film in a region of the amorphous semiconductor layer that is to be an active layer above the first electrode; and performing crystallization annealing on the amorphous semiconductor layer on which the insulating protective film is formed. Forming a polycrystalline semiconductor layer, forming a material film to be an insulating injection blocking film on the polycrystalline semiconductor layer on which the insulating protective film is formed, Patterning the insulating film on the polycrystalline semiconductor layer on which the protective film is formed. Forming an insulating injection-blocking film having substantially the same shape as the protective film, and performing ion implantation of impurities into the polycrystalline semiconductor layer using at least the injection-blocking film as a mask. Forming a region containing impurities on both sides of the active layer, and covering the polycrystalline semiconductor layer,
A step of forming a second insulating layer having an opening on a region containing the impurity of the polycrystalline semiconductor layer; and a step of forming a second conductive layer on the second insulating layer. Forming a second electrode connected to the region containing the impurity of the polycrystalline semiconductor layer through the opening by patterning the second conductive layer. This is a method for manufacturing a semiconductor device.

Thus, since the active layer region of the polycrystalline semiconductor layer is in contact with the upper and lower surfaces by the insulating films formed continuously, contamination or lattice defects are prevented, and electric characteristics are improved. You. In particular, the insulating protective film is previously formed at least in the electrically active direction larger than the insulating injection blocking film, and at the same time as forming the injection blocking film, the insulating protective film is formed of the injection blocking film. A method for manufacturing a semiconductor device, the method comprising re-forming to the same size as that of a semiconductor device.

As a result, the region containing the impurity defined by the edge of the injection blocking film is prevented from being separated from the active layer region protected by the protective film, and the electrical characteristics are improved. In particular, the insulating protective film, and the insulating injection blocking film, the step of forming a resist on each material film, and by irradiating light from the back surface of the substrate, the first of the resist A step of exposing a region other than the first electrode upper region to a region other than the first electrode upper region so as to be soluble in a developing solution; a step of developing the resist; Removing a region where the resist is not formed by etching a material film, and irradiating light from the back surface of the substrate to sensitize the resist on the material film serving as the insulating protective film. The light intensity and / or irradiation time in the step of performing the light irradiation may be different from the step of irradiating light from the back surface of the substrate in order to expose the resist on the material film to be the insulating injection blocking film. That the intensity and / or irradiation time of light, a method of manufacturing a semiconductor device consists in weak or / and short.

Thus, the protection film is once formed larger than the injection blocking film, so that the active layer region protected by the protection film is not separated from the region containing impurities.

[0019]

1 to 8 are sectional views showing steps of a manufacturing method according to an embodiment of the present invention. These figures show N-ch. First, in FIG. 1, a gate electrode (11) is formed by depositing a Cr film on a substrate (10) and etching it.
The gate electrode (11) is formed integrally with a gate line serving as a scanning signal supply line.

In FIG. 2, a gate insulating film (12) made of SiNx and SiO2 is formed on the entire surface covering the gate electrode (11) by CVD, and then continuously formed with C.
The amorphous silicon (a-Si) (13
a) and a protective film (14) made of SiO2 is formed without breaking vacuum. In FIG. 3, a protective film (14) is formed in the same shape as the gate electrode (11) by using a backside exposure method. That is, a positive resist is applied to the protective film (14), and the coated resist is irradiated with light from below the substrate (10) to transfer the shadow of the gate electrode (11).
1) Exposing the area other than 1). After the development, the SiO2 is etched using the resist as a mask, thereby leaving the protective film (14) only above the gate electrode (11) and removing other portions. In this step, as described later, exposure is performed with relatively weak light or for a relatively short period of time, so that the shadow region of the gate electrode (11) is relatively large exposed. That is, the protection film (14) is formed larger than the injection stopper (15) as described later.

In FIG. 4, excimer laser annealing (ELA) is performed in a state where the protective film (14) is formed only above the gate electrode (11), so that the a-Si
(13a) is crystallized to form p-Si (13). In this step, the substrate to be processed is taken out into the atmosphere and transported to the ELA step.
3) The area covered with the protective film (14) on the surface is prevented from being contaminated in the atmosphere. For this reason, the problem that the impurity ions are present in the transistor element, the flat band voltage is changed by the potential generated by these charges, and the threshold value is moved in parallel is eliminated. Also, p-Si (1
Since 3) and the protective film (14) are formed by continuous CVD, the number of lattice defects at the interface between both layers is small, and the interface state density is reduced. Therefore, electrical characteristics with few traps and a high on / off ratio can be obtained.

The protective film (14) has a thickness of about 520 °.
And the reflectance of the laser beam at the time of ELA on the surface of p-Si (13) is made sufficiently low. SiO2, which is the protective film (14), has a larger refractive index than air and smaller than a-Si (13a). Accordingly, the amount of light reflected on the surface of the protective film (14) is reduced, and the light is reflected a plurality of times between the upper surface and the lower surface in the protective film (14). At this time, when the wavelength of the laser beam is λ, the refractive index of SiO 2 is n, and the thickness of the protective film is d,

[0023]

(Equation 1)

The following equation holds. If λ is 308 nm and n is 1.46, d = 527 nm is obtained. Therefore, by setting the film thickness of the protective film (14) in this way, the reflected lights interfere with each other and strengthen each other with the interface between the protective film (14) and the a-Si (13a) as a fixed end. The reflectivity on the surface of SiO2, which is the protective film (14), is p-Si
(13) Since it is smaller than the reflectance at the surface, p-Si
By forming a protective film (14) on (13), p-
The ratio of light irradiated to Si (13) is increased.

Conventionally, when laser annealing in the form of a line or a sheet beam is performed in order to crystallize a-Si in a state where the gate electrode (11) and its line are present in the lower layer, the given energy becomes thermal conductivity. Gate electrode (11) and the other region along the line,
There is a problem that the applied energy is reduced only on the gate electrode (11) and its line, and the grain size of p-Si becomes smaller than in other regions. Therefore, as in the present invention, by forming the protective film (14) having an antireflection effect on the gate electrode (11) and its line, the absorption of the laser beam by the protective film (14) is increased and the gate electrode ( 11) and the diffusion of energy along the line acts in a direction that is exactly offset, and uniform laser annealing is performed over the entire surface.

In this laser annealing, a-Si
Although a large amount of hydrogen contained in (13a) is released, hydrogen escapes from the side of the protective film (14) because the protective film (14) is formed only on the channel region (CH). That is, when the protective film (14) is provided on the entire surface,
When hydrogen is released, it jumps into the protective film (14), and p-
The problem that a lattice defect occurs again at a favorable interface between the Si (13) and the protective film (14) is prevented.

In FIG. 5, a protective film (14) is formed by depositing SiO 2 on the substrate on which p-Si (13) is formed and etching the SiO 2 by using the same backside exposure method as in the process of FIG. As in the case of (1), an injection stopper (15) is formed above the gate electrode (11). The exposure at this time is shown in FIG.
The process is performed in a stronger light or for a longer time than in the step described above, and the shadow of the gate electrode (11) is exposed to a smaller size by utilizing the light wraparound effect or the like. That is, the injection stopper (15) is formed smaller than the protective film (14). When the implantation stopper (15) is etched, the protruding portion (E) of the same protective film (14) made of SiO2 is also etched, so that the protection film (14) is etched into the implantation stopper (15).
Reformed into the same shape as

Then, using this implantation stopper (15) as a mask, ion implantation of phosphorus (P) exhibiting N-type conductivity into p-Si (13) is performed at a low dose of about 10.sup.13. The region other than the implantation stopper (15) is lightly doped (N-). At this time, a region immediately below the injection stopper (15), that is, a region immediately above the gate electrode (11) is maintained in the intrinsic layer and becomes a channel region (CH) of the TFT. The resist when the implantation stopper (15) is etched may be left at the time of ion implantation, and may be peeled off after the ion implantation.

At this time, both ends of the channel region (CH) protected by the protective film (14) before being re-etched protrude from the re-etched injection stopper (15) and the protective film (14). Therefore, the low-concentration region (N−) whose edge is defined by the edge of the injection stopper (15) and the protective film (14) is formed without being separated from the channel region (CH) having good film quality.

Usually, in the channel area (CH),
Movable ions and interface states affect threshold characteristics. In the LD region (LD) and the source and drain regions (S, D), the concentration of impurity ions has a large effect on electric resistance. Therefore, it is possible to obtain an element having good electric characteristics by preventing the existence of a region which is not protected by the protective film (14) at the end portion in the channel region (CH) and affecting the electric characteristics. .

In FIG. 6, a resist (R) larger than the gate electrode (11) at least in the channel length direction is formed, and ion implantation of phosphorus (P) into p-Si (13) is performed by using this as a mask. Is performed at a high dose of about 15 to dope the region other than the resist (R) at a high concentration (N +). At this time, the low concentration area (N−) and the channel area (C
H) is maintained. As a result, an LDD structure is formed in which high-concentration source and drain regions (S, D) exist on both sides of the channel region (CH) with the low-concentration LD region (LD) interposed therebetween.

After the removal of the resist (R), activation annealing such as heating or laser irradiation is performed for the purpose of recovering the crystallinity of the p-Si film doped with impurity ions and replacing the lattice of the impurities. Subsequently, the p-Si
By etching (14), only the necessary area of the TFT is left to form an island.

In FIG. 7, an interlayer insulating layer (16) made of SiNx or the like is formed, and the source and drain regions (S,
A contact hole (CT) is formed by removing a portion corresponding to D) by etching, and p-Si (13) is formed.
Is partially exposed. In FIG. 8, a source electrode (17) connected to a source region (S) through a contact hole (CT) and a drain region (D) are formed by depositing Al / Mo or the like and etching the film. The drain electrode (18) connected to the TFT is formed, and the TFT is completed.

[0034]

As is apparent from the above description, according to the present invention, in the manufacture of a semiconductor device having an electrode and a semiconductor layer formed on a substrate, an insulating film formed continuously on both upper and lower surfaces of a semiconductor layer to be an active layer. With this structure, the lattice condition at the interface between the semiconductor layer and the insulating film is improved, and the active layer of the semiconductor layer is not exposed, so that surface contamination is prevented and electrical characteristics are improved. A good semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 substrate 11 gate electrode 12 gate insulating film 13 p-Si 14 protective film 15 injection stopper 16 interlayer insulating layer 17 source electrode 18 drain electrode

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device using at least a part of a semiconductor layer as an active layer, wherein an insulating protective film formed continuously with the semiconductor layer on the semiconductor layer is formed on the active layer region. A method of manufacturing a semiconductor device, wherein the method comprises the steps of: 2. A method for manufacturing a semiconductor device in which an electrode is formed on a substrate and a semiconductor layer including an area on the electrode sandwiching an insulating layer as an active layer is formed. An insulating layer covering the electrode, a semiconductor layer on the insulating layer, and
A step of forming an insulating protective film on the semiconductor layer; a step of leaving the insulating protective film only on a region of the semiconductor layer to be an active layer; and a region of the insulating protective film to be an active layer. Annealing the semiconductor layer formed thereon; and a method of manufacturing a semiconductor device. 3. a step of forming a first conductive layer on a substrate; a step of forming a first electrode by patterning the first conductive layer; and a step of forming a first electrode covering the first electrode. Forming an amorphous semiconductor layer on the first insulating layer, the first insulating layer, and an insulating protective film on the amorphous semiconductor layer; and patterning the insulating protective film. Leaving the amorphous semiconductor layer above the first electrode on a region to be an active layer; and crystallizing the amorphous semiconductor layer with the insulating protective film left in the region to be an active layer. Forming a polycrystalline semiconductor layer by annealing, forming regions containing impurities on both sides of the active layer of the polycrystalline semiconductor layer, covering the polycrystalline semiconductor layer, and A polycrystalline semiconductor layer having an opening on a region containing the impurity; Forming a second conductive layer on the second insulating layer; and patterning the second conductive layer to form the polycrystal through the opening. Forming a second electrode connected to the impurity-containing region of the semiconductor layer. 4. A step of forming a first conductive layer on a substrate, a step of forming a first electrode by patterning the first conductive layer, and a step of covering the first electrode. Forming an amorphous semiconductor layer on the first insulating layer, the first insulating layer, and a material film serving as an insulating protective film on the amorphous semiconductor layer; and patterning the material film. Forming the insulating protective film in a region of the amorphous semiconductor layer to be an active layer above the first electrode; and forming a crystal on the amorphous semiconductor layer on which the insulating protective film is formed. Forming a polycrystalline semiconductor layer by subjecting the polycrystalline semiconductor layer to a polycrystalline semiconductor layer on which the insulating protective film is formed,
Forming a material film to be an insulating injection blocking film; and forming an insulating film having substantially the same shape as the insulating protective film on the polycrystalline semiconductor layer on which the protective film is formed by patterning the material film. Forming an implantation blocking film, and performing ion implantation of impurities into the polycrystalline semiconductor layer using at least the implantation blocking film as a mask, so that impurities are contained on both sides of the active layer of the polycrystalline semiconductor layer. Forming a region, forming a second insulating layer that covers the polycrystalline semiconductor layer and has an opening on a region of the polycrystalline semiconductor layer containing the impurity; and Forming a second conductive layer on an insulating layer; and patterning the second conductive layer to form a second conductive layer connected to the impurity-containing region of the polycrystalline semiconductor layer through the opening. The method of manufacturing a semiconductor device characterized by having the steps of forming the electrode. 5. The insulating protective film is formed beforehand larger than the insulating injection blocking film at least in the electrically active direction, and at the same time as forming the injection blocking film, the insulating protective film is 5. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed again to have the same size as the injection blocking film. 6. The insulating protective film and the insulating injection blocking film are formed by forming a resist on each material film and irradiating light from the back surface of the substrate to form the resist. Exposing a region other than the first electrode upper region to a region other than the first electrode upper region so as to be soluble in a developing solution; developing the resist; Removing the region where the resist is not formed by etching the material film as a mask, from the back surface of the substrate to expose the resist on the material film serving as the insulating protective film. The intensity of light and / or the irradiation time in the step of irradiating light is determined by the step of irradiating light from the back surface of the substrate in order to expose the resist on the material film serving as the insulating injection blocking film. Light intensity and / or irradiation time of the a weak and / or shorter method according to claim 5, wherein.