JPH10276077A - Reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the reset circuit to have provision for controlled systems where a time from application of power till clearing of a reset state is different. SOLUTION: Any of four kinds of delay signals outputted from four specific D flip-flop circuits being a component of a delay circuit 3 is selectively outputted through the combination of selection signals C0, C1. Thus, the user of the reset circuit generates an intended delay signal independently of the manufacturer and the reset circuit easily has provision for controlled systems where a time from application of power to clearance of a reset state differs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a reset circuit suitable for reset release of different controlled systems.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional reset circuit, which is integrated. In FIG. 3, (1)
Is a comparator, the power supply voltage V1 of the reset circuit is applied to the + terminal, and the reference voltage Vref is applied to the-terminal. (2) is an oscillation circuit that operates in response to the comparison output of the comparator (1). That is, in the range of the power supply voltage V1 <the reference voltage Vref after the power is turned on, since the comparison output of the comparator (1) is at the low level,
The oscillation circuit (2) is in a state where the oscillation operation is stopped. On the other hand, in the range of the power supply voltage V1> the reference voltage Vref, the comparison output of the comparator (1) is inverted to a high level.
The oscillating circuit (2) is supplied with the high level and starts oscillating. Since the power supply voltage V1 is also supplied to the oscillation circuit (2), the reference voltage Vref is set so that the comparison output of the comparator (1) does not become a high level when the oscillation circuit (2) cannot oscillate stably. You. Oscillation circuit (2)
Any of an RC oscillation circuit, a crystal oscillation circuit, a ceramic oscillation circuit, and the like may be applied. (3) is a delay circuit that generates a plurality of delay signals obtained by delaying the oscillation signal of the oscillation circuit (2) by different times (for example, four types) and selectively outputs any one of the plurality of delay signals. It is. (4)
Is an output circuit for amplifying the delay signal of the delay circuit (3) to a level at which a controlled system such as a microcomputer can be reset. The comparator (1) and the delay circuit (3) are constituted by MOS transistors, and the oscillation circuit (2) and the output circuit (4) are constituted by bipolar transistors. In addition, the controlled system
The reset may be released by the first output change of the output circuit (4), or the reset may be released by receiving the output change of the output circuit (4) for a predetermined time.

FIG. 4 is a block diagram showing a specific example of the delay circuit (3). FIG. 4 shows n D-type flip-flops (5
-1) to (5-n) are cascaded.
Specifically, D (data input) of each D-type flip-flop
The terminal and the * Q (inverted output) terminal are short-circuited, and the * Q terminal of the preceding D-type flip-flop is connected to the CK (clock input) terminal of the subsequent D-type flip-flop. That is, each D-type flip-flop (5-1) to
(5-n) operates as a 1/2 frequency dividing circuit. Further, the Q (output) terminals of the specific four D-type flip-flops are derived inside the integrated circuit, and the output circuit (4) of the next stage is provided.
Is connected by input and metal switching. For example, if the oscillation cycle of the oscillation circuit (2) is set to 0.78 msec,
From the Q terminals of the specific four D-type flip-flops, the oscillation signal is divided by a predetermined frequency to 25 msec, 50 msec,
A delay signal of 100 msec and 200 msec is output, and one of the delay signals is amplified and output from the output circuit (4) via the metal wiring.

The controlled system has a different time from power-on to reset release depending on its configuration. Therefore, four types of delay signals are created by one reset circuit, that is, one reset circuit can cope with a plurality of controlled systems.

[0005]

However, in order to handle a plurality of controlled systems with one reset circuit, metal switching is indispensable. Therefore, on the manufacturing side of the reset circuit (integrated circuit), different models must be manufactured in accordance with the delay time of the delay signal, so that there is a problem that the manufacturing cost is increased and the delivery time is lengthened. On the use side, there is a problem that the disadvantage of manufacturing side is that the individual reset circuit must be used according to the delay time.

SUMMARY OF THE INVENTION It is an object of the present invention to enable a user of a reset circuit to arbitrarily select a delay time of a delay signal on the spot.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problem. After power-on, a plurality of delay signals obtained by delaying oscillation signals of an oscillation circuit by different times are created. And a delay circuit for selecting and outputting any one of the plurality of delay signals, and supplying any one of the plurality of delay signals to the controlled system, thereby causing the controlled system to output the delay signal. Wherein the delay circuit has a selection logic circuit for selecting and outputting one of the plurality of delay signals in response to a selection signal in response to a level change of the reset circuit. It is characterized by.

Further, the reset circuit is integrated, and a terminal for supplying the selection signal is derived.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a reset circuit of the present invention, which is assumed to be integrated. In the configuration of FIG. 1, the same elements as those of FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. Unlike the delay circuit (3) of FIG. 3, the delay circuit (3) of FIG. 1 does not have a wiring for metal switching.

In FIG. 1, reference numeral (6) denotes a selection logic circuit, which outputs from four specific D-type flip-flops constituting a delay circuit (3) in accordance with a combination of two-bit selection signals C0 and C1. Four types of delayed signals DLY1 to DLY1
DLY4 is selectively output and supplied to an output circuit (4). FIG. 2 is a specific circuit diagram of the selection logic circuit (6).

In FIG. 2, one input terminal of an AND gate (7) is connected to a selection signal C0 via an inverter (11).
And the other input terminal is connected to the selection signal C1. One input terminal of the AND gate (8) is a selection signal C
0 and the other input terminal is connected to the selection signal C1 via the inverter (12). AND gate (9)
Has one input terminal connected to the selection signal C0 and the other input terminal connected to the selection signal C1. AND gate (1
0) is connected to a selection signal C0 via an inverter (11), and the other input terminal is connected to a selection signal C1 via an inverter (12). That is, when the selection signals C0 and C1 are set to L (low level) and H (high level), respectively, the AND gate (7) opens, and when the selection signals C0 and C1 are set to H and L, respectively, the AND gate (8) is opened. When the selection signal C0 and C1 are both set to H, the AND gate (9) is opened. When the selection signals C0 and C1 are both set to L, the AND gate (10) is opened.

One input terminal of the NAND gate (13) is connected to the output terminal of the AND gate (7), the other input terminal is connected to the delay signal DLY1 (delay time: 25 msec), and the NAND gate (13) is connected to the AND gate. Only when the output of the gate (7) is H, the delay signal DLY1 is inverted and output. One input terminal of the NAND gate (14) is AN
The other input terminal is connected to the delay signal DLY2 (delay time 50 msec), and the NAND gate (14) is connected to the output terminal of the D gate (8) only when the output of the AND gate (8) is H. Is inverted. NA
One input terminal of the ND gate (15) is connected to the output terminal of the AND gate (9), and the other input terminal is connected to the delay signal DLY3 (delay time 100 msec).
The output of the AND gate (15) is H
The delay signal DLY3 is inverted and output only when. One input terminal of the NAND gate (16) is an AND gate (10)
And the other input terminal is a delay signal DL
Y4 (delay time 200 msec), connected to NAND
The gate (16) inverts and outputs the delay signal DLY4 only when the output of the AND gate (10) is H. The four input terminals of the NAND gate (17) are connected to the NAND gates (13) to (1).
6), and the output terminal is connected to the input terminal of the next stage output circuit (4).

For example, when the delay signal DLY2 is to be selectively output from the selection logic circuit (6), the selection signals C0 and C1 may be set to H and L, respectively. In this case, the output of the AND gate (8) is H, and the AND gates (7) (9) (10)
Is low, the NAND gate (14) outputs the delay signal D
LY2 is inverted and output, and NAND gates (13) and (15)
The output of (16) becomes H, whereby the delay signal DLY2 is output from the NAND gate (17).

As described above, the user can arbitrarily combine the selection signals C0 and C1 on the spot to create delay signals having different delay times. Therefore, the problems such as the manufacturing cost and the delivery date which have occurred conventionally can be solved, and a single reset circuit can easily cope with a plurality of controlled systems having different times from power-on to reset release.

[0015]

According to the present invention, the use side of the reset circuit arbitrarily selects the selection signals C0 and C1 without depending on the manufacturing side.
, It is possible to create delayed signals having different delay times. Therefore, it is possible to solve the problems such as the manufacturing cost and the delivery date which have conventionally occurred, and it is possible to obtain an advantage that a single reset circuit can easily cope with a plurality of controlled systems having different times from power-on to reset release.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a reset circuit according to the present invention.

FIG. 2 is a circuit block diagram showing a specific circuit of the selection logic circuit of FIG.

FIG. 3 is a block diagram showing a conventional reset circuit.

FIG. 4 is a circuit block diagram illustrating a specific circuit of the delay circuit of FIG. 3;

[Explanation of symbols]

 (2) Oscillation circuit (3) Delay circuit (6) Selection logic circuit (7) to (10) AND gate (11) (12) Inverter (13) to (17) NAND gate

Claims (2)

[Claims] And a delay circuit for selectively outputting one of the plurality of delay signals while generating a plurality of delay signals obtained by delaying an oscillation signal of the oscillation circuit by different times after power-on. A reset circuit configured to supply the control system with any one of the plurality of delay signals to change the controlled system from a reset state to a reset release state in response to a level change of the delay signal; And a selection logic circuit for selecting and outputting any one of the plurality of delay signals in response to a selection signal. 2. The reset circuit according to claim 1, wherein said reset circuit is integrated, and a terminal for supplying said selection signal is derived.