JPH10276080A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase of clock skewness without substantially changing circuit configurationand a circuit scale and to provide a highly reliable semiconductor device without malfunctions by laying out the output wiring of a buffer circuit so as to make the delay of clock signals larger on a front stage side than on the rear stage side of a logic circuit and connecting it to clock input. SOLUTION: A shift register circuit 100 sequentially sends data based on data input DA from an FF circuit 11 on the front stage side to the FF circuit 14 on the rear stage side every time the rising edge of the clock signals CK is inputted. Along with that, the Q1 output of the FF circuit 11 is supplied as the data of a least significant bit and the Q4 output of the FF circuit 14 is supplied as a most significant bit to the other circuit. That is, since the delay is enlarged as separating from the buffer circuit 10 and the clock signals CK are sequentially inputted first from the rear stage side to the C input of the respective FF circuits 11-14, erroneous data fetching in a synchronization circuit or the malfunctions caused by the erroneous data fetching in the synchronization circuit are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
More specifically, the present invention relates to a layout and wiring (layout) of a synchronous circuit used in a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device having a logic circuit such as CMOS or Bi-CMOS, a plurality of flip-flop circuits (hereinafter referred to as "FF circuits") such as a shift register circuit whose circuit diagram is shown in FIG. Abbreviated)
In many cases, a synchronous circuit is used in which a plurality of FF circuits operate at substantially the same timing by supplying a common clock signal to a circuit having the same.

The shift register circuit 300 shown in FIG. 3 will be described. In the following description, the clock input of the FF circuit is referred to as C input, the data input is referred to as D input, the non-inverted output is referred to as Q output, and the inverted output is referred to as QB output. The shift register circuit 300 has a clock signal CI
Buffer circuit 10 connected to N signal and outputting CK signal
And D-type FF circuits 11 to 14 to which a clock signal CK is commonly connected to the C input of each FF circuit. The data input DA is input to the D input of the FF circuit 11, the Q output is input to the D input of the FF circuit 12, the Q output is input to the D input of the FF circuit 13, and the Q output is input to the FF circuit 13. 14 D inputs.

With such a configuration, the clock signal CK
Each time a rising edge of the data is input, the data of each FF circuit is sent from the preceding FF circuit to the following FF circuit. Further, when this shift register circuit is formed in a semiconductor device, the operation of the gate circuits constituting each FF circuit has not been so fast so far. Therefore, as shown in FIG. It should have been wired. That is, since the load of the FF circuit or the like commonly connected to the output of the buffer circuit 10 is too large and the clock signal is too delayed, the data shift operation of the shift register circuit is extremely slower than the operation of other circuits not shown. It would have been better not to be.

However, in recent semiconductor devices using a fine process called a submicron, the operation of the gate circuit constituting the FF circuit has been accelerated and the wiring resistance has been increased. Each FF
Depending on the relationship with the input threshold voltage of the circuit, the clock signal of the subsequent FF circuit may be input later than the clock signal of the preceding FF circuit. In such a case, erroneous data is fetched by the FF circuit of the preceding stage fetching the data after the change of the FF circuit of the preceding stage first, and the other circuit using this data may malfunction. . Therefore, in order to make such a malfunction unlikely to occur, the circuit shown in FIG. 4 and the clock wiring are arranged in a tree structure have been implemented.

The shift register circuit 500 shown in FIG. 5 will be described. In this circuit, a plurality of buffer circuits are used as delay elements so that a clock signal is sequentially input from the rear stage to the front stage of the FF circuit. That is, the output of the buffer circuit 10a is
Of the buffer circuit 10b, the output of the buffer circuit 10b is input to the C input of the FF circuit 13 and the buffer circuit 10c, and the output of the buffer circuit 10c is input to the C input of the FF circuit 12 and the buffer circuit 10d. , The output of the buffer circuit 10d is input to the C input of the FF circuit 11. By doing so, the clock signal of the FF circuit in the subsequent stage is transmitted earlier using the predetermined transmission delay of each buffer circuit, and the malfunction as described above does not occur.

[0007]

However, in the circuit configuration shown in FIG. 4, since a buffer circuit as a delay element is used for each FF circuit, the number of FF circuits constituting a synchronous circuit increases. As a result, more buffer circuits are required, and the circuit scale increases. In addition, an increase in clock skew of the synchronous circuit due to accumulation of delay times by a large number of buffer circuits may cause a malfunction due to a delay in operation of the synchronous circuit compared to other circuits.

[0008] In addition, the provision of a tree structure for clock wiring has been accompanied by an increase in the number of buffer circuits and a lack of reliability. Therefore, the present invention provides a highly reliable semiconductor device free from malfunction by making it possible to easily provide a synchronous circuit capable of easily suppressing an increase in clock skew without significantly changing the circuit configuration and circuit scale. It is intended to be easily provided.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, wherein a logic circuit of a preceding stage is shifted from a logic circuit of a preceding stage in response to a clock signal commonly connected to a clock input. In a semiconductor device having a synchronous circuit in which data is sequentially transmitted to a logic circuit and a buffer circuit for supplying the clock signal to a clock input of a plurality of logic circuits, an output wiring of the buffer circuit is provided at a stage subsequent to the logic circuit. It is characterized in that it is laid out such that the delay of the clock signal is greater on the front stage side than on the side and is connected to the clock input. According to a second aspect of the present invention, in the semiconductor device according to the first aspect, each time the output wiring is connected to the clock input of the logic circuit, the output wiring is connected from one side of the logic circuit to the other side. It is characterized in that it is laid out so as to be connected to the clock input of the next stage logic circuit while traversing the arrangement. According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the logic circuit is configured by a flip-flop circuit, and the buffer circuit is a circuit array having a plurality of flip-flop circuits. The output wiring is arranged so as to be able to write approximately one stroke from the rear side of the plurality of flip-flop circuits to the clock input of the front side, and the clock signal is sequentially transmitted from the rear side to the front side of the flip-flop circuit. It is characterized in that it is.

With such a configuration, in the semiconductor device according to any one of the first to third aspects, the delay increases as the distance from the buffer circuit increases due to the distribution delay due to the wiring resistance and the parasitic capacitance of the wiring. The clock signal is sequentially input to the C input of the circuit from the latter stage first.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. In the present specification, the same or similar circuit elements are denoted by the same reference numerals throughout the drawings to simplify the description. FIG. 1 shows an embodiment of the present invention, and FIG.
Is shown as a circuit diagram according to the layout thereof. The shift register circuit 100 shown in FIG. 1 includes a buffer circuit 10 composed of a plurality of inverter circuits connected to a CIN signal serving as a clock signal at an input and outputting a CK signal from an output;
Is composed of D-type FF circuits 31 to 34 commonly connected to the C input of each FF circuit. The data input DA is connected to the D input of the FF circuit 31, the Q output (Q1) is connected to the D input of the FF circuit 32, and the Q output (Q2) is connected to the D input of the FF circuit 33. The Q output (Q3) is connected to the D input of the FF circuit 34, and the Q outputs (Q1 to Q4) of each FF circuit are connected to another logic circuit (not shown).

With such a circuit configuration, each time the rising edge of the clock signal CK is input, the shift register circuit 100 sequentially transfers data based on the data input DA from the preceding FF circuit to the subsequent FF circuit. And the Q1 output of the FF circuit 11 is the least significant bit (LS
The B) data and the Q4 output of the FF circuit 14 are supplied to other circuits as the most significant bit (MSB) data.

FIG. 2 is a layout example in which the circuit of FIG. 1 is arranged and wired by a method called a polycell system or a building block system used for a gate array, a standard cell, and the like. Only wiring other than the main part, connection wiring in each circuit, and the like are omitted. In the drawings, VDD indicates a power supply voltage line, and GND indicates a reference potential line.
The wirings L1, L4, L6, L8 and L10 are connected to VDD or G
A metal wiring (first wiring) in the same layer as a power supply line such as ND is shown, and wirings L2, L3, L5, L7, L9, and L11 are metal wirings (second wiring) in a layer different from the power supply line. Indicates a connection hole (contact) for connecting the first wiring and the second wiring.

A characteristic of the layout diagram of FIG. 2A is that the output from the buffer circuit 10 is connected to the lines L3 to L3.
5, C of the FF circuit 14 from above the drawing of the FF circuit 14
The FF circuit 14 is connected to the input, and
Is connected to the C input of the FF circuit of the next stage while traversing the arrangement of each FF circuit, such as being connected to the C input of the FF circuit 13 after exiting below the drawing. With such a wiring method, the distribution delay due to the wiring resistance and the parasitic capacitance of the wiring increases as the distance from the buffer circuit increases, and the clock signal is input to the C input of each FF circuit in a predetermined order. I have.

FIG. 2B shows a case where a gate electrode to which a clock signal is supplied in each FF circuit is used as a part of the wiring, instead of the second wiring of FIG. 2A. The wirings L5a, L7a, L9a, and L11a are wirings (third wirings) made of polysilicon. The present invention is shown in FIG.
Alternatively, the present invention is not limited to the embodiment shown in FIG.
For example, in FIG. 1 and FIG.
Although only the case where the circuit is a four-stage shift register circuit has been described, other synchronous circuits such as a multi-stage shift register circuit and a synchronous counter circuit can be similarly wired. Also, the arrangement of the synchronization circuits is not limited to a linear arrangement, and a clock signal may be supplied via a plurality of arrangements, and a part of the arrangement may include another circuit unrelated to the synchronization circuit. The wiring may be inserted, or the wiring may be only the second wiring or the polysilicon wiring. In addition to the above-described D-type FF circuit, any type of FF circuit such as a T-type FF circuit or a JK-type FF circuit may be used. It does not matter. Furthermore, a circuit that does not use an FF circuit may be used as long as it is a logic circuit that operates in synchronization, or the buffer circuit 10 may be configured by a single inverter circuit or another circuit by inverting the CIN signal.

[0016]

As described above, in the semiconductor device according to any one of claims 1 to 3, the delay increases as the distance from the buffer circuit increases due to the distribution delay due to the wiring resistance and the parasitic capacitance of the wiring. Since the clock signal is sequentially input to the C input of each FF circuit from the latter stage, the increase in clock skew can be easily suppressed without greatly changing the circuit configuration and circuit scale of the synchronous circuit. As a result, it is possible to reduce erroneous operation due to erroneous data capture in the synchronous circuit or erroneous data capture in the synchronous circuit, and it is possible to easily use a highly reliable semiconductor device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a layout of an embodiment of the present invention,

FIG. 2 is an explanatory diagram showing a layout example according to the embodiment of the present invention;

FIG. 3 is a circuit diagram illustrating a shift register circuit.

FIG. 4 is an explanatory view showing a conventional layout example;

FIG. 5 is a circuit diagram showing another conventional shift register circuit.

[Explanation of symbols]

 100: shift register circuit 10: buffer circuit 11 to 14: FF circuit (DFF) CIN, CK: clock signal DA: data input L1 to L11: wiring

Claims (3)

[Claims] A synchronous circuit for sequentially transmitting data from a preceding logic circuit to a succeeding logic circuit in response to a clock signal commonly connected to a clock input; In a semiconductor device having a buffer circuit for supplying a clock signal, an output wiring of the buffer circuit is laid out such that a delay of the clock signal is larger in a former stage than in a latter stage of the logic circuit. A semiconductor device connected to the clock input. 2. The output circuit according to claim 1, wherein each time the output wiring is connected to the clock input of the logic circuit, the output wiring traverses the arrangement of the logic circuit from one side to another side of the logic circuit. 2. The semiconductor device according to claim 1, wherein the semiconductor device is laid out so as to be connected to the clock input. 3. The logic circuit is constituted by a flip-flop circuit, the buffer circuit is arranged on a rear stage side of a circuit array having a plurality of the flip-flop circuits, and the output wiring is arranged on a rear stage side of the plurality of the flip-flop circuits. The clock signal is wired so that a single stroke can be drawn from the clock input to the preceding stage, and the clock signal is sequentially transmitted from the subsequent stage to the preceding stage of the flip-flop circuit. The semiconductor device according to claim 2.