JPH1027809A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the characteristics of a transistor from being deteriorated even in the case where the density of a current in a drain is high by a method wherein a source region having an impurity concentration higher than that of a channel region is formed in a semiconductor substrate deeper than a p-type semiconductor layer and a p-n junction part is formed between the end surfaces of the source region and the p-type semiconductor layer. SOLUTION: An n-type channel region 3 is formed on the main surface of a semiconductor substrate 1 via a p-type semiconductor layer 2. A gate electrode 6 is formed on the region 3. Source and drain electrodes 7 and 8 are formed on the substrate 1 on both sides of the electrode 6 apart from the electrode 6. A source region 4 having an impurity concentration higher than that of the region 3 is formed in the substrate 1 under the electrode 7 deeper than the layer 2. Moreover, a p-n junction 10 is formed between the end surfaces of the region 4 and the layer 2. Thereby, as holes can be inhibited from being stored, the deterioration of the characteristics of a transistor having the comparatively high density of a current can be prevented from being generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor (MESFET) having a Schottky junction gate.
About.

[0002]

2. Description of the Related Art In general, compound semiconductors are suitable for high-frequency devices because they have a higher electron mobility in a low electric field than Si, which is a single element semiconductor. In particular, GaAs
A field effect transistor (MESFET) having a Schottky junction gate in which a gate electrode, a source electrode, and a drain electrode are formed on an active layer on a semi-insulating compound semiconductor substrate such as It is widely used as a high-frequency transistor. However, recently, with the miniaturization and integration of elements, new problems have arisen. One of the new issues
One is a phenomenon called a short channel effect which occurs with the miniaturization of the gate length, and leads to deterioration of FET performance such as an increase in drain conductance. Another new problem is that in a field effect transistor, a p-type semiconductor layer is generally formed under an active layer in order to perform an effective channel operation. In this case, if the current density increases with miniaturization, The number of holes generated by impact ionization increases, and the generated holes accumulate in the source region of the p-type semiconductor layer immediately below the channel, causing a channel modulation phenomenon.

Recently, in order to address the above problems,
The following field effect transistors have been proposed. First, FIG. 6 shows a conventional technology document “Kimura et al.,“ Asymmetric n ⁺ self-aligned (ASIST) GaAs MESFET ””, IEICE Technical Report, ED88-85, pp4.
7 to 52, September 1989 "is a schematic diagram showing a configuration of a first conventional example. The field effect transistor of the first conventional example shown in FIG. 6 has an n ⁺ source region 40 having an impurity concentration higher than that of the n-type active layer 30 below the source electrode 7 and below the drain electrode 8, respectively. By forming the n ⁺ drain region 50, the ohmic contact resistance between the source electrode 7 and the drain electrode 8 is reduced. Further, in the field effect transistor according to the first conventional example, the n ⁺ source region 40 and the n ⁺ drain region 50 are formed in separate steps to form the n ⁺ drain region 5.
0 has a lower impurity concentration and is formed thinner than the n ⁺ source region 40 to suppress the short channel effect.

FIG. 7 is a schematic diagram showing a configuration of a second conventional field effect transistor disclosed in Japanese Patent Publication No. 7-13981. The field effect transistor of the second conventional example shown in FIG.
Between the active layer 30 and the n ⁺ source region 40 and between the active layer 30 and the n ⁺ drain region 50
And intermediate concentration layers 90a and 90b are formed between them. Here, the intermediate concentration layers 90a and 90b have an impurity concentration higher than the impurity concentration of the active layer 30 and lower than the impurity concentration of the source and drain regions. In the second conventional field effect transistor, the active layers 30 and n ^The intermediate concentration layer 90a formed between the active layer 30 and the n ⁺ drain region 50 is formed thicker than the intermediate concentration layer 90b formed between the active layer 30 and the n ⁺ drain region 50. That is, in the second conventional example, the resistance of the source region can be reduced by forming the intermediate concentration layer 90a thick, and the short channel effect is suppressed by forming the intermediate concentration layer 90b thin.

[0005]

However, the first and second conventional field-effect transistors can suppress the short-channel effect as described above, but the source region of the p-type semiconductor layer can be suppressed. Since the accumulation of holes on the side cannot be prevented, the accumulated holes increase with an increase in the drain current density, causing a problem such as a channel modulation phenomenon and the like, deteriorating the characteristics.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a field effect transistor in which the transistor characteristics do not deteriorate even when the drain current density is high.

[0007]

According to the present invention, a p-type semiconductor layer formed below a channel region and a source region formed immediately below a source electrode are formed so as to have a predetermined positional relationship. Accordingly, it has been found that holes accumulated on the source region side of the p-type semiconductor layer can be recombined with electrons in the source region, and accumulation of holes can be prevented. . That is, a field-effect transistor according to a first aspect of the present invention includes a semiconductor substrate, an n-type channel region formed on a main surface of the semiconductor substrate via a p-type semiconductor layer, and a transistor formed on the channel region. A gate electrode, and a field-effect transistor comprising a source electrode and a drain electrode formed on the semiconductor substrate on both sides of the gate electrode and separated from the gate electrode, wherein the semiconductor under the source electrode A source region having an impurity concentration higher than that of the channel region was formed deeper than the p-type semiconductor layer on the substrate, and a pn junction was formed between the source region and an end surface of the p-type semiconductor layer. It is characterized by the following. Thereby, holes can be moved to an end of the p-type semiconductor layer on the side of the source region which abuts on the source region, and the hole is in contact with the end to facilitate recombination. Since the pn junction is formed, the moved holes can be recombined with the electrons in the source region, and the accumulation of holes in the p-type semiconductor layer can be suppressed.

In the field effect transistor according to the first aspect of the present invention, in order to reduce the ohmic contact resistance of the drain electrode, the semiconductor substrate below the drain electrode further includes an impurity higher than the impurity concentration of the channel region. It is preferable to form a drain region having a concentration, and it is preferable to form the drain region thinner than the source region in order to suppress a short channel effect.

In the field-effect transistor according to the first aspect of the present invention, in order to reduce the concentration of an electric field at the end of the gate electrode, between the channel region and the source region and between the channel region and the drain region. It is preferable that an intermediate concentration region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source region and the drain region is formed between them. Thereby, the gate breakdown voltage can be improved.

The field-effect transistor according to the second aspect of the present invention is an effective solution particularly when the p-type semiconductor layer is formed deep, so that the source region penetrates the p-type semiconductor layer. Even when they are not formed, the same effect as that of the field effect transistor of the first embodiment is obtained. That is, the field-effect transistor according to the second aspect includes a semiconductor substrate, an n-type channel region formed on the main surface of the semiconductor substrate via a p-type semiconductor layer, and a gate formed on the channel region. Electrodes and
A field-effect transistor including a source electrode and a drain electrode formed on the semiconductor substrate on both sides of the gate electrode and separated from the gate electrode, wherein the semiconductor substrate below the source electrode includes a channel region. A source region having an impurity concentration higher than that of the channel region is formed at a depth at least twice the depth of the channel region. Thereby, the generated holes can be moved to the upper end of the p-type semiconductor layer located directly below the channel region on the side of the source region, and can be moved to the upper end of the p-type semiconductor layer. Since the above-mentioned pn junction portion which is easy to be recombined is formed in close proximity, it is possible to recombine the moved holes and the electrons of the above-mentioned source region,
Accumulation of holes in the p-type semiconductor layer can be prevented.

In the field effect transistor according to the second aspect of the present invention, in order to reduce the ohmic contact resistance of the drain electrode, the semiconductor substrate below the drain electrode further includes an impurity higher than the impurity concentration of the channel region. Preferably, a drain region having a concentration is formed, and in order to suppress a short channel effect, the drain region is preferably formed thinner than the source region.

In the field effect transistor according to the second aspect of the present invention, in order to reduce the concentration of the electric field at the end of the gate electrode, between the channel region and the source region and between the channel region and the drain region. And an intermediate concentration region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source region and the drain region. Thereby, the gate breakdown voltage can be increased.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A field effect transistor according to an embodiment of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a schematic diagram showing a configuration of a field-effect transistor according to a first embodiment of the present invention.
The field effect transistor according to the first embodiment is formed by the following method. That is, as shown in FIG. 3A, first, ions such as C or Mg are implanted into the entire surface of the compound semiconductor substrate 1 made of, for example, GaAs to form the p-type semiconductor layer 2s to a predetermined depth. Next, FIG.
As shown in (b), ions of Si or the like are implanted to a predetermined depth in the p-type semiconductor layer 2s to form an n-type semiconductor layer 3s. Next, as shown in FIG. 3 (c), n ⁺
An n-type semiconductor layer 3s is formed in a region where the drain region 5 is to be formed.
Ions of Si or the like to the same depth as
The n ⁺ drain region 5 is formed by implantation so as to have a concentration higher than s.

Further, Si ions are implanted into a region where the n ⁺ source region 4 is to be formed so as to have a depth higher than that of the p-type semiconductor layer 2s so as to have a concentration higher than that of the n-type semiconductor layer 3s.
n ⁺ 2 times or more the depth of the drain region 5 n ⁺ source region 4
To form As described above, the channel layer 3 made of an n-type semiconductor layer is formed at a predetermined position on the main surface of the compound semiconductor substrate 1, and the n ⁺ source region 4 and the n ⁺ drain region 5 are formed on both sides of the channel layer 3. It is formed. Further, a p-type semiconductor layer 2 is formed below the channel layer 3 and the n ⁺ drain region 5, and an end surface of the p-type semiconductor layer 2 is in contact with the n ⁺ source region 4 in the traveling direction of electrons or holes. Almost vertical pn
The joint 10 is formed. Then, a gate electrode 6, a source electrode 7, and a drain electrode 8 are formed on the channel layer 3, the source region 4, and the drain region 5, respectively.
The field effect transistor of the first embodiment shown in FIG. 1 is configured.

Here, in the field-effect transistor of the first embodiment, as the compound semiconductor substrate 1, another compound semiconductor substrate such as InP other than GaAs can be used. In the first embodiment, the impurity concentration of the channel layer 3 is set to 3 × 10 ^{17 to} 6 × 10 ¹⁷ cm ⁻³ , and the thickness is set to, for example, 1000 ° when the gate length is 0.5 μm. It is preferable to set the thickness to the following.
The impurity concentration of n ⁺ source region 4 is 2 × 10 ¹⁸ to
The density is set to 3 × 10 ¹⁸ cm ⁻³ and the thickness is 2000
Preferably, the thickness is set to {3000}.
The impurity concentration of ⁺ drain region 5 is preferably set to 1 × 10 ¹⁸ cm ⁻³ or less.

In the field effect transistor of the first embodiment having the above-described structure, holes generated by impact ionization easily accumulate near the end H of the p-type semiconductor layer 2 on the n ⁺ source region side. Since the pn junction 10 is formed, the holes that have moved to the end H can be recombined with the electrons in the n ⁺ source region 4, and the accumulation of holes at the end H can be reduced. Can be suppressed. Here, the number of holes generated by impact ionization increases as the drain current increases, and the number of holes increases. Also, the pn junction 10
The ratio of recombination is as follows: where n is the impurity concentration of the n ⁺ source region 4 and p is the impurity concentration of the p-type semiconductor layer 2, ΔC _n (pn ² −n _i ² n) + C _p (np ² −n _i ² p)｝. Here, C _n and C _p are Auger coefficients, and n _i
Represents the intrinsic carrier concentration. Therefore, n ⁺ source region 4
By increasing the impurity concentration and increasing the junction area of the pn junction 10, recombination can be performed more effectively, and the accumulation of holes can be more effectively prevented.

In the field effect transistor of the first embodiment configured as described above, holes can be recombined with electrons in the n ⁺ source region 4 at the pn junction 10, and the H shown in FIG. Since accumulation of holes in the portion can be suppressed, deterioration of characteristics due to the channel modulation phenomenon can be prevented even in an FET (field-effect transistor) having a relatively large current density, and as shown in FIG. The generated drain voltage Vd can be increased. here,
Kinking is a phenomenon in which holes accumulated in a substrate (p-type semiconductor layer) positively bias the substrate (p-type semiconductor layer) to lower a threshold voltage, thereby causing a sudden increase in drain current. it, and the FIG. 2, a kink a 'in the case of forming a shallow n ⁺ source region (deep enough and the channel layer 3 same), and a kink a in the case of deeply formed an n ⁺ source region This is schematically shown. In addition, since the n ⁺ drain region 5 is formed to have the same thickness as the channel layer 3, the short channel effect can be suppressed.

<Modification> FIG. 4 is a schematic diagram showing the structure of a field-effect transistor according to a modification. In the field-effect transistor according to the first embodiment, an n ⁺ drain region 5 is provided.
The structure is the same as that of the first embodiment except that the structure is not formed. Even with the above configuration, the same effects as in the first embodiment can be obtained.

<Second Embodiment> FIG. 5 is a schematic diagram showing the structure of a field-effect transistor according to a second embodiment. In the field-effect transistor according to the first embodiment, an n ⁺ source region 4 is further added. Except that an intermediate concentration layer 9a is formed between the n ⁺ drain region 5 and the channel region 3;
The configuration is the same as that of the first embodiment. Here, the intermediate concentration layers 9 a and 9 b are formed to have a thickness substantially equal to that of the channel region 3. With the above configuration, the same effect as in the first embodiment can be obtained, and the concentration of the electric field at the end of the gate electrode 6 can be reduced as compared with the first embodiment. Can be improved.

[0020]

According to the first aspect of the field effect transistor of the present invention, the semiconductor substrate below the source electrode has a source region having an impurity concentration higher than that of the channel region on the semiconductor substrate. Since the pn junction is formed close to the end of the p-type semiconductor layer, which is formed deeper than the layer and holes are likely to accumulate, the accumulation of holes can be suppressed. Can be prevented from deteriorating.

In the field effect transistor according to the first aspect of the present invention, a drain region having an impurity concentration higher than an impurity concentration of the channel region is formed in the semiconductor substrate below the drain electrode, and the drain region is By being formed thinner than the source region, the ohmic contact resistance of the drain electrode can be reduced, and the short channel effect can be suppressed.

In the field effect transistor according to the first aspect of the present invention, the impurity concentration between the channel region and the source region and between the channel region and the drain region is higher than the impurity concentration of the channel region. By forming an intermediate concentration region having an impurity concentration lower than the impurity concentration of the source region and the drain region, the gate withstand voltage can be increased.

In a field effect transistor according to a second aspect of the present invention, the semiconductor substrate below the source electrode includes a source region having an impurity concentration higher than the impurity concentration of the channel region. Since the pn junction is formed close to the end of the p-type semiconductor layer, which is formed at a depth of twice or more and holes are likely to accumulate, the accumulation of holes can be suppressed. However, deterioration of transistor characteristics can be prevented.

In the field effect transistor according to a second aspect of the present invention, a drain region having an impurity concentration higher than that of the channel region is formed in the semiconductor substrate below the drain electrode, and the drain region is By being formed thinner than the source region, the ohmic contact resistance of the drain electrode can be reduced, and the short channel effect can be suppressed.

In the field effect transistor according to a second aspect of the present invention, the impurity concentration between the channel region and the source region and between the channel region and the drain region are higher than the impurity concentration of the channel region. By forming an intermediate concentration region having an impurity concentration lower than the impurity concentration of the source region and the drain region, the gate withstand voltage can be increased.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a kink phenomenon in a drain current Id with respect to a drain voltage Vd of a field-effect transistor.

FIG. 3 is a conceptual diagram illustrating a method for manufacturing the field-effect transistor of FIG.

FIG. 4 is a schematic diagram illustrating a configuration of a field-effect transistor according to a modified example of the invention.

FIG. 5 is a schematic diagram illustrating a configuration of a field-effect transistor according to a second embodiment of the present invention.

FIG. 6 is a schematic diagram showing a configuration of a first conventional field-effect transistor.

FIG. 7 is a schematic diagram showing the configuration of a second conventional field-effect transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Compound semiconductor substrate, 2 ... P-type semiconductor layer, 3 ... Channel layer, 4 ... n ⁺ source region, 5 ... n ⁺ drain region, 6 ... Gate electrode, 7 ... Source electrode, 8 ... Drain electrode, 9a, 9b ... intermediate concentration region, 10 ... pn junction.

Claims (6)

[Claims] 1. A semiconductor substrate, an n-type channel region formed on a main surface of the semiconductor substrate via a p-type semiconductor layer, a gate electrode formed on the channel region, and both sides of the gate electrode A field effect transistor comprising a source electrode and a drain electrode formed on the semiconductor substrate apart from the gate electrode, wherein the semiconductor substrate under the source electrode has an impurity concentration higher than that of the channel region. A field effect transistor wherein a source region having a high impurity concentration is formed deeper than the p-type semiconductor layer, and a pn junction is formed between the source region and an end surface of the p-type semiconductor layer. 2. The semiconductor device according to claim 1, further comprising a drain region formed on the semiconductor substrate below the drain electrode, the drain region having a higher impurity concentration than the channel region.
A field-effect transistor according to claim 1. 3. The field effect transistor according to claim 1, further comprising an impurity concentration higher than an impurity concentration of said channel region between said channel region and said source region and between said channel region and said drain region. 3. The field effect transistor according to claim 2, wherein an intermediate concentration region having an impurity concentration lower than that of the drain region is formed. 4. A semiconductor substrate, an n-type channel region formed on a main surface of the semiconductor substrate via a p-type semiconductor layer, a gate electrode formed on the channel region, and both sides of the gate electrode A field effect transistor comprising a source electrode and a drain electrode formed on the semiconductor substrate apart from the gate electrode, wherein the semiconductor substrate under the source electrode has an impurity concentration higher than that of the channel region. A field effect transistor, wherein a source region having a high impurity concentration is formed at a depth of at least twice the channel region. 5. The field effect transistor further includes a drain region formed thinner than the source region on the semiconductor substrate below the drain electrode and having a higher impurity concentration than the impurity concentration of the channel region.
A field-effect transistor according to claim 1. 6. The field effect transistor further comprising a region between the channel region and the source region and a region between the channel region and the drain region, each having a higher impurity concentration than the channel region. 6. The field effect transistor according to claim 5, wherein an intermediate concentration region having an impurity concentration lower than that of said source region and said drain region is formed at a depth substantially equal to said channel region.