JPH11265896A - Field effect transistor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a gate without deteriorating linearity by modifying the structure of a conventional FET, suppressing the accumulation of holes directly below a channel region and suppressing the substrate current. An object of the present invention is to provide a field-effect transistor suitable for analog signal processing and a method for manufacturing the same. SOLUTION: An "inactive region" which does not substantially function as an n-type channel region or a p-type buried region is provided between a channel region and a p-type buried region.
By providing such an inactive region, the occurrence of kink and the occurrence of substrate leakage current can be effectively suppressed, and the invention can be applied to analog signal processing in a high frequency band.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method for manufacturing the same. More specifically, the present invention relates to a field-effect transistor suitable for signal processing of a high-frequency analog signal and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a structure of a field effect transistor (FET) used for digital signal processing requiring a high current driving force such as an optical communication system, a so-called buried p-lay (BP) is used.
r) A type structure was used. FIG. 6 is a schematic sectional view showing such a conventional BP structure. That is, the conventional BP-type FET has the n-type channel region 112, the n ⁺ -type source region 114, and the drain region 116 formed on the surface of the insulating (SI) GaAs substrate 101. On the channel region 112, for example, a gate electrode in which a tungsten nitride (WNx) layer 120 and a tungsten (W) layer 122 are stacked is formed. Further, a source electrode 130 and a drain electrode 132 are formed in the source region and the drain region, respectively. Further, gate sidewalls 126 are provided adjacent to the gate electrode,
In some cases, n-type intermediate concentration regions 140 having an intermediate carrier concentration between the channel region and the source / drain regions therebelow are provided.

In this FET, the channel region is substantially thinned by providing a high-concentration p-type buried region 150 under the channel region 112. Further, since the substrate leakage current between the source and the drain can be suppressed, the gate electrode can be shortened. As a result, the current driving force is improved, which is advantageous for high-speed operation.

[0004]

However, a problem arises when a conventional BP-type field effect transistor as shown in FIG. 6 is used for analog signal processing such as a power amplifier for a mobile communication terminal. That is, the conventional BP type FE
At T, kinks occur in the current characteristics because holes (holes) generated by impact ionization accumulate immediately below the channel region. As a result, there is a problem that linearity is deteriorated and power efficiency is reduced.

The kink will be further described as follows. That is, at the end of the gate electrode having a high current density, electrons and holes are generated by impact ionization. Of these electrons and holes, holes accumulate below the channel region. As a result, a parasitic bipolar transistor effect occurs, and a relatively large substrate current temporarily flows at a certain drain voltage. This phenomenon is called "kink". This kink causes deterioration of linearity.

As a result, when the conventional BP-type FET is applied to an analog application where linearity is important, a problem arises because high-concentration holes accumulate in a shallow place to cause kink. In order to suppress kink, it is necessary to lower the hole concentration below the channel region.

[0007] The present inventors have proposed a so-called P-pocket type structure (PP) as a structure for suppressing the accumulation of holes in order to solve this problem. FIG. 7 shows this P
It is sectional drawing showing the schematic structure of a pocket type structure. In the figure, the same parts as those of the above-described BP-type FET are denoted by the same reference numerals, and detailed description thereof will be omitted. In a P-pocket FET, p
No mold region is provided, and p-type pocket regions 160, 160 are provided below the source / drain regions, respectively.

[0008] In such a PP structure, the accumulation of holes near the channel region can be effectively suppressed. As a result, the occurrence of kink is effectively suppressed,
The linearity is improved, and the power characteristics are improved.

However, as a result of the study by the present inventor, in the PP type structure, there is no p-type region immediately below the channel region, and therefore, there is a problem that the substrate leakage current tends to increase particularly when the gate is shortened. I found it. Also, P
When the gate electrode length is reduced in a P-type FET, the structure approaches a BP-type structure. As a result, it has been found that a problem that kink is likely to occur also occurs.

FIG. 8 is a graph showing the relationship between gate length and current driving force (gm) in the BP type structure and the PP type structure. As shown in the figure, in the BP type structure, the maximum value of gm is obtained when the gate length is 0.5 μm. In the BP structure, the p-type buried region is provided immediately below the channel region, so that the substrate leakage current is also suppressed. Generally, in the application of digital signal processing, a high current driving force is required, and kinks are not regarded as important. Therefore, it is possible to form a transistor having a BP structure with a gate length of 0.5 μm.

On the other hand, in applications for analog signal processing, excellent linearity is required. However, since kink occurs in the BP structure, the PP structure must be used. However, the kink does not occur in the PP type structure, but the current driving force is smaller than that in the BP type structure. Further, there is a problem in that the kink is generated near the BP type structure on the short gate side. Therefore, when a transistor having a PP-type structure is applied to analog signal processing, the gate length cannot be reduced. That is, as shown in FIG. 8, in the PP type structure, the maximum value of the current driving force is obtained when the gate length is 0.6 μm, but the gate length is about 0.8 μm in order to secure the linearity. At present, it is relatively long and formed for analog use.

The present invention has been made based on the recognition of such a problem. That is, the purpose is
By modifying the structure of T and suppressing the accumulation of holes directly under the channel region and also suppressing the substrate current, the gate length can be shortened without deteriorating the linearity. An object of the present invention is to provide a suitable field effect transistor and a method for manufacturing the same.

[0013]

That is, a field effect transistor according to the present invention comprises: a first region doped with a first conductivity type impurity in a surface portion of a semiconductor substrate;
A first portion which is provided below the region and has a second conductivity type impurity introduced therein, wherein the first portion substantially acts as the first conductivity type channel region in the first region; A second portion substantially acting as the buried region of the second conductivity type in a second region, and substantially the first conductivity type between the first portion and the second portion; A third portion, which does not act as a semiconductor and substantially does not act as the second conductivity type semiconductor, is interposed. By providing the third portion, the third portion is caused by accumulation of holes. In addition to suppressing kinks, substrate leakage current can also be effectively suppressed.

Alternatively, a field effect transistor according to the present invention comprises a first conductivity type channel region provided on a surface portion of a semiconductor substrate, and a first conductivity type source region and a drain region provided on both sides of the channel region. And an inactive region provided below the channel region; and a buried region of the second conductivity type provided below the inactive region, wherein the inactive region is provided. By
The kink caused by the accumulation of holes can be suppressed, and the substrate leakage current can be effectively suppressed.

Alternatively, the field effect transistor according to the present invention is provided so as to be adjacent to both sides of the channel region on the surface portion of the semiconductor substrate and the first conductivity type channel region provided on the surface portion of the semiconductor substrate. A first intermediate region and a second intermediate region of a first conductivity type having a higher carrier concentration than the channel region; and a channel region adjacent to the first intermediate region on a surface portion of the semiconductor substrate. A source region of the first conductivity type, which is provided on the opposite side and has a higher carrier concentration than the first intermediate region, and the second region at a surface portion of the semiconductor substrate;
A drain region of a first conductivity type provided adjacent to the intermediate region and opposite to the channel region and having a higher carrier concentration than the first intermediate region; And a buried region of the second conductivity type provided adjacent to the inactive region, the source region, and the drain region below the inactive region. In addition to suppressing the kink caused by the accumulation of GaN, the substrate leakage current can also be suppressed effectively.

Alternatively, a field effect transistor according to the present invention comprises a first conductivity type channel region provided on a surface portion of a semiconductor substrate, and a first conductivity type source region and a drain region provided on both sides of the channel region. And a buried region of the second conductivity type provided below the channel region;
Wherein the depth of the concentration peak of the second conductivity type impurity introduced into the substrate to form the buried region from the substrate surface is introduced into the substrate to form the channel region. 0.25 μm larger than the depth of the concentration peak of the first conductivity type impurity from the substrate surface.
m or more, the depth of the concentration peak of the impurity of the second conductivity type introduced into the substrate to form the buried region from the substrate surface, and the substrate to form the source region and the drain region. Said first introduced into
The difference between the concentration peak of the conductivity type impurity and the depth from the surface of the substrate is 0.25 μm or less, which suppresses the kink caused by the accumulation of holes and reduces the substrate leakage current. Can also be effectively suppressed.

Here, the carrier concentration of the second conductivity type in the p-type buried region is configured to be 1 × 10 ¹⁶ cm ⁻³ or less, so that the holes are accumulated. Can be suppressed, and the substrate leakage current can be effectively suppressed.

On the other hand, the method of manufacturing a field-effect transistor according to the present invention comprises a first conductivity type channel region provided on a surface portion of a semiconductor substrate and a first conductivity type source region provided on both sides of the channel region. And a drain region, and a buried region of the second conductivity type provided below the inactive region, wherein the impurity of the second conductivity type is added to the surface of the semiconductor substrate by 25%.
A step of forming the buried region of the second conductivity type by injecting at an accelerating voltage of 0 keV or more; suppressing a kink caused by the accumulation of holes by forming the buried region deeply At the same time, the substrate leakage current can be effectively suppressed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a schematic configuration of a field effect transistor according to the present invention.
That is, the field-effect transistor 10 of the present invention has the n-type channel region 12, the n ⁺ -type source region 14, and the drain region 16 formed on the surface of the insulating (semi-insulating: GaAs) substrate 11. . On the channel region 12, for example, tungsten nitride (WNx)
A gate electrode in which the layer 20 and the tungsten (W) layer 22 are stacked is formed. The source region and the drain region have a source electrode 30 and a drain electrode 32, respectively.
Are formed. Further, as shown in the figure, gate sidewalls 26, 26 are provided adjacent to the gate electrode, and between the channel region and the source / drain region thereunder, an n-type having an intermediate carrier concentration between the two. Intermediate density area 4
0 and 40 may be provided.

The FET 10 of the present invention has a channel region 12
A p-type buried region 50 is provided at a predetermined interval below. That is, an inactive region 60 having an extremely low electron concentration and a very low hole concentration is provided between the channel region 12 and the p-type buried region 50. According to the present invention,
Through such an inactive region 60, the p-type buried region 5
By providing 0, the generation of holes directly below the channel region 12 can be suppressed, and the substrate leakage current can also be suppressed effectively. Here, the inactive region 6 shown in FIG.
The shape of 0 is in a state where no bias voltage is applied. In a state where a predetermined bias voltage is applied to each electrode of the transistor to operate the transistor, the layer thickness of the inactive region 60 changes in the longitudinal direction of the channel and has a predetermined distribution.

In the present invention, as a method of forming the p-type buried region 50 via the inactive region 60, for example, a method of ion-implanting a p-type impurity at a higher acceleration voltage than in the prior art can be mentioned. For example, the p-type buried region 15 in the conventional BP type structure as shown in FIG.
In order to form 0, a method of ion-implanting magnesium (Mg) under an acceleration voltage of about 200 keV has been implemented. On the other hand, when forming the p-type buried region 50 of the present invention, for example, magnesium (Mg) is used.
Is implanted under the condition of an acceleration voltage of about 400 keV.
Thus, the configuration of the present invention can be realized by implanting p-type impurities at a higher acceleration voltage than in the conventional BP-type structure.

FIG. 2 shows a doping profile diagram and a carrier concentration profile diagram below a gate portion of the transistor of the present invention. That is, FIG. 2A is a concentration profile diagram of the doping impurity from below the gate along the depth direction of the GaAs substrate, and FIG. 2B is a carrier concentration profile diagram.

Here, the conditions for forming the illustrated transistor are as follows. First, the channel region 12 is formed by depositing silicon at an acceleration voltage of 45 keV and a dose of 6 × 10 ¹² cm.
^-2 . Further, the intermediate concentration region 40 is formed by
The implantation is performed at keV and 1.3 × 10 ¹³ cm ⁻² . The source region 14 and the drain region 16 are made of
Implant at eV, 6 × 10 ¹³ cm ⁻² . Also, the p-type buried region 50 is made of magnesium at 400 keV, 3 × 10
Ion implantation is performed under the condition of ¹² cm ^-2 .

The carrier concentration profile shown in FIG. 2B shows the peak of the hole concentration peak generated when 0 volt is applied to the gate-source voltage and 6 volt is applied to the drain-source voltage of the transistor. It is a profile figure in a position.

From FIG. 2A, in the transistor of the present invention, the n-type impurity forming the channel region has a relatively steep concentration profile, and its peak is located at a depth of about 0.04 μm. You can see that there is. On the other hand, the p-type impurity forming the p-type buried region has a very gentle concentration profile, and its peak has a depth of about 0.45.
It is at a very deep position of μm.

Next, looking at the carrier concentration profile shown in FIG. 2B, the electron concentration in the channel region has a very steep profile, and its concentration peak is about 1.10.
4 × 10 ¹⁷ cm ⁻³ , located at a depth of about 0.06 μm. Here, the reason why the peak of the electron concentration is formed at a position deeper than the concentration peak of the n-type impurity is that the surface layer of the channel region is depleted due to the Schottky junction with the metal gate stacked on the surface of the channel region. Because it becomes

Here, the range that effectively acts as the channel region is defined as the range from the electron concentration to the portion where the electron concentration decreases to 1/10 ⁶ from the peak concentration. This is because, with such a definition, 99.99% or more of the electrons moleculed in the n-type region can be included in the range. FIG.
In the profile shown in (b), the portion where the electron concentration is 1.4 × 10 ¹¹ cm ⁻³ is effective as a channel region with respect to the electron peak concentration of 1.4 × 10 ¹⁷ cm ⁻³ . Range. In FIG. 2B,
This range is indicated by oblique lines. The lower end of this range is located at a depth of about 0.16 μm from the surface.

On the other hand, a similar range can be defined for p-type impurities. That is, in the p-type buried region, the range that substantially acts as the p-type is defined as the range in which the hole concentration decreases from the peak concentration to 1/10 ⁶ . In the profile shown in FIG. 2B, the hole concentration peak is about 1 × 10 ¹⁶ cm ⁻³ ,
The range of the mold region can be defined as the portion where the hole concentration decreases to 1 × 10 ¹⁰ cm ⁻³ . As shown in the figure, the upper limit of this region is located at about 0.23 μm from the surface.

According to the present invention, as shown in the figure, the lower limit of the hatched portion of the electron concentration and the upper limit of the hatched portion of the hole concentration are separated by an interval of about 0.07 μm in the depth direction. ing. That is, the region effectively acting as the channel region and the region effectively acting as the p-type region are about 0.07.
They are separated by an interval of μm. And this 0.
The portion of 07 μm is a portion which does not substantially act as an n-type channel region or a p-type buried region.
In this specification, this region is referred to as an “inactive region”. According to the present invention, by providing such an inactive region, the occurrence of kink and the occurrence of substrate leakage current can be effectively suppressed.

FIGS. 3A and 3B are a doping profile diagram and a carrier concentration profile diagram of a conventional BP-type transistor evaluated for comparison. Here, at the time of forming this BP-type transistor, magnesium is applied to the p-type buried region 150 by accelerating voltage 200 ke.
V, ion implantation at a dose of 2 × 10 ¹² cm ⁻² ,
Other conditions were the same as those of the present invention described above.

The impurity concentration profile shown in FIG.
Compared with the profile of the present invention shown in FIG. 2A, the n-type impurity has almost the same profile,
It can be seen that the p-type impurity has a steeper profile than that of the present invention, and its concentration peak is formed at a position of about 0.25 μm, which is very shallower than that of the present invention.

Further, comparing the carrier concentration profile shown in FIG. 3B with that of FIG. 2B, it can be seen that the electron concentration in the channel region has almost the same profile as that of the transistor of the present invention. However, the peak of the hole concentration in the p-type region is as high as about 1 × 10 ¹⁸ cm ⁻³ ,
Also, the position is very shallow, about 0.25 μm from the substrate surface. That is, the conventional BP-type transistor has a steep and high hole concentration peak at a shallower position than the transistor of the present invention.

As a result of examining the effective range of the electron and hole profiles shown in FIG. 3B according to the same definition as described above with reference to FIG. 2, the lower limit of the effective range for the n-type channel region is the depth. It was found to be located at about 0.15 μm, and the upper limit of the effective range for the p-type region was located at a depth of about 0.13 μm. That is, in the conventional BP-type transistor, the substantial n-type region and the substantial p-type region overlap, and there is no inactive region.

The presence or absence of such an inactive region causes a remarkable difference between the characteristics of the transistor of the present invention and the characteristics of the conventional transistor, as will be described in detail later. As a result of detailed studies by the present inventors, in order to achieve both the suppression of kink and the suppression of substrate leakage current in the present invention, the concentration peak of the p-type impurity forming the p-type buried region forms the channel region. It has been found that it is desirable that the concentration is 0.25 μm or more deeper than the n-type impurity concentration peak and within 0.25 μm from the n-type impurity concentration peak position forming the source / drain region.

That is, it is desirable that the p-type impurity is formed at a position 0.25 μm or more deeper than the n-type impurity under the gate. Further, in order to introduce the p-type impurity in this manner, it is desirable that the acceleration voltage for ion implantation of the p-type impurity be 250 keV or more. This is because, when formed under such conditions, the above-described inactive region can be provided. If the p-type impurity is shallower than this, as will be described in detail later, it approaches a conventional BP-type structure, and kinks easily occur.

On the other hand, it is desirable that the peak position of the p-type impurity in the buried region should not be formed deeper than the peak position of the n-type impurity in the source / drain region by more than 0.25 μm. If the p-type impurity is deeper than this, an inactive region is also formed between the buried region and the source / drain region, the effect of the p-type buried region is suppressed, the substrate leakage current increases, and the short gate This is because there is a tendency to make the conversion difficult.

Next, the present inventors examined the hole concentration distribution of the transistor of the present invention in more detail, and compared it with a transistor having a conventional structure.

FIG. 4 is a profile diagram showing a two-dimensional hole concentration distribution during operation of the transistor. That is, FIG. 2A shows the transistor of the present invention, and FIG.
Is a two-dimensional concentration profile of holes for a conventional PP transistor, and FIG. 10C is a two-dimensional concentration profile of holes for a conventional BP transistor.

Here, as the bias voltage, the gate voltage
This represents the case where 0 volt is applied between the source and 7 volt between the drain and the source. Further, in FIG. 4, the contour lines of the hole concentration distribution are shown at a 10 1 power pitch. FIG.
As shown in (a), according to the present invention, the peak of the hole concentration is located below the channel region near the source, has a depth of 0.5 μm, and has a peak concentration of about 1 × 10 ^16. cm
It is ^-3 . Note that the hole concentration profile shown in FIG. 2B is represented along this concentration peak.

Next, in the case of the PP type structure shown in FIG. 4B, the peak of the hole concentration is located at a depth of about 0.3 μm, and the peak concentration is about 1 × 10 ¹⁴ cm ^{− 3}

On the other hand, in the case of the BP type structure shown in FIG. 4C, the peak of the hole concentration is extremely shallow, about 0.25 m in depth, and the peak concentration is also about 1 × 10 ¹⁸ cm ^−3. And high.
The hole concentration profile shown in FIG.
It is shown along this concentration peak.

When comparing FIG. 4 (b) and FIG. 4 (c),
In the case of the PP structure shown in FIG. 4B, the hole concentration peak is as shallow as 0.3 μm, but the concentration is about 1 × 10 ^14.
It is characterized by a low point of cm ^-3 . That is, in the PP-type structure, it is found that the accumulation of holes under the channel region is effectively suppressed. On the other hand, FIG.
In the case of the conventional BP-type structure described above, the peak of the hole concentration is extremely shallow, about 0.25 μm in depth, and the peak concentration is also extremely high, about 1 × 10 ¹⁸ cm ^−3. It was found that holes were accumulated in the holes and kink tended to occur. Conventionally, the accumulation of such high-concentration and shallow holes has caused "kinks". That is, when the conventional BP-type FET is applied to an analog application where linearity is emphasized, a problem arises because high-concentration holes accumulate in a shallow place to cause kink.

On the other hand, according to the present invention shown in FIG. 4A, the peak concentration of holes is about 1 × 10 ¹⁶ cm ^−3, which is higher than that of the PP type, but the depth is about 0.5 μm. To be deep
No parasitic bipolar effect occurs, and kink is effectively suppressed. That is, according to the present invention, since kink can be effectively suppressed, it can be used for analog signal processing applications requiring excellent linearity.

As described above, according to the present invention, p
By deeply forming the mold buried region and providing an inactive region between the channel region and the channel region, the accumulation of holes under the channel region is effectively suppressed, the generation of kink is prevented, and the linearity of the current characteristic is reduced. Nature can be secured sufficiently.

Next, the present inventors prototyped the transistor of the present invention and a conventional transistor, respectively, and compared and evaluated the substrate leakage current.

FIG. 5 is a graph showing the drain voltage / current characteristics of each transistor. In each of the transistors, the gate length was 0.5 μm. From the figure, it can be seen that, in the case of the PP type structure, when the drain voltage is 2 volts, the drain current flows about 10 times that of the transistor of the present invention and the BP type transistor, and when the drain voltage is 8 volts, about 1000 times It can be seen that a drain current flows.

This is because, in the case of the PP-type structure, the substrate leak current easily occurs because the p-type region is not provided immediately below the channel region. In particular, since FIG. 5 shows a transistor whose gate length is as short as 0.5 μm, this tendency is strong.

On the other hand, the transistor of the present invention
To have a p-type buried region below the channel region,
It can be seen that the substrate leakage current is effectively suppressed and the drain current is sufficiently small. That is, in the transistor of the present invention, the substrate leakage current can be suppressed to the same level as in the BP structure.

The embodiment of the invention has been described with reference to examples. However, the present invention is not limited to these specific examples. For example, the present invention can be similarly applied to a transistor in which an intermediate concentration region is not provided between a channel region and a source / drain region to obtain a similar effect.

The materials used in the present invention are not limited to those shown as specific examples. In addition, for example, the same applies to field effect transistors made of indium phosphide (InP) or other compound semiconductors. Can be applied.

[0051]

According to the present invention, the accumulation of holes under the channel region is effectively suppressed, the generation of kinks is effectively suppressed, the linearity is improved, and the power characteristics are improved. .

Further, according to the present invention, the substrate leakage current can be sufficiently suppressed.

Further, according to the present invention, the gate length can be reduced without increasing the substrate leakage current. As a result, a transistor with low leakage current and excellent frequency characteristics can be realized.

That is, according to the present invention, a transistor having low leakage, excellent linearity, and excellent frequency characteristics can be realized. A field effect transistor suitable for use in the field can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a schematic configuration of a field-effect transistor according to the present invention.

FIG. 2 shows a doping profile diagram and a carrier concentration profile diagram below a gate portion of the transistor of the present invention.

FIG. 3 shows a doping profile diagram and a carrier concentration profile diagram of a conventional BP-type transistor evaluated for comparison.

FIG. 4 is a profile diagram showing a two-dimensional hole concentration distribution during operation of the transistor. That is, FIG. 2A shows a two-dimensional hole of the transistor of the present invention, FIG. 2B shows a two-dimensional hole of the conventional PP transistor, and FIG. 2C shows a two-dimensional hole of the conventional BP transistor. It is a density profile figure.

FIG. 5 is a graph showing drain voltage-current characteristics of a transistor.

FIG. 6 is a schematic sectional view showing a conventional BP structure.

FIG. 7 is a sectional view illustrating a schematic configuration of a P pocket type structure.

FIG. 8 is a graph showing a relationship between a gate length and a current driving force (gm) in a BP type structure and a PP type structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Field effect transistor 11, 101 Substrate 12, 112 Channel region 14, 114 Source region 16, 116 Drain region 20, 22, 120, 122 Gate electrode 26, 126 Side wall 30, 130 Source electrode 32, 132 Drain electrode 40, 140 Middle Region 50, 150 buried region 60 inactive region 160 pocket region

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshiaki Kitaura 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba R & D Center

Claims (5)

[Claims] A first region in which a first conductivity type impurity is introduced in a surface portion of the semiconductor substrate; and a second conductivity type impurity provided below the first region of the semiconductor substrate in which the second conductivity type impurity is introduced. A first portion substantially acting as the channel region of the first conductivity type in the first region; and a buried region of the second conductivity type substantially in the second region. A second portion acting between the first portion and the second portion, substantially not acting as the semiconductor of the first conductivity type, substantially the second conductivity type And a third portion which does not act as a semiconductor of the above. A first conductivity type channel region provided on a surface portion of the semiconductor substrate; a first conductivity type source region and a drain region provided on both sides of the channel region; A field effect transistor comprising: an inactive region provided; and a buried region of a second conductivity type provided below the inactive region. 3. A channel region of a first conductivity type provided on a surface portion of a semiconductor substrate, and a carrier which is provided adjacent to both sides of the channel region on the surface portion of the semiconductor substrate and is higher than the channel region. A first intermediate region and a second intermediate region having a first conductivity type having a concentration; and A first conductivity type source region having a higher carrier concentration than the first intermediate region; and a first conductive type source region provided on the surface portion of the semiconductor substrate, adjacent to the second intermediate region and opposite to the channel region; A first conductivity type drain region having a higher carrier concentration than the intermediate region, a non-active region provided below the channel region, and a The field effect transistor, characterized in that the non-active region and the source region and the drain region and the second conductivity type provided adjacent to the embedded region, with a. 4. A channel region of a first conductivity type provided on a surface portion of a semiconductor substrate; a source region and a drain region of a first conductivity type provided on both sides of the channel region; And a buried region of the second conductivity type provided, wherein the depth of the concentration peak of the impurity of the second conductivity type introduced into the substrate to form the buried region from the surface of the substrate is: 0.25 μm or more deeper than the depth from the substrate surface of the concentration peak of the first conductivity type impurity introduced into the substrate to form the channel region, The depth of the concentration peak of the introduced second conductivity type impurity from the substrate surface, and the first conductivity type impurity introduced into the substrate to form the source region and the drain region. The difference between the impurity concentration peak and the depth from the substrate surface is 0.
A field effect transistor, wherein the field effect transistor is configured to be 25 μm or less. 5. A channel region of a first conductivity type provided on a surface portion of a semiconductor substrate; a source region and a drain region of a first conductivity type provided on both sides of the channel region; And a buried region of the second conductivity type provided in the semiconductor device, wherein the impurity of the second conductivity type is added to the surface of the semiconductor substrate by 250 k.
forming a buried region of the second conductivity type by implanting at an acceleration voltage of eV or more.