JPH1028043A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device capable of enlarging the VIL and VIH margins of input signals without causing the increase of a chip area by inserting a resistor element between a reference potential and an input circuit. SOLUTION: The resistor element 4 used for the serial terminating resistor of an output buffer is inserted between the reference potential 7 and the reference potential input part of an input buffer circuit in the case of performing use as the input buffer circuit. That is, in the case of using this input/output circuit (semiconductor device) as the input buffer circuit, the input signals from a pad 6 are inputted through a protection element 5 to one of the terminals of a GTL input circuit 1. By the constitution, since the noise of the reference potential 7 actually inputted to the GTL input circuit 1 is suppressed and stablized by the resistor element 4, the VIL margin and the VIH margin are widened for that portion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a small amplitude input / output interface circuit.

[0002]

2. Description of the Related Art In recent years, power consumption tends to increase as the speed and integration of semiconductor integrated circuits increase. For example, a CMOS circuit consumes relatively low power, but a recent CMOS LSI has a power consumption of several watts to several tens of watts. Therefore, in order to cope with the reduction in power consumption and the increase in speed, an input / output circuit for performing an interface at a voltage level lower than the power supply voltage may be used for the interface circuit of the CMOS LSI in some cases.

For example, the logic level of the GTL interface is 1.2 V on the HIGH side and 0.4 V on the LOW side.
, Which is lower than a commonly used power supply voltage (for example, 3.3 V). In this GTL interface, since the signal amplitude is very small at 0.8 V, the input circuit uses a differential amplifier, and determines the logic level of the input signal by comparison with a reference voltage (0.8 V).

Therefore, it is extremely important for the operation of the LSI to stably supply the reference voltage to the input circuit. In particular, noise generated during operation in an LSI with large power consumption,
This reference voltage is liable to fluctuate because the power supply voltage is large. Therefore, a resistor is inserted between the reference voltage source (often received from the outside of the chip) and the input circuit to absorb noise, or a capacitor is inserted to stabilize the reference voltage against noise. A method has been proposed. (See, for example, JP-A-56-134753)

[0005]

In the above-mentioned conventional example,
It is necessary to form a dedicated resistor and a dedicated capacitor for forming the resistor and the capacitor in the LSI, and there is a problem that the chip area is increased.

In order to suppress the increase in chip area, resistors and capacitors must be formed small.
There is a problem that a sufficient effect cannot be obtained.

Therefore, a margin (VIL, VI) of a sufficient signal level in the input circuit due to the "fluctuation" of the reference voltage.
H margin) cannot be secured.

In particular, in a recent high power consumption LSI, the "fluctuation" becomes large, and furthermore, the reference voltage is set to the LSI.
In this case, there is a problem that the "fluctuation" of the power supply voltage in the LSI is directly reflected on the reference voltage and the VIL and VIH margins are reduced.

Therefore, an object of the present invention is to solve the problem of V
An object of the present invention is to provide a semiconductor device which can increase an IL and VIH margin and does not increase a chip area.

[0010]

According to the present invention, an input buffer circuit which receives a reference voltage and determines an input level by comparing a voltage with the reference voltage, an output circuit, and an input / output having a resistance element Wherein the input / output circuit forms the input buffer circuit by a wiring process, and the reference voltage is input via the resistance element when the input buffer circuit is formed. can get.

Further, according to the present invention, there is provided an input buffer circuit which receives a reference voltage and determines an input level by comparing a voltage with the reference voltage, an output circuit, and an input / output circuit having a resistance element. The input / output circuit constitutes the output buffer circuit by a wiring process, and the resistor element is connected in series with the output circuit to output a signal when the output buffer circuit is constituted. Can be

Further, according to the present invention, there is provided a semiconductor device characterized by being generated from a supplied power supply.

[0013]

Next, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. 1 and 2 are layout diagrams showing an embodiment of the present invention,
3 and 4 are circuit diagrams corresponding to FIG.

Referring to FIGS. 1 and 2, the semiconductor device has a GTL input circuit 1, a gate unit 2, an output circuit 3, a resistance element 4, a protection element 5, and a pad 6 arranged in the order described above. An input / output circuit is configured. This input / output circuit is L
It is arranged on the outer periphery of SI. The wiring of the reference potential 7 is arranged along the input / output circuit arranged above the resistance element 4.

First, a case where this input / output circuit is used as an output buffer circuit will be described with reference to FIG. As shown in FIG. 4, necessary logic is obtained in the gate unit 2 and the output circuit 3
An output signal is generated by a transistor mounted on the device. This output signal is transmitted from pad 6 through resistance element 4 and protection element 5. The resistance element 4 is a series termination resistor for the output circuit 3, and is used for stabilizing an output waveform. A relatively large current of several mA to several tens mA flows through the resistor, and a resistor having a relative size as shown in FIG. 1 is required in order to secure the resistance value accuracy. The resistance is formed by, for example, a gate polycide forming the gate of a MOS transistor. The size at this time is, for example, about 20 μm × 100 μm, and the resistance value is about 50Ω.

Next, the case of using as an input circuit will be described. As shown in FIGS. 2 and 3, an input signal from the pad 6 is input to one terminal D of the GTL input circuit 1 via the protection element 5. The reference potential 7 is input to the terminal A of the resistance element 4, and is input from the terminal B to the other terminal C of the GTL input circuit 1. Either the input buffer circuit or the output buffer circuit is selected depending on the wiring process.

Here, the reference potential 7 is generated by a reference potential generation circuit 21 in the chip as shown in FIG. 3 as an example. In this case, since the reference potential 7 is generated from the power supply voltage, its value fluctuates with a relatively large amplitude due to fluctuation of the power supply voltage, noise, or the like. The noise component is absorbed in the potential of the reference potential (Vth) including noise by the resistance component and the parasitic capacitance component of the resistance element 4. FIG. 5 shows potential levels at respective points corresponding to FIG. FIG. 5 is a reference potential level Vth at point A in FIGS. 2 and 3, and FIG.
Reference potential level at point B and the input signals VIL and VI
Shows the H margin. Since the GTL input circuit 1 is a differential amplifier circuit, the potential difference between the H level of the input signal and Vth is substantially equal to Vth.
The IH margin is provided, and the potential difference between the Vth level and the L level of the input signal is substantially equal to the VIL margin. The larger these values are, the larger the operating margin (noise margin) is.

In the present embodiment, the resistance G
Since the noise of the reference potential input to the TL input circuit 1 is suppressed and stabilized, the VIL margin and VIH
Margins widen.

In the embodiment of the present invention, the case where the reference potential generating circuit 21 for the reference potential 7 is provided in the chip has been described, but the case where the reference potential 7 is supplied from outside the chip is similarly applied. Can be applied. Further, the present invention can be used not only in the GTL input circuit but also in an input circuit form using the reference potential 7.

[0020]

As described above, according to the present invention, in a semiconductor device having an input buffer circuit using a reference potential and an input / output circuit having a resistance element, a resistance element is inserted between the reference potential and the input circuit. As a result, the fluctuation of the reference potential can be reduced.
This has the effect that the IH margin can be increased. At this time, since the resistance element is already prepared for the output buffer circuit, the chip area is not increased.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing an input / output circuit of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a layout diagram showing wiring of the input / output circuit shown in FIG.

FIG. 3 is a circuit diagram of the input / output circuit of FIG. 1;

FIG. 4 is a circuit diagram when the input / output circuit of FIG. 1 is used as a buffer circuit.

FIG. 5 is a graph showing a relationship between a change in reference potential and VIL and VIH margins in FIG. 1;

FIG. 6 is a graph showing a relationship between a change in reference potential and a VIL and VIH margin in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GTL input circuit 2 Gate part 3 Output circuit 4 Resistance element 5 Protection element 6 Pad 7 Reference potential 21 Reference potential generation circuit

Claims (3)

[Claims] An input buffer circuit that receives a reference voltage and determines an input level by comparing a voltage with the reference voltage; an output circuit; and an input / output circuit having a resistance element. Wherein the input buffer circuit is formed by a wiring process, and the reference voltage is input via the resistance element when the input buffer circuit is formed. 2. An input / output circuit, comprising: an input buffer circuit which receives a reference voltage and determines an input level by comparing a voltage with the reference voltage; an output circuit; and an input / output circuit having a resistance element. A semiconductor device, wherein the output buffer circuit is formed by a wiring process, and when the output buffer circuit is formed, the resistance element is connected in series with the output circuit to output a signal. 3. The semiconductor device according to claim 1, wherein the reference voltage is generated from a supplied power supply.