JPH1028109A - Bit protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of a circuit scale even when the number of bits is increased by counting the number of protecting stages at every bit and successively writing and reading the counted protecting stage number at every bit as against a shared memory. SOLUTION: A selector 7 selects 1 by a carry signal at a rear part protecting side, O by the carry signal at a front part protecting side and a protecting result at the time of a preceding frame, which is stored in RAM 4, in the other cases so as to execute an output. Then, the protecting result is written in RAM 4. Since a data signal inputted to a counter 1-2 is inverted by an inverter 2 in a front part protecting operation, the bit state of a rear part protecting operation only becomes the opposite one. But, 0 is outputted as the protecting result by the logic of the selector 7. Thus, storage is temporarily executed in RAM 4 so that one circuit is shared concerning the respective bits of serially multiplexed status bits and, therefore, the circuit scale is not increased even when the bits are increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit protection circuit, and more particularly to a bit protection circuit for performing forward and backward protection on serially multiplexed status bits.

[0002]

2. Description of the Related Art In data transmission circuits, status bits indicating the state of each part of the circuit may be serially multiplexed and transmitted in addition to the main signal data to be transmitted.
Since the contents of such status bits may change due to an error during transmission, it is usual to perform forward protection and backward protection for a predetermined number of protection stages. In other words, even when the contents of the bits change, only when the state after the change continues for the predetermined number of protection steps, the fact that the contents have changed is definitely handled. For example, as shown in FIG. 3, data D1 to D
The detection of m status bits of m increases the reliability by passing through a protection circuit in consideration of the case where the detected bits are erroneous due to an error in the transmission path. The data D1 to Dm in the figure are one frame, a frame pulse rises in each frame, and a clock rises in each data.

In the conventional protection circuit, if the status bit to be detected is m bits, as shown in FIG. 4, the protection circuit 8 for detecting one bit is required for m bits.

In FIG. 1, a protection circuit 8 includes counters 9-1 and 9-2 for counting the number of protection stages and an inverter 2 for inverting a data signal input to one counter 9-2.
And a reset / set-flip-flop (RS-F / F) 10 that receives the carry signals of the counters 9-1 and 9-2 and outputs a protection result. The clock signal input to each protection circuit is output from the timing generation circuit 11 based on the clock and the frame pulse. Here, protection when the bit state (contents of the bit) changes from "0" to "1" is defined as backward protection (the number of protection steps is x), and the opposite is protection in the forward direction (y is the number of protection steps). Then, the counter 9-1 becomes a rear protection counter, and the counter 9-2 becomes a front protection counter.

[0005] The rearward protection operation will be described. The data signal is supplied to the enable terminal (E) of the counter 9-1 for backward protection.
N) and the load terminal (LD), the initial value of the preset number of protection stages is read when the bit content of the input data is "0". The initial value set here is a value at which the value of (initial value + number of protection stages x) becomes the full count value of the counter.

Next, when the content of the bit changes to "1", both the enable terminal and the load terminal of the rear protection counter 9-1 become "1", so that the counter counts up. Then, when the content of the bit continues to be "1" and the counter is counted up x times, the counter becomes full count and outputs a carry signal. Since the carry signal is input to the set terminal (S) of the RS-F / F 10, the output (protection result) is "1".

If the bit is "0" and the bit is inverted due to noise or the like, the rear protection counter 9-1 counts up. However, since the rear protection counter 9-1 does not reach a full count unless it is continuously inverted x times, no carry signal is output and the output does not become "1". In this way, it is assumed that the bit content has changed only when a predetermined number of protection stages is reached, thereby protecting against noise and the like.

Next, the forward protection operation will be described. Since the inverted data signal is input to the enable terminal and the load terminal of the forward protection counter 9-2, the forward protection operation is only the opposite of the bit state of the backward protection operation. However, since the carry signal output from the front protection counter 9-2 is input to the reset terminal (R) of the RS-F / F 10, the protection result is “0”.

FIG. 5 shows a protection circuit described in Japanese Patent Application Laid-Open No. 1-73836. The bit protection circuit shown in FIG. 1 includes a shift register 12 for delaying a data signal by one frame, and a data signal and a shift register 1.
2, an exclusive OR gate 13 for detecting coincidence with the data signal delayed by one frame output from 2, an adding circuit 14 for counting the number of protection stages based on the detection result of the exclusive OR gate, and a count value and protection of the adding circuit 14. And the result
A RAM 4 for storing bit by bit the address output from the address counter 15 based on the clock and the frame pulse, an x detection circuit 16 for detecting that the count value of the adder circuit 14 is x, and a count value of y
Y detection circuit 17 and x detection circuit 1
6 and a selector 7 for selecting a protection result by both outputs of the y detection circuit 17.

Next, the operation will be described. The status bits multiplexed serially are exclusive OR gates 13,
The bit is compared with the previous bit output from the shift register 12. The adder circuit 14 counts up the count value until the previous frame output from the RAM 4 when the comparison result indicates a match, and resets the count value to “0” when the comparison result indicates a mismatch. Then, the count value is written into the RAM 4 again. That is,
A different count value is temporarily stored in the RAM 4 for each bit, and reading / writing of the count value for each bit is performed based on the address output from the address counter 15.

An x detection circuit 16 detects a state in which the addition circuit 14 has counted the number x of data matches, and the y detection circuit 1
7 detects the number of matches y. Here, the exclusive OR gate 13 is a gate for detecting a data matching state.
In both cases of "1" and "0", the matching state is detected. That is, the adder circuit 14 counts both the backward protection and the forward protection, and another detection circuit may operate first depending on the magnitudes of x and y. Therefore, a data signal is input to each detection circuit as an enable signal to control the circuits.

The selector 7 outputs "1" in response to the input of the detection signal of the x detection circuit 16, outputs "0" in response to the input of the detection signal of the y detection circuit 17, Outputs the protection result of the corresponding bit of the previous frame stored in the RAM 4. Then, the output protection result is RA
Written to M4. Since the protection operation is performed continuously for m bits, the protection result is output serially.

[0013]

The conventional bit protection circuit shown in FIG. 4 requires the same number of protection circuits as the number of bits to be detected, and has a drawback that the circuit scale increases as the number of bits increases. . Although the circuit of FIG. 5 is a circuit that can handle a plurality of bits to be detected, a shift register is used to delay data by one frame. Therefore, if the number of bits to be detected is about several bits, there is no particular problem. However, for example, when the number of bits to be detected is several hundreds, the shift register itself becomes large-scale, and the circuit scale also increases.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a bit protection circuit which does not increase the circuit scale.

[0015]

SUMMARY OF THE INVENTION A bit protection circuit according to the present invention is a bit protection circuit that performs at least one of forward protection and backward protection on the contents of individual bits of serial data composed of a plurality of bits, A counting means for sequentially counting the number of times a specific value is continuous for each of the plurality of bits and counting the number of times a specific value is continuous for each of the bits, and a continuous number value to be sequentially preset for the counting means. Storage means for reading out and sequentially writing the count value of the counting means as a new continuous count value for the bit; and storing the count value written to the storage means and a predetermined protection stage value for each bit. And a comparing means for making a comparison output every time.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention is as follows.

In order to solve the above problem, the bit protection circuit of the present invention counts the number of rear and front protection stages using a counter with a preset. Further, the count value of the number of protection stages is divided into a rearward and a forward
M, and the process of writing and reading the number of protection stages is performed for each bit. As a result, even when the number of bits increases, an increase in circuit scale can be suppressed.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a bit protection circuit according to the present invention. This bit protection circuit includes counters 1-1 and 1-2 capable of presetting data asynchronously with a clock, an inverter 2 for inverting a data signal input to one of the counters 1-2, and counters 1-1 and 1--1. Count value output from 2 and backward /
Comparators 3-1 and 3-2 for comparing the number of forward protection stages (backward / forward protection values), a read state when the clock is "H", and a write state when the clock is "L", and the counter 1-1.
, A RAM 4 for storing a count value for each bit output from 1-2 and a protection result, an address signal for an address terminal (ADDRESS) of the RAM 4 and a counter 1
Preset enable (PE) for -1 and 1-2
And a flip-flop (F / F) 6 for retiming the result of comparison with the number of protection stages output from the comparators 3-1 and 3-2.
-1 and 6-2, and a selector 7 for selecting and outputting a protection result based on a comparison result of the number of protection stages output from the F / Fs 6-1 and 6-2. Here, assuming that protection when the bit state changes from “0” to “1” is backward protection (the number of protection steps is x) and the opposite is forward protection (the number of protection steps is y), the counter 1− 1 is a rear protection counter, and the counter 1-2 is a front protection counter.

Next, the backward protection operation will be described with reference to FIG. A preset enable signal at the timing shown in FIG. 2D is input to the preset enable terminal (PE) of the counter 1-1. With this enable signal, the counter 1-1 sets data read from the RAM 4 when the signal is "L", and performs the counting operation at the falling edge of the clock when the signal is "H".

A data signal (FIG. 2A) is input to the reset terminal (R) of the counter 1-1. When the content of the input status bit is "1", a normal count operation is performed. When the count is "0", the count value is reset, that is, set to "0". The RAM 4 performs a read / write operation according to the clock signals “H” and “L” in FIG.

While the status bit is "0",
The counter 1-1 is in the reset state as described above,
The value written to AM4 is also "0". On the other hand, when the state of the bit changes from "0" to "1", the counter 1-1 is preset with the count value "0" written in the RAM 4 by the preset enable signal (a), and the clock falls. Counting is performed at the edge (b). As a result, the count value changes from "0" to "1", and the count value "1" is written into the RAM 4.

When "1" continues in the state of the bit, the count-up is continued ((E) in the figure). Then, when the count value advances to x, which is the number of rear protection stages, it matches the symmetry to be compared in the comparator 3-1. For this reason,
A carry signal is output as shown in FIG. The carry signal is retimed by the F / F 6-1 by the clock shown in FIG. 2B and input to the selector 7 as shown in FIG.

In the selector 7, "1" is set for the carry signal on the rear protection side, "0" is set for the carry signal on the front protection side,
At other times, the protection result at the previous frame stored in the RAM 4 is selected and output. Then, the protection result ((H) in the figure) is written in the RAM 4.

In the forward protection operation, since the data signal input to the counter 1-2 is inverted by the inverter 2, only the bit state of the above-described backward protection operation is reversed. However, “0” is output as a protection result by the logic of the selector 7.

As described above, the bit protection circuit comprises:
A counter having a data preset function is used as a counter for counting the number of times that a specific value is continuous for each bit, that is, the number of protection steps both rearward and forward, and the counter value of the counter and the protection result are stored in each bit. By temporarily storing the status bits in the RAM every time, one circuit can be shared for each of the serially multiplexed status bits. Therefore, even if the number of bits increases, the circuit scale does not increase.

In the circuit disclosed in Japanese Patent Application Laid-Open No. 1-73836, a shift register whose circuit size is determined by the number of bits in one frame is used. Can be suppressed.

Although the protection circuit for status bits has been described above, it is clear that other bits can be protected.

The present invention can take the following aspects in connection with the description of the claims.

(4) A clock that transitions from the first level to the second level at the transition timing of the plurality of bits and transitions from the second level to the first level at a timing other than the transition timing of the bits. As an input, the count value is preset in the counting means at a transition timing of the clock to a second level, and the counting means performs a counting operation at a transition timing of the clock to the first level. The bit protection circuit according to claim 1.

(5) When the clock is at the second level, a count value is read from the storage means, and when the clock is at the first level, the count value is written to the storage means. The bit protection circuit according to claim 1, wherein

[0032]

As described above, according to the present invention, the number of protection stages is counted for each bit, and the counted number of protection stages is sequentially written and read for each bit with respect to the shared memory. There is an effect that the circuit scale does not increase even when the number increases.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a bit protection circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the bit protection circuit of FIG.

FIG. 3 is a waveform diagram showing contents of a data signal input to a bit protection circuit.

FIG. 4 is a block diagram showing a configuration of a conventional bit protection circuit.

FIG. 5 is a block diagram showing a configuration of another conventional bit protection circuit.

[Explanation of symbols]

 1-1, 1-2 Counter 2 Inverter 3-1, 3-2 Comparator 4 RAM 5 Timing generation circuit 6-1, 6-2 Flip-flop 7 Selector

Claims (3)

[Claims] 1. A bit protection circuit that performs at least one of forward protection and backward protection on the content of each bit of serial data composed of a plurality of bits, wherein a specific value is continuous for each of the plurality of bits. Counting means for sequentially counting the number of consecutive times of a specific value for each of the bits, and a continuous number value to be sequentially preset to the counting means is sequentially read out; And a comparing means for comparing, for each bit, a count value written to the storing means and a predetermined protection stage value for each bit. A bit protection circuit characterized in that a result is a protection output. 2. The bit protection circuit according to claim 1, wherein said storage means is a semiconductor memory. 3. The method according to claim 1, wherein the forward protection and the backward protection are regarded as being changed only when the state in which the content of the bit has changed continues for the number of protection stages. Bit protection circuit.