JPH1028232A - display - Google Patents

display

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Publication number
JPH1028232A
JPH1028232A JP18039396A JP18039396A JPH1028232A JP H1028232 A JPH1028232 A JP H1028232A JP 18039396 A JP18039396 A JP 18039396A JP 18039396 A JP18039396 A JP 18039396A JP H1028232 A JPH1028232 A JP H1028232A
Authority
JP
Japan
Prior art keywords
circuit
distortion
graphic distortion
display
graphic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18039396A
Other languages
Japanese (ja)
Inventor
Koji Kito
浩二 木藤
Kentaro Oku
健太郎 奥
Isao Yoshimi
功 吉見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18039396A priority Critical patent/JPH1028232A/en
Publication of JPH1028232A publication Critical patent/JPH1028232A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce the apparent graphic distortion and to improve the display quality by preparing a graphic distortion-generation circuit which generates the graphic distortion at an infinite visual point, in order to reduce the apparent graphic distortion that is caused at a finite visual point. SOLUTION: The signal inputted to a signal input terminal T1 is added to a drive circuit 2, which converts the signal into a drive signal suitable to a display device 1 and adds it to the device 1. The display screen of the device 1 is curved, and a user sees this curved screen with a finite distance. Thus, the apparent graphic distortion is generated. When the user inputs the visual point position to a visual point position input means 6, the visual point position information is fetched by an arithmetic controller 4. A memory 5 stores the graphic distortion generation data to reduce the apparent graphic distortion, corresponding to the visual point position. Then the controller 4 generates the graphic distortion corresponding to the input visual point position information, and a graphic distortion generation circuit 3 produces a graphic distortion generation signal and outputs it to the circuit 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はディスプレイに関す
る。
The present invention relates to a display.

【0002】[0002]

【従来の技術】従来、ブラウン管ディスプレイ等表示面
が湾曲したディスプレイでは無限遠から見た時の図形歪
が最小となる様に調整されている。
2. Description of the Related Art Conventionally, in a display having a curved display surface such as a cathode ray tube display, adjustment is made so that the figure distortion when viewed from infinity is minimized.

【0003】この種のディスプレイに関する従来技術
は、特開平6−334887号、特開平6−23314
9号公報がある。
[0003] The prior art relating to this type of display is disclosed in JP-A-6-334887 and JP-A-6-23314.
No. 9 publication.

【0004】[0004]

【発明が解決しようとする課題】上記従来例では、無限
遠点から見た図形歪が無い場合でも、ユーザの使用環境
である有限遠の視点から見た時に生じる見かけの図形歪
については考慮されていない。
In the above conventional example, even if there is no figure distortion as viewed from a point at infinity, an apparent figure distortion generated when viewed from a finite point of view, which is a user's usage environment, is taken into consideration. Not.

【0005】本発明の目的は、表示面が湾曲したディス
プレイで、有限遠の視点から見た時に生じる見かけの図
形歪を低減し、ユーザの使用環境での表示品質を向上す
ることにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a display having a curved display surface, to reduce apparent graphic distortion generated when viewed from a finite viewpoint, and to improve display quality in a user's use environment.

【0006】[0006]

【課題を解決するための手段】上記問題点を解決するた
めに、本発明は有限遠の視点から見た時に生じる見かけ
の図形歪を低減する様に無限遠の視点での図形歪を発生
する図形歪発生回路を設けた。
In order to solve the above-mentioned problems, the present invention generates a graphic distortion at an infinite viewpoint so as to reduce an apparent graphic distortion occurring when viewed from a finite viewpoint. A graphic distortion generating circuit is provided.

【0007】[0007]

【発明の実施の形態】以下、本発明の実施例について図
を用いて説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0008】図1は本発明によるディスプレイの第1の
実施例を示すブロック図ある。図1で、1は表示デバイ
ス、2は駆動回路、3は図形歪発生回路、4は演算制御
回路、5はメモリ、6は視点位置入力手段、T1は信号
入力端子である。
FIG. 1 is a block diagram showing a first embodiment of a display according to the present invention. In FIG. 1, 1 is a display device, 2 is a drive circuit, 3 is a graphic distortion generation circuit, 4 is an arithmetic control circuit, 5 is a memory, 6 is a viewpoint position input means, and T1 is a signal input terminal.

【0009】図1で、信号入力端子T1に入力された信
号は駆動回路2に加えられる。この信号は、駆動回路2
により表示デバイス1に適した駆動信号に変換され、表
示デバイス1に加えられる。表示デバイス1の表示面は
湾曲していて、ユーザはこれを有限の距離から見ること
になり、見かけの図形歪が発生する。ユーザが視点位置
入力手段6に視点位置を入力すると、視点位置情報が演
算制御回路4に取り込まれる。メモリ5には視点位置に
対応した見かけの図形歪を低減するための図形歪発生デ
ータが保持されていて、演算制御回路4は入力された視
点位置情報に対応した図形歪発生データを作成し、図形
歪発生回路3に出力する。図形歪発生回路3は図形歪発
生データより図形歪発生信号を作成し、駆動回路2に出
力する。この結果、見かけの図形歪を低減し、ユーザの
使用環境での表示品質を向上することが出来る。
In FIG. 1, a signal input to a signal input terminal T 1 is applied to a drive circuit 2. This signal is supplied to the drive circuit 2
Is converted into a drive signal suitable for the display device 1 and is applied to the display device 1. The display surface of the display device 1 is curved, and the user views the display from a finite distance, and apparent graphic distortion occurs. When the user inputs the viewpoint position to the viewpoint position input means 6, the viewpoint position information is taken into the arithmetic and control circuit 4. The memory 5 holds graphic distortion generation data for reducing apparent graphic distortion corresponding to the viewpoint position, and the arithmetic and control circuit 4 creates graphic distortion generation data corresponding to the input viewpoint position information, Output to the graphic distortion generating circuit 3. The graphic distortion generation circuit 3 creates a graphic distortion generation signal from the graphic distortion generation data and outputs the signal to the drive circuit 2. As a result, it is possible to reduce apparent graphic distortion and improve display quality in a user's use environment.

【0010】図2はCRTディスプレイの見かけの図形
歪の一例を示したものである。(a)は表示面が水平方
向のみ湾曲した円筒状の場合であり、(b)は表示面が
球面状の場合である。いずれも点線が無限遠点での図形
歪なしの場合を示しており、実線が×印上の有限遠から
見た見かけの図形歪を表している。
FIG. 2 shows an example of apparent graphic distortion of a CRT display. (A) is a case where the display surface is cylindrical only curved in the horizontal direction, and (b) is a case where the display surface is spherical. In each case, the dotted line shows the case where there is no figure distortion at the point at infinity, and the solid line shows the apparent figure distortion seen from finite distance on the X mark.

【0011】図3は本発明による第1の実施例をCRT
ディスプレイに適用した例を示している。図3で、51
はビデオプリアンプ、52はビデオ出力回路、53は垂
直偏向コイル、54は水平偏向コイル、55はCRT、
56は垂直偏向回路、57は水平偏向回路、58は高圧
回路、T2は水平同期信号入力端子、T3は垂直同期信
号入力端子、T6はビデオ信号入力端子である。
FIG. 3 shows a first embodiment of a CRT according to the present invention.
The example applied to the display is shown. In FIG.
Is a video preamplifier, 52 is a video output circuit, 53 is a vertical deflection coil, 54 is a horizontal deflection coil, 55 is a CRT,
56 is a vertical deflection circuit, 57 is a horizontal deflection circuit, 58 is a high voltage circuit, T2 is a horizontal synchronization signal input terminal, T3 is a vertical synchronization signal input terminal, and T6 is a video signal input terminal.

【0012】すなわちCRTディスプレイでは表示デバ
イス1がCRT55、垂直偏向コイル53、水平偏向コ
イル54に相当する。また、駆動回路2がビデオプリア
ンプ51、ビデオ出力回路52、垂直偏向回路56、水
平偏向回路57に相当する。
That is, in the CRT display, the display device 1 corresponds to the CRT 55, the vertical deflection coil 53, and the horizontal deflection coil 54. The drive circuit 2 corresponds to a video preamplifier 51, a video output circuit 52, a vertical deflection circuit 56, and a horizontal deflection circuit 57.

【0013】図4は図3の垂直偏向回路56、水平偏向
回路57、図形歪発生回路3の第1の例を示す回路図で
あり、CRTの表示面が水平方向のみ湾曲した円筒状の
場合である。
FIG. 4 is a circuit diagram showing a first example of the vertical deflection circuit 56, the horizontal deflection circuit 57, and the graphic distortion generation circuit 3 shown in FIG. 3, in which the display surface of the CRT is a cylindrical shape curved only in the horizontal direction. It is.

【0014】この場合には、図2(a)より図形歪発生
回路3として上下独立調整可能な上下ピン歪発生回路と
左右独立の水平リニアリティ歪発生回路を設ければ見か
けの図形歪が低減できる。
In this case, apparent graphic distortion can be reduced by providing upper and lower independent pin distortion generating circuits and vertically independent horizontal linearity distortion generating circuits as the graphic distortion generating circuit 3 as shown in FIG. .

【0015】図4で、7は水平発振回路、8は水平ドラ
イブ回路、9は水平出力トランジスタ、10はダンパダ
イオード、11は共振コンデンサ、12は水平偏向コイ
ル、13はチョークコイル、14はS字コンデンサ、1
5は水平ブランキングパルス発生回路、16は水平ノコ
ギリ波発生回路、17は水平パラボラ波発生回路、1
8,19,20,21は電圧制御アンプ、22,23,
24は加算器、25は乗算器、26はS字電圧制御回
路、27は制御電圧発生回路、28は垂直発振回路、2
9は差動アンプ、30は垂直出力アンプ、31は垂直偏
向コイル、32はコンデンサ、33は抵抗器である。
In FIG. 4, 7 is a horizontal oscillation circuit, 8 is a horizontal drive circuit, 9 is a horizontal output transistor, 10 is a damper diode, 11 is a resonance capacitor, 12 is a horizontal deflection coil, 13 is a choke coil, and 14 is an S-shape. Capacitor, 1
5 is a horizontal blanking pulse generating circuit, 16 is a horizontal sawtooth wave generating circuit, 17 is a horizontal parabolic wave generating circuit, 1
8, 19, 20, 21 are voltage controlled amplifiers, 22, 23,
24 is an adder, 25 is a multiplier, 26 is an S-shaped voltage control circuit, 27 is a control voltage generation circuit, 28 is a vertical oscillation circuit,
9 is a differential amplifier, 30 is a vertical output amplifier, 31 is a vertical deflection coil, 32 is a capacitor, and 33 is a resistor.

【0016】以下に図4の動作を説明する。The operation of FIG. 4 will be described below.

【0017】水平発振回路7、水平ドライブ回路8、水
平出力トランジスタ9、ダンパダイオード10、共振コ
ンデンサ11、水平偏向コイル12、チョークコイル1
3、S字コンデンサ14は水平偏向回路57を構成して
おり、水平偏向コイル12には水平信号入力端子T2か
ら入力された水平同期信号と同一の周波数の水平のこぎ
り波電流が流れる。
A horizontal oscillation circuit 7, a horizontal drive circuit 8, a horizontal output transistor 9, a damper diode 10, a resonance capacitor 11, a horizontal deflection coil 12, and a choke coil 1.
3. The S-shaped capacitor 14 forms a horizontal deflection circuit 57, and a horizontal sawtooth current having the same frequency as the horizontal synchronization signal input from the horizontal signal input terminal T2 flows through the horizontal deflection coil 12.

【0018】垂直発振回路28、差動アンプ29、垂直
出力アンプ30、垂直偏向コイル31、コンデンサ3
2、抵抗器33は垂直偏向回路56を構成しており、垂
直偏向コイル31には垂直同期信号入力端子T3から入
力された垂直同期信号と同一の周波数の垂直のこぎり波
電流が流れる。
A vertical oscillation circuit 28, a differential amplifier 29, a vertical output amplifier 30, a vertical deflection coil 31, and a capacitor 3
2. The resistor 33 forms a vertical deflection circuit 56, and a vertical sawtooth current having the same frequency as the vertical synchronization signal input from the vertical synchronization signal input terminal T3 flows through the vertical deflection coil 31.

【0019】水平ブランキングパルス発生回路15、水
平のこぎり波発生回路16、水平パラボラ波発生回路1
7、電圧制御アンプ18,19、加算器22、S字電圧
制御回路26は左右独立の水平リニアリティ歪発生回路
を構成しており、水平パラボラ波と水平のこぎり波の合
成信号により水平偏向回路57のS字コンデンサ14の
電圧を制御する事により左右独立の水平リニアリティ歪
を発生させる。
Horizontal blanking pulse generator 15, horizontal sawtooth generator 16, horizontal parabola generator 1
7, the voltage control amplifiers 18 and 19, the adder 22, and the S-shaped voltage control circuit 26 constitute a left and right independent horizontal linearity distortion generation circuit, and the horizontal deflection circuit 57 is formed by a composite signal of a horizontal parabola wave and a horizontal sawtooth wave. By controlling the voltage of the S-shaped capacitor 14, left and right independent horizontal linearity distortion is generated.

【0020】水平パラボラ波発生回路17、電圧制御ア
ンプ20,21、加算器24、乗算器25は上下独立調
整可能な上下ピン歪発生回路を構成しており、水平パラ
ボラ波と垂直のこぎり波と水平パラボラ波との乗算信号
との合成信号を加算器23により垂直偏向回路56の差
動アンプ29に入力する事により垂直偏向電流を制御
し、上下独立の上下ピン歪を発生させる。
The horizontal parabolic wave generating circuit 17, the voltage control amplifiers 20, 21, the adder 24, and the multiplier 25 constitute an upper / lower pin distortion generating circuit capable of vertically adjusting independently. The vertical deflection current is controlled by inputting a combined signal of the multiplication signal with the parabolic wave to the differential amplifier 29 of the vertical deflection circuit 56 by the adder 23, thereby generating upper and lower independent pin distortion.

【0021】制御電圧発生回路27は、演算制御回路4
の一部であり電圧制御アンプ18,19,20,21に
制御電圧を送り、見かけの図形歪が低減する様に各図形
歪成分の振幅調整を行う。この結果、ユーザの使用環境
での表示品質を向上する事が出来る。
The control voltage generation circuit 27 includes an arithmetic control circuit 4
And sends a control voltage to the voltage control amplifiers 18, 19, 20, and 21 to adjust the amplitude of each figure distortion component so that the apparent figure distortion is reduced. As a result, it is possible to improve display quality in a user's use environment.

【0022】図5は図3の垂直偏向回路56,水平偏向
回路57,図形歪発生回路3の第2の例を示す回路図で
あり、CRTの表示面が球面状の場合である。
FIG. 5 is a circuit diagram showing a second example of the vertical deflection circuit 56, the horizontal deflection circuit 57, and the graphic distortion generation circuit 3 in FIG. 3, in which the display surface of the CRT is spherical.

【0023】この場合には、図2(b)より図形歪発生
回路3として図4に左右独立調整可能な左右ピン歪発生
回路と上下独立の垂直リニアリティ歪発生回路を追加す
れば見かけの図形歪が低減できる。
In this case, apparent figure distortion can be obtained by adding a left and right pin distortion generating circuit capable of independently adjusting left and right and a vertical linearity distortion generating circuit which is vertically independent as FIG. 4 as the figure distortion generating circuit 3 from FIG. 2B. Can be reduced.

【0024】図5で、34は加算器、35は水平同期信
号遅延回路、36は電源電圧変調回路、37,38,3
9,40は電圧制御アンプ、41は制御電圧発生回路、
42は垂直パラボラ波発生回路、43は垂直S字補正信
号発生回路、44は垂直ブランキングパルス発生回路で
ある。
In FIG. 5, 34 is an adder, 35 is a horizontal synchronizing signal delay circuit, 36 is a power supply voltage modulation circuit, and 37, 38, and 3
9 and 40 are voltage control amplifiers, 41 is a control voltage generation circuit,
42 is a vertical parabolic wave generation circuit, 43 is a vertical S-shaped correction signal generation circuit, and 44 is a vertical blanking pulse generation circuit.

【0025】垂直パラボラ波発生回路42、垂直ブラン
キングパルス発生回路44、水平同期信号遅延回路3
5、電源電圧変調回路36、電圧制御アンプ37,38
は左右独立調整可能な左右ピン歪発生回路を構成してお
り、垂直パラボラ波を水平同期信号遅延回路35と電源
電圧変調回路36に加える事により左右独立調整可能な
左右ピン歪を発生させる。
The vertical parabolic wave generating circuit 42, the vertical blanking pulse generating circuit 44, and the horizontal synchronizing signal delay circuit 3
5. Power supply voltage modulation circuit 36, voltage control amplifiers 37 and 38
Constitutes a left and right pin distortion generating circuit capable of right and left independent adjustment, and applies a vertical parabola wave to a horizontal synchronizing signal delay circuit 35 and a power supply voltage modulation circuit 36 to generate left and right independently adjustable left and right pin distortion.

【0026】電圧制御アンプ39,40、加算器34、
垂直S字補正信号発生回路43は上下独立の垂直リニア
リティ歪発生回路を構成しており、垂直パラボラ波と垂
直S字補正信号を加算器34に加える事により垂直偏向
電流を制御して上下独立の垂直リニアリティ歪を発生さ
せる。
The voltage control amplifiers 39 and 40, the adder 34,
The vertical S-shaped correction signal generation circuit 43 constitutes a vertical linearity distortion generation circuit which is independent of the upper and lower sides. Generate vertical linearity distortion.

【0027】制御電圧発生回路41は、演算制御回路4
の一部であり電圧制御アンプ18,19,20,21,
37,38,39,40に制御電圧を送り、見かけの図
形歪が低減する様に各図形歪成分の振幅調整を行う。こ
の結果、ユーザの使用環境での表示品質を向上する事が
出来る。
The control voltage generation circuit 41 includes an arithmetic control circuit 4
And voltage control amplifiers 18, 19, 20, 21,
The control voltage is sent to 37, 38, 39, and 40, and the amplitude of each graphic distortion component is adjusted so that the apparent graphic distortion is reduced. As a result, it is possible to improve display quality in a user's use environment.

【0028】図6は本発明による第2の実施例を示すブ
ロック図であり、図1との相違点は視点位置入力手段6
が視点位置検出手段45に変わっている点である。
FIG. 6 is a block diagram showing a second embodiment according to the present invention. The difference from FIG.
Is replaced by the viewpoint position detecting means 45.

【0029】視点位置検出手段45は自動的にユーザの
視点位置を検出し、演算制御回路4に視点位置情報を入
力する。その他の動作は図1と同じであり、ユーザが視
点位置を入力する事なく、自動的に有限遠の視点から見
た時に生じる見かけの図形歪を低減できる効果がある。
The viewpoint position detecting means 45 automatically detects the viewpoint position of the user and inputs the viewpoint position information to the arithmetic and control circuit 4. Other operations are the same as those in FIG. 1, and there is an effect that the apparent graphic distortion generated when the user automatically sees from a finite distant viewpoint without inputting the viewpoint position can be reduced.

【0030】[0030]

【発明の効果】本発明のディスプレイでは有限遠の視点
から見た時に生じる見かけの図形歪を低減し、ユーザの
使用環境での表示品質を向上する事が出来る。
According to the display of the present invention, it is possible to reduce apparent graphic distortion generated when viewed from a finite distance viewpoint, and to improve display quality in a user's use environment.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による第1の実施例を示すブロック図。FIG. 1 is a block diagram showing a first embodiment according to the present invention.

【図2】見かけの図形歪の一例を示す説明図。FIG. 2 is an explanatory diagram showing an example of apparent graphic distortion.

【図3】本発明による第1の実施例をCRTディスプレ
イに適用した例のブロック図。
FIG. 3 is a block diagram of an example in which the first embodiment according to the present invention is applied to a CRT display.

【図4】図3の偏向回路及び図形歪発生回路の第1の例
を示す回路図。
FIG. 4 is a circuit diagram showing a first example of the deflection circuit and the graphic distortion generation circuit of FIG. 3;

【図5】図3の偏向回路及び図形歪発生回路の第2の例
を示す回路図。
FIG. 5 is a circuit diagram showing a second example of the deflection circuit and the graphic distortion generation circuit of FIG. 3;

【図6】本発明による第2の実施例を示すブロック図。FIG. 6 is a block diagram showing a second embodiment according to the present invention.

【符号の説明】[Explanation of symbols]

1…表示デバイス、 2…駆動回路、 3…図形歪発生回路、 4…演算制御回路、 5…メモリ、 6…視点位置入力手段、 12…水平偏向コイル、 31…垂直偏向コイル、 45…視点位置検出手段。 DESCRIPTION OF SYMBOLS 1 ... Display device, 2 ... Drive circuit, 3 ... Graphic distortion generation circuit, 4 ... Operation control circuit, 5 ... Memory, 6 ... Viewpoint position input means, 12 ... Horizontal deflection coil, 31 ... Vertical deflection coil, 45 ... Viewpoint position Detection means.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】表示面が湾曲した表示デバイスを用いたデ
ィスプレイにおいて、表示面から視点までの距離が有限
である時に発生する見かけの図形歪を低減する図形歪発
生回路を設けたことを特徴とするディスプレイ。
1. A display using a display device having a curved display surface, wherein a graphic distortion generation circuit is provided for reducing apparent graphic distortion generated when the distance from the display surface to the viewpoint is finite. Display.
【請求項2】請求項1において、視点位置入力手段と視
点位置に対しての図形歪発生データを保持しているメモ
リと演算制御回路を設け、視点位置を入力すれば自動的
に見かけの図形歪を低減するディスプレイ。
2. An apparatus according to claim 1, further comprising a viewpoint position input means, a memory for storing graphic distortion generation data for the viewpoint position, and an arithmetic control circuit. A display that reduces distortion.
【請求項3】請求項1において、視点位置検出手段と視
点位置に対しての図形歪発生データを保持しているメモ
リと演算制御回路を設け自動的に見かけの図形歪を低減
するディスプレイ。
3. The display according to claim 1, further comprising a viewpoint position detecting means, a memory for storing figure distortion occurrence data for the viewpoint position, and an arithmetic control circuit, wherein the apparent figure distortion is automatically reduced.
【請求項4】請求項1において、前記表示デバイスがブ
ラウン管であるディスプレイ。
4. The display according to claim 1, wherein said display device is a cathode ray tube.
JP18039396A 1996-07-10 1996-07-10 display Pending JPH1028232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18039396A JPH1028232A (en) 1996-07-10 1996-07-10 display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18039396A JPH1028232A (en) 1996-07-10 1996-07-10 display

Publications (1)

Publication Number Publication Date
JPH1028232A true JPH1028232A (en) 1998-01-27

Family

ID=16082460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18039396A Pending JPH1028232A (en) 1996-07-10 1996-07-10 display

Country Status (1)

Country Link
JP (1) JPH1028232A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006006641A1 (en) * 2004-07-12 2006-01-19 Sharp Kabushiki Kaisha Display device, vehicle, display method, display program, and display program storage medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006006641A1 (en) * 2004-07-12 2006-01-19 Sharp Kabushiki Kaisha Display device, vehicle, display method, display program, and display program storage medium

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