JPH10282943A - Pixel number converter - Google Patents

Abstract

(57) Abstract: A pixel number conversion device capable of reducing the capacity of an input buffer memory even when performing pixel number conversion for increasing the number of pixels. An input buffer memory (3) for storing an image signal in synchronization with a first cycle (T) and reading out the image signal in synchronization with a second cycle (T ') different from the first cycle (T), A pixel number conversion circuit 4 for generating an image signal having a different number of pixels with respect to the output read from the input buffer memory 3 in synchronization with T ′, and outputting the image signal output from the pixel number conversion circuit 4 in a second cycle An output buffer memory 5 for storing and reading in synchronization with T ', and a D / A converter 6 for converting an output read from the output buffer memory 5 in synchronization with the second period T' from a digital signal to an analog signal And

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel number conversion device for increasing or reducing the number of pixels of an image signal.

[0002]

2. Description of the Related Art As a device for displaying a personal computer (PC) or television broadcast screen, a CRT display,
There are a liquid crystal display and a plasma display.
In these displays, the number of pixels that can be displayed is limited depending on the performance, and is generally called resolution. For example, in a PC, VGA (640 × 480), SVGA
(800 × 600), XGA (1024 × 768), S
There are resolutions such as XGA (1280 × 1024).

On the other hand, when an image signal of a different resolution is to be displayed on a certain display, when the resolution of the display is higher than that of the image to be displayed, a black frame of a non-display portion occurs around the image to be displayed. When the resolution of the display is low with respect to the image to be displayed, all the image information cannot be displayed on one screen.

[0004] The pixel number conversion device is a means for eliminating the above-mentioned problem, and converts the number of pixels for input image signals having different resolutions to display an image on one screen. The pixel number conversion device makes it possible to efficiently display various images and video signals on a display device having a fixed resolution.

Conventionally, as such a pixel number conversion device,
For example, there is one shown in FIG.

FIG. 8 is a block diagram showing a configuration of a conventional pixel number conversion device.

In the figure, 1 is an image signal input terminal, 2 is an A / D converter, 3 is an input buffer memory, 4 is a pixel number conversion circuit, 5 is an output buffer memory, 6 is a D / A converter,
7 is an input buffer controller, 8 is an output buffer controller, 9 is an image signal output terminal, 10 is a PLL (Phase Locked Loop) circuit that generates a pixel rate cycle T (cycle 1) from a horizontal synchronization signal of the input image signal, and 11 is A horizontal synchronizing signal input terminal 12 for an input image signal is a sample period T '(period 2) input terminal for an output image signal.

Next, the operation will be described.

An analog image signal is input to an image signal input terminal 1, and a horizontal synchronization signal corresponding to the image signal is input to a horizontal synchronization signal input terminal 11. The PLL circuit 10 generates a pixel rate signal (period 1) having a period T synchronized with the input image signal. Here, the pixel rate signal refers to a clock (CLK) signal synchronized with the input signal. A / D converting the input signal with this clock CLK,
That is, since the conversion result becomes each pixel data of the image signal, it is called a pixel rate.

The analog image signal is converted into a digital image signal by the A / D converter 2 using a clock (CLK) signal having a pixel rate period T, and is then taken into the input buffer memory 3 under the control of the input buffer controller 7. . The input buffer controller 7 controls the input buffer memory 3 by a control signal (not shown) so that writing can be performed in synchronization with the output of the A / D converter 2.

Thereafter, the output of the input buffer memory 3 is input to the pixel number conversion circuit 4, and the pixel number conversion circuit 4 performs a pixel number conversion process.

Here, when actually writing data to the input buffer memory 3, the write data (output of the A / D converter 2) and the input buffer memory 3 cannot be operated independently. Further, in order to perform write or read access to the input buffer memory 3, a control signal such as a write enable and an address is required. Therefore, the input buffer controller 7 controls the A / D
Control is performed such that writing to the input buffer memory 3 can be performed in synchronization with the output of the converter 2. For the same reason, the output buffer controller 8 also supplies a control signal to the output buffer memory 5.

The above-described pixel number conversion processing will be described with reference to FIG.

FIG. 9 is a block diagram showing a schematic configuration of the pixel number conversion circuit 4. As shown in FIG.

The pixel number conversion circuit 4 generates a signal whose number of pixels is L / M times (L and M are natural numbers) from a signal having a pixel rate cycle T of the signal. It consists of a porator and a decimator for reducing the number of pixels to 1 / M times. When performing digital signal processing, it is necessary to change the data sample rate in order to directly transfer data between blocks having different sampling frequencies. In that case, the interpolator increases the sampling frequency, and the decimator decreases the sampling frequency.

Actually, in the figure, a zero-interpolation block 41 for interpolating (L-1) data 0 (zero) between each data of the pixel rate period T, a low-pass filter (LP)
F) 42, Μ of the number of pixels multiplied by L in the zero interpolation block 41
It comprises a thinning block 43 for thinning out one for each sample.

The LPF 42 is generally made of a FIR (Finite Imp
This is realized by a (ulse response) filter, and is used for calculating data of a zero-interpolated part at the time of interpolation and preventing aliasing at the time of decimation. The characteristics of the LPF are H when interpolated.
1 (z), the transfer function represented by H2 (z) is required at the time of decimating.
(Z) is H (z) = H1 (z) · H2 (z).

The image signal data of Ν number of pixels input to the pixel number conversion circuit 4 is multiplied by L in the zero interpolation block 41 to obtain the number of pixels (N × L). After the calculation, the number of pixels is reduced to 1 /
M, and the output is the desired number of pixels (Ν ×
L) / M image signal data are obtained.

Returning to FIG. 8, the output of the pixel number conversion circuit 4 is
The data is taken into the output buffer memory 5 under the control of the output buffer controller 8. Output buffer controller 8
Controls the write data and the write operation of the output buffer memory 5 in synchronism with the input buffer controller 7. In particular, when the number of pixels is reduced (the number of input pixels> the number of output pixels), the data Data writing is controlled in consideration of the fact that the data is not always output from the number conversion circuit 4 and the writing timing to the output buffer memory 5 may be random.

The conversion of the number of pixels has been completed when the data is taken into the output buffer controller 8. However, if the processing up to this point is performed at the pixel rate period T of the input image signal, the number of pixels is reduced. In this case, the blanking period becomes longer, and when the number of pixels is increased, the output data has a larger number of pixels. Therefore, normal display cannot be performed at the same pixel rate.
It is necessary to change the cycle of reading data from the memory.

Assuming that one vertical cycle does not change at the input / output of the pixel number conversion circuit 4, when the number of pixels increases, the sample period T '= τ shorter than the pixel rate period T of the input signal data.
(T> τ), the data is read out from the output buffer memory 5 at the sampling period T ′ = τ ′ (T <τ ′) longer than the pixel rate period T at the time of reduction, and the D / A converter 6 The analog image signal is converted to D /
After the A conversion, it is output from the image signal output terminal 7.

The number of pixels and the sampling period of the image signal can be changed by using the pixel number converter operating as described above.

[0023]

Since the conventional pixel number conversion device is configured as described above, when the number of pixels is increased, the required capacity of the input buffer memory increases as the rate of increase increases. There was a problem of becoming.

That is, as shown in FIGS. 10 and 11, when the number of pixels is increased, the number of output pixels of the pixel number conversion device is larger than the number of input pixels. Data reading is intermittent. More specifically, when the number of pixels is increased by the pixel number conversion circuit 4, it takes time to execute a process for increasing the number of pixels, and theoretically a time difference of (the number of output pixels−the number of input pixels) is required. Occurs. Actually, since the time difference is dispersed by using the input buffer memory 3 and reading from the input buffer memory 3 is controlled in accordance with a request from the pixel number conversion circuit 4, data reading is intermittent.

When the number of pixels is increased, the number of output pixels of the pixel number conversion circuit 4 becomes larger than the number of input pixels, and a time difference corresponding to the difference between the number of output pixels and the number of input pixels occurs as shown in FIG. There is no input signal data corresponding to this time difference, which is generated by increasing the number of pixels in the pixel number conversion circuit 4. Actually, as shown in FIG. 10, the reading of data from the input buffer memory 3 becomes intermittent rather than one-to-one for each input pixel, and the time difference is dispersed. In order to absorb the time difference, when the number of pixels increases in the horizontal direction, a line memory is required for the input buffer. Further, since the image signal is a two-dimensional signal, and in order to increase the number of lines not only in the horizontal direction but also in the vertical direction, it is necessary to hold at least one line or more of data, Frame memory must be used.

Therefore, there is a problem that the larger the rate of increase in the number of pixels, the more memory is required.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to reduce the capacity of the input buffer memory even when performing pixel number conversion for increasing the number of pixels. It is intended to obtain a conversion device.

[0028]

According to a first aspect of the present invention, there is provided a pixel number conversion apparatus for increasing or reducing the number of pixels of an image signal, wherein a first period is calculated from a horizontal synchronization signal of an input image signal. Means for generating a sample frequency, converting means for converting an image signal from an analog signal to a digital signal in synchronization with the first cycle, storing the image signal in synchronization with the first cycle, A first memory that reads out an image signal in synchronization with a different second cycle and an image signal with a different number of pixels is generated based on an output read from the first memory in synchronization with the second cycle. A pixel number conversion unit, a second memory that stores and reads an image signal output from the pixel number conversion unit in synchronization with the second cycle, and a second memory that is read out from the second memory unit in synchronization with the second cycle. Output from digital signal to analog signal It is obtained by a means for converting.

According to a second aspect of the present invention, there is provided a pixel number conversion device including a first memory, a second memory, and switching means for switching between a first cycle and a second cycle supplied to the pixel number conversion means. .

According to a third aspect of the present invention, there is provided an apparatus for converting the number of pixels, comprising: first switching means for switching the input of a plurality of image signals; and second switching means for switching the output of the image signal after the number of pixels has been converted. It is.

According to a fourth aspect of the present invention, there is provided a pixel number conversion device including control means for controlling an output destination and a display position of a plurality of video signals read from the second memory.

A pixel number conversion device according to a fifth aspect of the present invention includes an address control means for controlling an address of data stored in the first memory, and controls an address by the address control means to control a portion of the number of pixels of the input image signal. It is designed to reduce or increase in size.

[0033]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
The present invention will be specifically described.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of a pixel number conversion device according to Embodiment 1 of the present invention. In the description of the pixel number conversion device according to the first embodiment, the same components as those of the pixel number conversion device shown in FIG. 8 are denoted by the same reference numerals.

In the figure, 1 is an image signal input terminal, 2 is an A / D converter, 3 is an input buffer memory (first memory), 4 is a pixel number conversion circuit (pixel number conversion means), and 5 is an output buffer. A memory (second memory), 6 is a D / A converter, 7 is an input buffer controller, 8 is an output buffer controller, 9 is an image signal output terminal, and 10 is a pixel rate period T ( PLL (Phase Locked Loop) circuit that generates period 1), 1
1 is a horizontal synchronizing signal input terminal of the input image signal, and 12 is a sample period T '(period 2) input terminal of the output image signal.

In particular, the pixel number conversion apparatus according to the first embodiment is the same as the conventional example shown in FIG. 8 except that the period supplied to the output buffer memory 5 and the D / A converter 6 as the sampling period of the output image signal is used. T ′ (cycle 2) is also supplied to the input buffer memory 3 and the pixel number conversion device 4, and when the number of pixels increases, the input buffer memory 3 stores the image signal in synchronization with the cycle T, and synchronizes with the cycle T ′. The pixel number conversion circuit 4 generates an image signal having a different number of pixels for the output read from the input buffer memory 3 in synchronization with the cycle T ′. I have.

Hereinafter, the operation of the pixel number conversion device configured as described above will be described.

The pixel number conversion device according to the present embodiment converts the sample period in the output buffer memory 5 in the same manner as in the conventional example when the number of pixels is reduced, and the preceding stage of the pixel number conversion circuit 4 when the number of pixels is increased. The capacity of the input buffer memory is reduced by changing the sample period input to the input buffer memory 3 between the time of writing data to the input buffer memory 3 and the time of reading data.

The case where the number of pixels is reduced is the same as that of the conventional example, so that the description is omitted, and the operation when the number of pixels is increased will be described.

First, an image signal of an analog waveform is input to an image signal input terminal 1 and is converted into a digital signal by an A / D converter 2 at a pixel rate period T of the input image signal.
After the conversion, the input image signal is once taken into the input buffer memory 3 at the pixel rate period T of the input image signal. PL
The L circuit 10 generates a pixel rate signal (period 1) having a period T synchronized with the input image signal. Further, a sample period T ′ of the output image signal is input from the period 2 input terminal 12.

When the number of pixels is to be increased, data is read from the input buffer memory 3 at the sampling period T 'of the output image signal after the conversion of the number of pixels, and the read data is input to the pixel number conversion circuit 4 to be read. Processing is performed at the sampling period T ′ of the output image signal. As a result, as shown in FIG. 2, the processing of one line of the output image signal can be performed in the time of one line of the input image signal.
Can use a buffer memory for one line. This effect will be described later in detail.

The output data of the pixel number conversion circuit 4 is taken into the output buffer memory 5 and sequentially read. The operation at this time is performed at the sampling period T 'of the output image signal for both writing and reading.

Thereafter, the image data is converted into an analog signal again by the D / A converter 6 at the sampling period T 'of the output image signal.
It is possible to obtain an image signal in which the number of pixels and the sampling period are converted by the A / A conversion and the output terminal 9.

The pixel rate period T of the input image signal
And the sample period T ′ of the output image signal will be described in more detail.

Generally, the period T depends on the resolution of the monitor of the input signal, and the period T ′ depends on the resolution of the monitor to be output. For example, when the VGA input is to be converted to the XGA output, the VESA (Video) Electronics Stan
dard Associate), the period T is about 39.7.
ns (= 1 / 25.175 MHz), and the period T ′ is about 15.4 ns (= 1 / 65.000 MHz). However, since these periods include a blanking period, it is theoretically possible to perform processing at a slightly longer period (low clock), and if the vertical frequency is constant for input and output, (The number of input pixels in one frame) × T ≧
T such that (the number of input pixels in one frame) × T ′ is satisfied;
T 'may be determined.

The input buffer controller 7 writes data to the input buffer memory 3 at the above-mentioned cycle T and reads data at the above-mentioned cycle T ′. Do.

As described above, the pixel number conversion device according to the first embodiment stores an image signal in synchronization with the first period T and sets the image signal in the second period T ′ different from the first period T. An input buffer memory 3 for reading out an image signal in synchronization with a pixel number conversion circuit 4 for generating an image signal having a different number of pixels for an output read out from the input buffer memory 3 in synchronization with a second period T ' And an output buffer memory 5 for storing and reading out the image signal output from the pixel number conversion circuit 4 in synchronization with the second period T ′, and reading out the image signal output from the output buffer memory 5 in synchronization with the second period T ′. And a D / A converter 6 for converting the output from the digital signal into an analog signal. The input buffer memory 3 converts the sample period to perform the pixel number conversion process when the number of pixels increases. Can be done in It becomes possible to reduce the capacity of the input buffer memory.

That is, in the first embodiment, the number of pixels is increased by changing the value of the clock CLK for writing image signal data to the input buffer memory 3 and the value of the clock CLK for reading data from the input buffer memory 3. The processing time for one line of data at that time is shortened. For example, the first cycle T = 39.7 ns (2
5.175 MHz) for the second period T '= 15.4 ns
(65 MHz). In this manner, even if the number of pixels increases and the time required for processing becomes necessary, the clock CL for reading data from the input buffer memory 3 is used.
By changing K to the cycle T ′, the time required for reading data and converting the number of pixels can be shortened, and the processing time can be reduced as compared with the case where processing is performed using the clock CLK having the cycle T. If the pixel number conversion process can be completed during the 1H period, the capacity of the memory for storing the next data may be a line memory capable of storing one line of pixel data. Therefore, the memory capacity can be reduced as compared with the conventional device.

Further, since the present invention can be implemented without changing the hardware configuration of the conventional pixel number conversion device, there is no increase in cost.

Embodiment 2 FIG. 3 is a block diagram of a pixel number conversion device according to Embodiment 2 of the present invention. In addition,
FIG. 1 illustrates the pixel number conversion device according to the second embodiment.
The same components as those of the pixel number conversion device shown in FIG.

Since the pixel number conversion device according to the second embodiment can cope with the reduction of the number of pixels in addition to the operation of increasing the number of pixels of the first embodiment, the pixel number conversion circuit 4 and the input circuits at the preceding and succeeding stages are provided. The operation cycle of the buffer memory 3 and the output buffer memory 5 can be switched.

In the figure, 1 is an image signal input terminal, 2 is an A / D converter, 3 is an input buffer memory, 4 is a pixel number conversion circuit, 5 is an output buffer memory, 6 is a D / A converter,
7 is an input buffer controller, 8 is an output buffer controller, 9 is an image signal output terminal, 10 is a PLL circuit that generates a pixel rate period T (cycle 1) from a horizontal synchronization signal of the input image signal, and 11 is a horizontal line of the input image signal. A synchronization signal input terminal 12 is a sample period T 'of the output image signal.
(Period 2) Input terminal, 13 is a switching signal input terminal for inputting a switching signal for increasing / decreasing the number of pixels, and 14 is an input terminal switching switch for switching between Period 1 and Period 2 according to the switching signal.

In the above configuration, a switching signal is input to the switching signal input terminal 13 to switch the input terminal switch 14 depending on whether the number of pixels is to be increased or reduced, and the read cycle of the input buffer memory 3 and the conversion of the number of pixels are changed. The operation cycle of the circuit 4 and the write cycle of the output buffer memory 5 can be switched.

When the number of pixels is increased, the same operation as in the first embodiment is performed. When the pixel is reduced, the same operation as in the conventional example is performed. Becomes possible.

As described above, the pixel number conversion device according to the second embodiment includes a switching signal input terminal 13 for inputting a switching signal for increasing and reducing the number of pixels, and an input terminal switching switch for switching between the period T and the period T ′. 14 is provided so that the operation cycle of the pixel number conversion device can be switched depending on whether the number of pixels is increased or reduced, so that the number of pixels can be increased or reduced with one pixel number conversion device having a small-capacity input buffer. Either process becomes possible.

Embodiment 3 FIG. 4 is a block diagram showing a configuration of the pixel number conversion device according to the first embodiment of the present invention. In the description of the pixel number conversion device according to the third embodiment, the same components as those of the pixel number conversion device shown in FIGS. 1 and 3 are denoted by the same reference numerals, and the same reference numerals having different subscripts use the same type of parts. To indicate that

The pixel number conversion device according to the third embodiment is configured to perform time-division input when converting the number of pixels of a plurality of inputs, and to perform the pixel number conversion processing at a sufficiently high operation speed.

In the drawing, reference numerals 1a to 1n denote image signal input terminals to which different image signals are input, 2a to 2n denote A / D converters, 3a to 3n denote input buffer memories, 4 denotes a pixel number conversion circuit, and 5a to 5n. 5n is an output buffer memory, 6
a to 6n are D / A converters, 7 is an input buffer controller, 8 is an output buffer controller, 9a to 9n are image signal output terminals, and 10 is a pixel rate period T (period 1) from a horizontal synchronization signal of an input image signal. A PLL circuit 11 generates a horizontal synchronizing signal input terminal for an input image signal.
Is an input terminal of a sample period T '(period 2) of an output image signal, 15 is a multiplexer (first switching means) for selecting one of n channels, and 16 is one input of one of n channels. Demultiplexer (second switching means) for output to the multiplexer 17, a multiplexer selection signal input terminal for controlling the multiplexer 15 and the demultiplexer 16, and a delay circuit 18 for providing a delay equal to the time required for the processing of the pixel number conversion circuit 4. , 19 is the period T "
This is a cycle 3 signal input terminal for inputting (cycle 3).

The period T ″ (period 3) corresponds to the periods Ta to Tn of the image signals input to the respective channels and the periods Ta ′ to Ta of the image signals output from the image signal output terminals 9a to 9n.
The period is sufficiently shorter than Tn '.

Each cycle T, T ′, T ″ is set at each input terminal 1
1, 12, and 19, or may be generated by another circuit. In the third embodiment, the PLL circuit 10 generally generates the cycle T corresponding to the CLK of the input signal in consideration that the cycle T is not transmitted together with the video signal. The period T 'may be a time sufficient to execute the pixel number conversion time division processing of each channel, and an input from a fixed period oscillator such as XTAL or VCO is used. The period T "depends on the specifications of the apparatus because it depends on the display device. However, the same method as the period T or the period T 'can be used, or an external input may be used.

The multiplexer selection signal input terminal 1
7 is a signal for selecting and switching on which display device the input signal input to the image signal input terminals 1a to 1n is to be displayed.
As in the case of T ′ and T ″, another circuit may be internally provided, or an external signal may be input.

The multiplexer 15 switches the signal to be processed by the pixel number conversion circuit 4 according to the channel selection signal.

The demultiplexer 16 switches the device for displaying the signal after the pixel number conversion according to the channel selection signal delayed by the time corresponding to the processing of the pixel number conversion circuit 4 by the delay circuit 18.

In the pixel number conversion device according to the third embodiment,
In the pixel number conversion device according to the second embodiment, the pixel number conversion circuit 4 is operated in a sufficiently short cycle, and the image signal input for n channels (n is an integer of 2 or more) is switched to perform time division. By performing numerical conversion, image signals of a plurality of channels can be processed.

As an image signal of a plurality of channels, for example, a two-screen display is used. The image conversion of the image signals of a plurality of channels is executed according to the specified display size specification rather than the resolution of the display device. 2 horizontally
When it is desired to display a screen, it is necessary to reduce the number of pixels of both input images to be input on two screens in the horizontal direction by half. In order to realize this, a plurality of pixel number conversion circuits for performing pixel number conversion for each channel input may be prepared, but in the third embodiment, the operating frequency of one pixel number conversion circuit 4 is sufficiently increased. By increasing the value, the pixel number conversion of each channel is time-divisionally processed.

Using the circuit shown in FIG. 4, for example,
(1) (2) becomes possible.

(1) A plurality of video signals can be input and displayed on one monitor (display device).
In this case, when a plurality of video signals input to the circuit shown in FIG. 4 are displayed on one display device, the position where each video signal is displayed on the monitor is designated by the address by the output buffer controller 8. You can decide freely.

(2) A plurality of input video signals can be output to a plurality of display devices.

Hereinafter, the operation of the pixel number conversion device configured as described above will be described.

When displaying images of a plurality of channels on one screen, images having different resolutions or images having the same resolution but different display sizes may be displayed. For example,
There is a case where an NTSC small screen is displayed on a PC screen, or a screen is divided into a plurality of sections (for example, divided into four or nine) to display different images on each screen.

In such a case, the above-mentioned image signals are input to the image signal input terminals 1a to 1n, A / D converted for each channel, and are once taken into the input buffer memories 3a to 3n.

Reading from the input buffer memories 3a to 3n, processing in the pixel number conversion circuit 4, and writing to the output buffer memories 5a to 5n are performed in accordance with the periods Ta to Tn of the image signals input to the respective channels and the output of the image signals. Terminal 9a ~
9n is operated at a period T ″ (period 3) that is sufficiently shorter than the periods Ta ′ to Tn ′ of the image signals output from 9n. FIG. 5 shows this state.

FIG. 5 is a conceptual diagram showing a method of time-division pixel number conversion processing.

The image signal data held in the input buffer memories 3a to 3n is time-divisionally switched by the multiplexer 15 in accordance with the signal input from the channel selection signal terminal 17 and sequentially input to the pixel number conversion circuit 4, In the number conversion circuit 4, the output of the pixel number conversion circuit 4 is similarly switched by the multiplexer 16 according to the channel selection signal and written in the output buffer memories 5a to 5n. At this time, assuming that each channel is processed in units of frames, it is necessary that the time required to process all channels, {Kxｘ} ”, be shorter than any of the frame periods of each channel.

The output from the output buffer memories 5a to 5n to the video signal output terminals 9a to 9n can be performed at the sampling periods Ta 'to Tn' required for each output channel. In step 4, pixel number conversion processing can be executed in real time for a plurality of inputs having different resolutions and video sources. When a plurality of screens are displayed on one display device, the sample periods Ta 'to Tn' are periods corresponding to the one display device, and have only one common value. When an input video (which may be common or plural) is displayed on a plurality of displays having different resolutions, the period T ′ differs depending on the display device, and is therefore a period corresponding to each display. Are expressed as periods Ta ′ to Tn ′.

The selection of the channel for executing the pixel number conversion process is performed by the multiplexer 15 and the demultiplexer 16 according to the channel selection signal. The third embodiment is an example in which an input signal and an output display device from which the input signal is output have a one-to-one correspondence, and one frame of data of each channel is transmitted within a certain fixed period. Will be processed. If the multiplexer 15 and the demultiplexer 16 supply independent channel selection signals, a high degree of freedom in displaying one channel input signal on a plurality of displays becomes possible.

The output destination and output position of a plurality of video signals output from the pixel number converter are controlled by the output buffer controller 8.

As described above, the pixel number converter according to the third embodiment includes a multiplexer 15 for selecting one of n-channel inputs and a demultiplexer for outputting one input to one of n channels. 16, a multiplexer selection signal input terminal 17 for controlling the multiplexer 15 and the demultiplexer 16, a delay circuit 18, and a cycle 3 signal input terminal 19 for inputting a cycle T ″ (cycle 3). Since the processing is performed, a plurality of input image signals can be switched, and a plurality of input pixel number conversion processing can be executed by one pixel number conversion device.

Embodiment 4 FIG. 6 is a block diagram of a pixel number conversion device according to Embodiment 4 of the present invention. In addition,
FIG. 1 illustrates the pixel number conversion device according to the fourth embodiment.
The same components as those of the pixel number conversion device shown in FIG. 3 are denoted by the same reference numerals, and the description of the overlapping portions will be omitted.

The pixel number conversion device according to the fourth embodiment controls the write address or the read address to the input buffer memory 3 when increasing or reducing the number of pixels of an image signal in the second embodiment. Thus, the number of pixels of the input image can be partially increased or reduced.

In the figure, 1 is an image signal input terminal, 2 is an A / D converter, 3 is an input buffer memory, 4 is a pixel number conversion circuit, 5 is an output buffer memory, 6 is a D / A converter,
7 is an input buffer controller, 8 is an output buffer controller, 9 is an image signal output terminal, 10 is a PLL circuit that generates a pixel rate period T (cycle 1) from a horizontal synchronization signal of the input image signal, and 11 is a horizontal line of the input image signal. A synchronization signal input terminal 12 is a sample period T 'of the output image signal.
(Cycle 2) input terminal, 13 is a switch signal input terminal for inputting a switch signal for increasing / decreasing the number of pixels, 14 is an input terminal switch for switching between cycle 1 and cycle 2 by a switch signal, 2
Reference numeral 0 denotes an address control circuit of the input buffer memory provided in the input buffer controller 7.

The address control circuit 20 controls a write address or a read address to the input buffer memory 3 when increasing or reducing the number of pixels of an image signal. In the fourth embodiment, the address control of the input buffer memory 3 is performed. However, by installing a similar address control circuit in the output buffer controller 8, the write and read addresses of the input buffer memory 3 and the output buffer memory 4 can be controlled. Alternatively, the number of pixels to be processed by the pixel number conversion circuit 4 or the conversion rate may be designated.

In the above configuration, the pixel number conversion is normally performed for all the image signals of one frame as in the second embodiment, but the address control circuit 20 accesses the input buffer memory 3 when writing or reading. The number of pixels can be converted by controlling only a part of the image signal. This allows, for example, a partial increase or reduction of the input image.

FIG. 7 is a diagram for explaining an example of partial enlargement / reduction. The image of the input signal at the upper left of FIG. 7 is partially enlarged / reduced to an arbitrary position as shown in the figure by controlling the address to be accessed at the time of writing to or reading from the input buffer memory 3 by the address control circuit 20. Can be displayed.

The write and read addresses of the input buffer memory 3 and the output buffer memory 4 and the number of pixels to be processed by the pixel number conversion circuit 4 or the conversion rate are designated. When such a partial enlargement / reduction process is performed, it is basically the same as the full size process described in each of the above embodiments, and a desired offset is set in the start address specification of the input / output buffer memory. Another difference is that the access size is changed. Here, in order to perform partial enlargement / reduction of a certain input signal, and to process the parent screen and the child screen in real time, a combination with the third embodiment is required.

As described above, in the pixel number conversion device according to the fourth embodiment, since the address control circuit 20 is provided in the input buffer controller 7 to control the address, the image signal data is partially input. Can be
The input image signal can be partially enlarged or reduced.

Note that the pixel number conversion device according to each of the above embodiments can be applied to, for example, a pixel number conversion device of a wide aspect television receiver. It is needless to say that the present invention can be applied to any video device as long as it is a pixel number conversion device.

Further, it goes without saying that the type, number, connection state, and the like of, for example, a buffer memory and a line memory constituting the pixel number conversion device are not limited to the above-described embodiments.

[0089]

According to the first aspect of the present invention, there is provided a first pixel number conversion device which stores an image signal in synchronization with a first cycle and reads out the image signal in synchronization with a second cycle different from the first cycle. , A pixel number conversion means for generating image signals having different numbers of pixels based on an output read from the first memory in synchronization with the second cycle, and an image signal output from the pixel number conversion means A second memory for storing and reading the data in synchronization with the second cycle, and means for converting an output read from the second memory means in synchronization with the second cycle from a digital signal to an analog signal. Since the first memory converts the sample period, the pixel number conversion process when the number of pixels is increased can be performed in the output sample period, and the memory can be reduced in capacity.

In the pixel number conversion device according to the second aspect, the first
And a switching means for switching between the first cycle and the second cycle to be supplied to the memory, the second memory, and the pixel number converting means, so that one pixel number converting apparatus having a small-capacity input buffer memory can be used. This has the effect of enabling either the process of increasing or reducing the number of pixels.

[0091] The pixel number conversion device according to the third aspect is provided with a first switching means for switching the input of a plurality of image signals and a second switching means for switching the output of the image signal after the pixel number conversion. Therefore, there is an effect that the pixel number conversion processing of the image signals of a plurality of channels can be performed by one pixel number conversion device.

In the pixel number conversion device according to the fourth aspect, the second
Control means for controlling the output destinations and display positions of a plurality of video signals read from the memory of the display device, so that when displaying a plurality of input video signals on one display device, each video signal is monitored. There is an effect that the position displayed above can be freely determined.

In the pixel number conversion device according to claim 5, the first
Address control means for controlling the address of the data stored in the memory, and the address control means controls the address to partially reduce or increase the number of pixels of the input image signal. An effect that partial input can be performed and an input image signal can be partially enlarged or reduced is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a pixel number conversion device according to a first embodiment of the present invention;

FIG. 2 is a diagram for explaining processing time of the pixel number conversion device according to the first embodiment of the present invention;

FIG. 3 is a block diagram illustrating a configuration of a pixel number conversion device according to a second embodiment of the present invention;

FIG. 4 is a block diagram illustrating a configuration of a pixel number conversion device according to a third embodiment of the present invention;

FIG. 5 is a diagram for explaining a time-division pixel number conversion processing method of the pixel number conversion device according to the third embodiment of the present invention;

FIG. 6 is a block diagram illustrating a configuration of a pixel number conversion device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram for explaining an example of partial enlargement / reduction of a pixel number conversion device according to a fourth embodiment of the present invention;

FIG. 8 is a block diagram illustrating a configuration of a conventional pixel number conversion device.

FIG. 9 is a block diagram illustrating a configuration of a pixel number conversion circuit of a conventional pixel number conversion device.

FIG. 10 is a timing chart showing the operation of a conventional pixel number conversion device.

FIG. 11 is a diagram for explaining the processing time of a conventional pixel number conversion device.

[Explanation of symbols]

1 image signal input terminal, 2 A / D converter, 3 input buffer memory (first memory), 4 pixel number conversion circuit (pixel number conversion means), 5 output buffer memory (second memory), 6 D / A converter, 7 input buffer controller, 8 output buffer controller, 9 image signal output terminal, 10 PLL circuit,
11 horizontal synchronizing signal input terminal, 12 period T '(period 2) input terminal, 13 switching signal input terminal, 14 input terminal switching switch, 15 multiplexer, 16
Demultiplexer, 20 address control circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/14 G06F 15/66 355F

Claims (5)

[Claims] 1. A pixel number conversion device for increasing or reducing the number of pixels of an image signal, comprising: means for generating a sample frequency serving as a first cycle from a horizontal synchronization signal of an input image signal; Means for synchronously converting an image signal from an analog signal to a digital signal; storing the image signal in synchronization with the first cycle;
A first memory for reading an image signal in synchronization with a second cycle different from the cycle of the first cycle; and a different number of pixels based on an output read from the first memory in synchronization with the second cycle. A pixel number conversion unit that generates an image signal; a second memory that stores and reads an image signal output from the pixel number conversion unit in synchronization with the second cycle; Means for converting an output read from the second memory means from a digital signal to an analog signal. 2. A switching means for switching between the first cycle and the second cycle supplied to the first memory, the second memory, and the pixel number conversion means. 2. The pixel number conversion device according to 1. 3. A first method for switching input of a plurality of image signals.
3. The pixel number conversion device according to claim 1, further comprising: a switching unit for switching the output of the image signal after the pixel number conversion. 4. The pixel according to claim 1, further comprising control means for controlling an output destination and a display position of the plurality of video signals read from the second memory. Number converter. 5. An address control means for controlling an address of data stored in the first memory, wherein the address control means controls an address to partially reduce or increase the number of pixels of an input image signal. 3. The pixel number conversion device according to claim 2, wherein: