JPH10284672A - Lead frame for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the influences upon a wire bonding process, such as breakages of bonding decline in bondability between a bonding wire and an inner lead, etc., by a method, wherein easy-to-deform parts which are easier to deform than the other parts of inner lead tip parts are formed in downset parts. SOLUTION: A neck 21 in the width direction of an inner lead 1 is formed in the downset part 10 of the inner lead 1 for making the deforming force of the downset part 10 smaller than that of the other part. Therefore, when downset depths are relatively large, even if a semiconductor chip 5 is pressed against a jig 4 and a force which pushes up the downset parts 10 of the inner leads 1 to produce an inclination tends to be applied, the necks 21 which are formed in the downset parts 10 of the inner leads 1 in the width direction of the inner lead 1 are deformed and absorb a force pushing up the downset parts 10 in a thickenss direction to make an inclination. With this constitution, the inclination of the bonding plane 11 of the inner lead 1 can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device on which a semiconductor chip (hereinafter, referred to as an IC) is mounted. The present invention relates to a semiconductor device lead frame that can reduce the influence on a wire bonding step.

[0002]

2. Description of the Related Art Conventionally, in an IC package, a flat portion called an island is provided at a central portion of a lead frame.
A semiconductor chip is mounted on this unland. For this reason, the size of the IC package must be larger than the size of the semiconductor chip. However, with the spread of portable electronic devices or the increase in demand in recent years, it is required to reduce the size of IC packages used for such electronic devices. In order to respond to this requirement, an inclined downset processing portion is formed at the tip of the inner lead in the lead frame, and the semiconductor chip is bonded to the surface opposite to the wire bonding surface with an insulating adhesive film. 2. Description of the Related Art A lead frame for a semiconductor device having a LOC (Lead on Chip) structure for miniaturizing a package is used.

FIG. 3 shows the structure of a lead frame for a semiconductor device having the LOC structure. As shown in the figure, an insulating film 2 having an adhesive property is provided on a surface opposite to a bonding surface 11 of an inner lead 1 on which a downset processing portion 10 is formed.
Is provided, the semiconductor chip 5 is bonded, and the semiconductor chip 5 is positioned while the inner lead 1 is positioned by the jig 3.
And the bonding surface 11 of the inner lead 1 and the semiconductor chip 5 are bonded by bonding wires 6.

[0004]

However, according to the conventional lead frame for a semiconductor device having a LOC structure, when the downset amount of the downset processing portion 10 is processed to be deeper than a prescribed amount, the wire bonding process is performed. Since the inner lead 1 presses the semiconductor chip 5 against the jig 4, the downset portion 10 of the inner lead 1 is given an undesired inclination.

[0005] That is, if the downset amount is deep, the jig (die) is used when the semiconductor chip 5 is wire-bonded.
4, the tip of the inner lead 1 is pushed up, and a force that causes the downset processing portion 10 to tilt acts. When the tilt occurs, for example, FIG.
As shown in FIG. 5, the capillary 7 for supplying the bonding wire 6 comes in contact with the downset processing section 10 of the inner lead 1, and the bonding wire 6 is torn. As shown in FIG. An interval larger than the specified interval is generated between the bonding wire 6 and the inner lead 1, which has a significant effect on wire bonding, such as a decrease in bondability between the bonding wire 6 and the inner lead 1.

[0006]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a lead frame for a semiconductor device which can reduce the influence on a wire bonding process such as a breakage of a bonding wire or a decrease in bonding property between a bonding wire and an inner lead. It is in.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor device lead formed by forming a downset processing portion at the tip of an inner lead and bonding the tip to a semiconductor chip. In the frame, the downset processing portion is provided with a lead frame for a semiconductor device, wherein an easily deformable portion that is easier to deform than other portions of the distal end portion is formed.

In this case, the easily deformable portion is preferably a constriction formed in a width direction of the inner lead, and is preferably a constriction formed in a thickness direction of the inner lead.

[0009]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIGS. 1A, 1B and 1C show a lead frame for a semiconductor device according to an embodiment of the present invention.
The same parts as those in FIG. 3 are denoted by the same reference numerals and symbols, and thus redundant description will be omitted. However, in this embodiment, as shown in FIG. A constriction 21 is formed in the downset processing portion 10 in the width direction of the inner lead 1 so as to form the downset processing portion 1.
The difference from the conventional LOC structure lead frame for a semiconductor device is that the zero deformation force is smaller than that of the other parts.

According to the lead frame for a semiconductor device, when the downset amount is deep, the semiconductor chip 5 is pressed against the jig 4 to push up the downset processing portion 10 of the inner lead 1 to generate a tilting force. However, the constriction 21 formed in the downset processing portion 10 in the width direction of the inner lead 1 is deformed,
The force which pushes down set processing section 10 in the thickness direction to tilt it is absorbed.
Of the bonding surface 11 is suppressed.

FIGS. 2A, 2B and 2C show another example of a semiconductor device lead frame according to an embodiment of the present invention. 1 (a), 1 (b), and 1 (c) are denoted by the same reference numerals and symbols, and duplicate description will be omitted. However, according to this example, FIG. As shown in an enlarged manner, the downset processing portion 1 of the inner lead 1
0 is characterized in that a constriction 22 is formed in the thickness direction of the inner lead 1.

According to the lead frame for a semiconductor device, similarly to the lead frame for a semiconductor device shown in FIG. 1, the downset processing portion 10 of the inner lead 1 having the constriction 22 is deformed, and It absorbs a force that pushes the processed portion 10 in the plate thickness direction to tilt it, and suppresses the tilt of the bonding surface 11 of the inner lead 1.

In the above embodiment, the constriction in the width direction of the inner lead provided in the downset portion can be formed simultaneously with the punching of the lead frame. The constriction in the thickness direction can be formed by cutting, etching, or the like. However, the easily deformable structure formed in the downset processing portion is not limited to this.

[0015]

As described above, according to the lead frame for a semiconductor device of the present invention, an easily deformable portion which is more easily deformed than the other portion of the tip of the inner lead is formed in the downset portion. Therefore, it is possible to reduce the influence on the wire bonding process, such as the tearing of the bonding wire and the deterioration of the bonding property between the bonding wire and the inner lead.

[Brief description of the drawings]

1A and 1B show a semiconductor device lead frame according to an embodiment of the present invention, wherein FIG. 1A is a schematic cross-sectional view, FIG. 1B is a plan view thereof, and FIG. is there.

2A and 2B show another example of a semiconductor device lead frame according to the embodiment of the present invention, wherein FIG. 2A is a schematic cross-sectional view, and FIG.
Is a plan view thereof, and (c) is a partially enlarged view of a downset processing portion.

FIG. 3 is a view showing a conventional lead frame for a semiconductor device.

FIG. 4 is a view showing a problem of a conventional lead frame for a semiconductor device, showing a state in which a bonding surface is inclined and a bonding wire is torn in a wire bonding step.

FIG. 5 is a view showing a problem of a conventional lead frame for a semiconductor device, and shows a state in which a bonding surface is inclined in a wire bonding step and the bonding property between a bonding wire and an inner lead is reduced.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Inner lead 2 Insulating film 3 Jig 4 Jig 5 Semiconductor chip 6 Bonding wire 10 Downset processing part 11 Bonding surface 21 Neck 22 Neck

Claims (3)

[Claims] 1. A lead frame for a semiconductor device, wherein a downset portion is formed at a tip portion of an inner lead and the tip portion is bonded to a semiconductor chip. A lead frame for a semiconductor device, wherein an easily deformable portion which is easier to deform than a portion is formed. 2. The lead frame for a semiconductor device according to claim 1, wherein said easily deformable portion is a constriction formed in a width direction of said inner lead. 3. The semiconductor device lead frame according to claim 1, wherein said easily deformable portion is a constriction formed in a thickness direction of said inner lead.