JPH10285462A - Video signal processing unit for prompter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute vertical scrolling and horizontal scrolling by using the configuration which employs a microcomputer speed of which is not high so as to reduce the cost. SOLUTION: An up-counter 21 as an address counter is used for an original memory 12 that stores original image data, and a CPU 20 is connected to the up-counter 21. Then a head address of a horizontal line is set to the up-counter 21 from input/output ports of the CPU 20 for a horizontal blanking period and the head address is incremented by the up-counter 21 with a clock signal for an image data valid period. Thus, the CPU 20 has only to set the head address of the horizontal line. Furthermore, consecutive address numbers are numbered in a horizontal direction, while pluralities of images are arranged laterally in the memory 12 and then vertical and horizontal scrolling are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus of a prompter for displaying a manuscript to be read by a newscaster or the like, and to a structure for controlling an address required for writing / reading image data of a manuscript memory. .

[0002]

2. Description of the Related Art A prompter stores original image data photographed by an original camera or the like in a memory, and allows an original read from this memory to be displayed on a display during broadcasting. Control of writing / reading of the memory is performed by designating an address of the memory via an address bus.

FIG. 7 shows a conventional configuration for address control, for example, an SRAM (Static Ran).
A high-speed CPU (microcomputer) 2 is connected to a document memory 1 composed of a dom access memory via an address bus. According to the high-speed CPU 2, an address signal for each pixel is output at a high speed via the address bus, and the image memory 1 is output.
Write image data to the specified address of
The image data at the specified address is read. In this manner, a predetermined number of document images can be stored in the document memory 1, output as needed, and displayed on the display.

[0004]

However, the above-mentioned high-speed CPU 2 is expensive, and the use of this high-speed CPU 2 to construct a video signal processing apparatus has a problem that the cost of the prompter apparatus is high. That is, if the address can be set using a CPU (microcomputer) that does not operate at high speed, the device can be manufactured at low cost.

Accordingly, the present applicant has proposed a CP which does not operate at high speed.
A device that controls addresses by combining a U and a logic circuit has been proposed (details will be described later). In this proposed device, not only vertical scrolling of a horizontally written document but also horizontal scrolling of a vertically written document is performed. It is required to be able to do so.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide a video signal processing system for a prompter capable of performing up / down scrolling and left / right scrolling even in a configuration in which a low-speed microcomputer is used to reduce the cost. It is to provide a device.

[0007]

In order to achieve the above object, the present invention writes image data in a document memory,
A video signal processing device of a prompter for reading image data from the original memory; a microcomputer for outputting a head address of horizontal line data from an input / output port during a horizontal blanking period of the video signal; An address counter which is connected via an address bus, sets the head address output from the microcomputer, and increases or decreases (increments or decrements) the address of a horizontal line by a clock signal during the image data valid period of the video signal. The document memory is characterized in that a plurality of images are arranged in the horizontal direction and consecutively assigned address values (numbers) in the horizontal direction.

According to the above arrangement, an up counter (or down counter) is provided as the logic circuit, and the microcomputer sets the top address of the horizontal line in the horizontal blanking period for the up counter. Thereafter, in the up counter, the value is incremented from the head address by the input clock signal, and the address data is output to the image memory via the address bus. Therefore, writing and reading to and from the memory are performed by the address set and specified by the clock signal in the up counter, and the microcomputer does not need to directly specify the address at a high speed.

In the above address control, the addresses of the horizontal lines are sequentially designated by the clock signal. Therefore, images of the number of pages (sheets) that can be stored in the document memory are arranged in the vertical direction, and the images are sequentially arranged in the horizontal direction. When an address value is added, there is no problem in vertical scrolling for a horizontally written document, but horizontal scrolling for a vertically written document cannot be performed. However, in the present invention, the address values are sequentially assigned in the horizontal direction in a state where the images are arranged horizontally. Therefore, even if the image is scrolled left and right, by setting the start address, the continuous address value to be incremented for one screen. Image data can be read.

[0010]

FIG. 1 shows a circuit configuration of a video signal processing apparatus of a prompter according to an embodiment, and FIG.
3 shows an operation of signal processing, and FIG. 3 shows a setting state of an address in a memory (for one image). First, in FIG. 1, a video input terminal 10 receives a composite video signal of a document photographed by a document camera, and an A / D converter 11 is connected to the video input terminal 10.
An original memory 12 composed of an SRAM or the like is connected via the CPU, and original image data is stored in the memory 12. A video amplifier 14 is connected to the document memory 12 via a D / A converter 13, and a video signal amplified by the video amplifier 14 is output from a video output terminal 15 to a display.

On the other hand, the video input terminal 10 is connected to a synchronization separation circuit 17 for separating a synchronization signal from a composite video signal, and a timing generator 18 for forming various timing signals is connected to the synchronization separation circuit 17. The timing signal from the timing generator 18 is supplied to each circuit as shown. In this example, a CPU 20 constituted by, for example, an 8-bit one-chip microcomputer is provided.
An up-counter (logic IC circuit) 21 as an address counter is connected to an input / output (I / O) port of the device. The up-counter 21 is connected to the document memory 12 via an address bus.

In the document memory 12, address details (numbers) are sequentially assigned in the horizontal direction in a state where images of a predetermined number of pages are arranged in the horizontal direction, as will be described later in detail with reference to FIGS. This allows not only vertical scrolling but also horizontal scrolling to be executed.

Here, as shown in FIG. 3, the operation of the above-described circuit in the case where addresses are assigned to only one page of images in the document memory 12 will be described. First, the composite video signal input to the video input terminal 10 is a signal including a synchronization signal as shown in FIG. 2A, and the synchronization separation circuit 17 separates the synchronization signal. In the timing generator 18, FIG.
A horizontal blanking signal as shown in FIG. As shown in this horizontal blanking signal, the composite video signal is composed of a blanking period H1 of about 10.9 μs and an image data valid period (period for substantially forming an image) H2 of about 51.1 μs. .

In the timing generator 18, a timing signal in which a clock signal exists during the image data valid period H2 of the horizontal blanking signal is formed.
As shown in FIG. 3, if one image in the memory 12 has an address width (value) of 365 in the horizontal direction as shown in FIG. 3, 51.1 μs / 365 =
The signal has a cycle of 0.14 μs (which is a cycle of the subcarrier frequency 2fsc).

Then, as shown in FIG. 3, on the display screen of the prompter, for example, the 21st horizontal line to the 262nd horizontal line are set as data of one screen, and in this case, the address is assigned to 21 lines. (Value) 1
Addresses 366 to 730 are allocated to 365 and 22 lines, and addresses are sequentially set up to 262 lines.

From the CPU 20, the head address of the horizontal line is set in the up counter 21 via the I / O port. For example, an address (value) = 1 is set for the 21 lines. Then, in the up-counter 21, the address value is incremented to 2, 3, 4... 365 by the clock signal of FIG. 2C, so that the addresses of the document memory 12 are sequentially specified via the address bus. Is done. Similarly, for the above 22 lines, 366, 367, 368
… The address of 730 is specified, and thus
Addresses are sequentially specified up to 262 lines.

In addition, at the same time as the above-mentioned address designation, the A / D converter 11
The image data of the effective period H2 of (A) is sequentially input, and each pixel data is sequentially written to the designated address. On the other hand, even when displaying the original, if the CPU 20 sets the top address in the up counter 21, the addresses of the horizontal lines are sequentially specified based on the clock signal, and the pixel data of the specified address is sequentially read. Thus, the document image is displayed on the display.

As described above, according to the example, the CP
The U20 only needs to set the head address of the horizontal line, and address control can be performed by a low-speed CPU without using a conventional high-speed CPU.

FIG. 4 shows a state in which images of 22 pages are arranged in the vertical direction and address numbers are sequentially assigned.
Here, for the sake of simplicity, one image is 10
It is assumed that (horizontal) × 10 (vertical) = 100 pixels. As shown in FIG. 4A, in this case, the address of one line (horizontal line) of the image of the first page is from 1 to 1.
Address numbers are assigned such as 0 to 0, 2 lines from 11 to 20,..., The address of one line of the image of the second page is 101 to 110, 2 lines from 111 to 120, and so on.

FIG. 4B shows a state in which the horizontal writing document is scrolled up and down. For example, if the CPU 20 sets 51 as the head address of one line based on a scroll operation to the lower side, 51 to 60 are designated as addresses of one line. Also, by setting the head address every tenth, 61 to 70 are specified as the addresses of the two lines, and 141 to 150 are specified as the addresses of the last ten lines, thereby enabling vertical scrolling.

However, in the case of horizontal scrolling, as shown in FIG. 4A, for example, assuming that 5 is set as the head address in a vertically written original, 5-10 and 101-104 in this horizontal line. It is necessary to increment the number up to the number, but the up counter increments the address number in order, so that it is not possible to specify the jump from the number 10 to the number 101 and scrolling left and right is not possible.

Therefore, in the embodiment, as shown in FIG. 5, the images are arranged horizontally from the right side to the 22nd page, and the address numbers are sequentially assigned from the left side. Therefore, for example, as shown by the horizontal line of the image on the 22nd page, the start address is a 220-step number such as 1,221,441,. Can be).

FIG. 6A shows the control of the horizontal scrolling. When the image of the vertically written original is moved to the intermediate position of the second page by the scroll operation to the left, the CPU 20 controls the horizontal scrolling. For example, 206, 426, 646, and finally 21
86 is set. Then, the up counter 21 increments from each of the above-mentioned head addresses, and
~ 215, 426-435, 646-655, and finally 2
186 to 2195 are output, and this address is designated, whereby horizontal scrolling becomes possible.

FIG. 6B shows the control of the vertical scrolling. When the image of the horizontally written original is moved to the upper position of two pages by the downward scroll operation, the CPU 20 controls the horizontal line. For example, 781, 1001 and finally 641 are set as the head address of the. Then, the up counter 21 increments from each of the above-mentioned head addresses, and
By specifying addresses 001 to 1010 and finally 641 to 650, vertical scrolling becomes possible.

In the above example, the image numbers arranged in the horizontal direction are numbered sequentially from the left side. However, the numbers can be sequentially numbered from the right side. In this case, the addresses are decremented by using a down counter. Similarly, horizontal scrolling and vertical scrolling can be performed.

[0026]

As described above, according to the present invention,
A microcomputer that outputs the head address of the horizontal line from the input / output port during the horizontal blanking period, and sets the head address output from the microcomputer, and then increases or decreases the address of the horizontal line by a clock signal during the image data valid period Logic circuit
In the original memory, multiple images are arranged in the horizontal direction and consecutive address values are assigned in the horizontal direction, so that a low-speed microcomputer can be used to reduce cost, and scrolling up and down and left and right can be performed Thus, a horizontally-written document and a vertically-written document can be read by scrolling, and an easy-to-use prompter device can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a video signal processing device of a prompter according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing a processing operation in the circuit of FIG.

FIG. 3 is an explanatory diagram showing an address setting state of one image in the embodiment.

FIG. 4 is an explanatory diagram showing an example of an address setting state when a plurality of images are stored (FIG. (A)) and an address designation state (FIG. (B)) when scrolling up and down in this example.

FIG. 5 is an explanatory diagram showing an address setting state in the embodiment.

6A and 6B show an address designation state when a scroll operation is performed in the embodiment, and FIG. 6A is a diagram of left and right scroll, and FIG. 6B is a diagram of up and down scroll.

FIG. 7 is a block diagram showing a configuration of an address control circuit of a conventional prompter video signal processing device.

[Explanation of symbols]

 1, 12: Document memory, 2: High-speed CPU, 18: Timing generator, 20: CPU, 21: Up counter (address counter).

Claims (1)

[Claims] An image data is written in a document memory,
A video signal processing device of a prompter for reading image data from the original memory; a microcomputer for outputting a head address of horizontal line data from an input / output port during a horizontal blanking period of the video signal; And a logic circuit as an address counter for increasing or decreasing the address of a horizontal line by a clock signal during the image data valid period of the video signal after setting the head address output from the microcomputer. A video signal processing device for a prompter, wherein the original memory has a plurality of images arranged in a horizontal direction and an address value which is continuous in a horizontal direction.