JPH102942A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable screening inspection and the like with a power-supply voltage being changed minutely at the time of burn-in operation. SOLUTION: In the burn-in operation and the like, wherein a power-supply voltage is specified value or more, the output of a high-voltage detecting circuit 202 becomes the high level, and a node 4 also becomes the high level. Therefore, an NMOS transistor T2-1 is conducted, and a node 2 is connected to a power supply terminal Vcc. The reference voltage of the node 2 becomes the value, which is obtained by subtracting the threshold voltage of the transistor T201 from the power supply voltage. Then, after an operation switching signal (high level) is inputted into an input 1, the high-level state of the node 4 is maintained by an AND gate 203 even if the power supply voltages is decreased to the value less than the preset value. Therefore, the potential of an output node 1 is finely changed in correspondence with the change in power supply voltage, and screening inspection and the like can be performed excellently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to an improvement in performing a burn-in operation to which a high voltage is applied and a screening test.

[0002]

2. Description of the Related Art FIG. 14 shows a conventional semiconductor device, particularly showing a step-down circuit portion thereof. In FIG. 1, reference numeral 1 denotes a voltage supply circuit, which supplies a voltage to a node 1. Reference numeral 2 denotes a reference voltage generation circuit which outputs a reference voltage for determining the voltage level of the node 1 to the node 2. Reference numeral 3 denotes a comparator which compares the potential of the node 1 with the reference voltage of the node 2 and outputs a signal for driving the voltage supply circuit 1 to the node 3 when the potential of the node 1 is lower. Output. The transistor T101 constituting the voltage supply circuit 1 is controlled by the potential of the node 3, receives the drive signal from the comparator 3 output to the node 3, connects the node 1 to the power supply terminal, and connects the node 1 to the node 1. Supply voltage.

Reference numeral 201 denotes a constant voltage source constituting a part of the reference voltage generating circuit 2, and outputs a constant voltage to the node 2 without depending on a power supply voltage. 202 is a high voltage detection circuit that constitutes another part of the reference voltage generation circuit 2, detects that the power supply voltage is equal to or higher than a specific high voltage, and outputs a High level signal to the node 4. The transistor T201 is a reference voltage supply NMOS transistor for receiving a high voltage detection signal from the node 4 and increasing the reference voltage of the node 2 when the power supply voltage is equal to or higher than the specific high voltage.

FIG. 15 shows the relationship between the power supply voltage and the voltage of node 1 in the step-down circuit of the semiconductor circuit having the structure shown in FIG. First, when the power supply voltage is lower than the detection level of the high voltage detection circuit 202, the node 4 is at the Low level, and the transistor T201 is off. Therefore, the reference voltage of the node 2 is determined by the output of the constant voltage source 201. When the power supply voltage is lower than the predetermined constant voltage of the constant voltage source 201, the generated voltage of the constant voltage source 201 does not become the constant voltage, but becomes the same voltage as the power supply voltage, and the potential of the node 2 is the same as the power supply voltage. Therefore, the potential of the node 1 is
In the range indicated by the symbol A in the figure, the voltage supply circuit 1 and the comparator 3 keep the same potential as the potential of the node 2.

Next, when the power supply voltage is higher than a predetermined constant voltage of the constant voltage source 201, the constant voltage source 201 generates a constant voltage regardless of the power supply voltage. , And the potential of node 1 is
As shown in the range indicated by, the potential of the node 2 is maintained at the same potential.

Further, when the power supply voltage is higher than the detection level of the high voltage detection circuit 202, for example, during an operation such as burn-in, the high voltage detection circuit 202 outputs a high level signal, and the transistor T201 is turned on. Therefore, the reference voltage of the node 2 does not depend on the constant voltage of the constant voltage source 201, and is a voltage obtained by subtracting the threshold voltage Vtn of the transistor T201 from the power supply voltage. As in the range indicated by the symbol C, the potential is maintained at the power supply voltage-threshold voltage Vtn.

[0007]

However, in the conventional semiconductor device, when the high voltage detection circuit 202 detects a high voltage, the range shifts from the range of symbol B to the range of symbol C in FIG. 1 is a predetermined voltage (power supply voltage−threshold voltage Vtn) from the constant voltage of the constant voltage source 201.
It changes suddenly. For this reason, it is impossible to perform a screening test or the like that finely changes the voltage of the node 1 to an arbitrary voltage and removes a component that does not satisfy a specified quality level.

Further, as disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 6-113530, the substrate potential generating circuit is designed to keep a constant substrate voltage even when the power supply voltage fluctuates. In a burn-in operation, etc., in which a high voltage is applied in a screening test, current consumption in an internal circuit increases, and accordingly, a substrate current increases and a substrate voltage rises. Operation becomes unstable or difficult.

Further, in the conventional boosted potential generating circuit, as disclosed in, for example, Japanese Patent Application Laid-Open No. 5-235734, when the power supply voltage increases, the boosted voltage generated also increases proportionally, resulting in an excessive boost. Therefore, the load on the transistors constituting the circuit increases, and there is a problem in reliability.

In addition, in the above-described step-down circuit and step-up voltage generating circuit, the step-down voltage and step-up voltage generated by the variation in the characteristics of the transistors constituting these circuits change. There is also a disadvantage that the acceleration coefficient varies.

In a semiconductor device such as a DRAM (Dynamic RAM), the arrangement of terminals for connection to the outside is determined in advance, so that a new terminal is added to operate in a special mode used for screening inspection and the like. It is difficult to switch states.

An object of the present invention is to solve the above-mentioned conventional problems. It is an object of the present invention to provide a semiconductor device in which a high voltage equal to or higher than a power supply voltage in a normal operation is applied. The high voltage that can be changed can be finely changed, so that the screening test and the like can be performed accurately, the rise of the substrate voltage and the boosted voltage can be suppressed, the stable operation can be guaranteed, and further, in the case of a semiconductor device such as a DRAM, a terminal is not added. Is to make the operation state switchable.

[0013]

In order to achieve the above object, according to the present invention, once a transition is made to a burn-in operation or the like under a high power supply voltage, an output node is changed according to a change in the power supply voltage. A semiconductor device capable of performing a fine screening test by finely changing the potential to a desired value.

Further, according to the present invention, at the time of a high voltage power supply such as a burn-in operation, the substrate voltage of the substrate voltage generating circuit and the boosted voltage of the boosted voltage generating circuit are lowered to suppress the excessive rise of the substrate voltage and the boosted voltage. To ensure stable and high reliability.

At the time of a high power supply voltage such as a burn-in operation, the high-voltage power supply is used as a step-down voltage or a step-up voltage.

Further, according to the present invention, in a semiconductor device such as a dynamic RAM, a signal which does not occur in a normal operation is generated, and this signal is used as an operation switching signal. Can be switched.

That is, a semiconductor device according to a first aspect of the present invention includes a power supply terminal and an input terminal to which an operation switching signal is input, and the semiconductor device has at least two or more operation modes. A voltage detecting means for detecting when the voltage of the connected power supply is equal to or higher than a set value; receiving an output of the voltage detecting means; 1, when the voltage of the power supply connected to the power supply terminal is equal to or higher than a set value, an operation switching signal input to the input terminal is received, and the voltage of the power supply connected to the power supply terminal is changed to the set value. Operation switching means for switching the operation state after the operation state has decreased to less than the second operation mode.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor device includes a step-down circuit that steps down a voltage of a power supply connected to a power supply terminal to generate a step-down voltage, When the voltage of the power supply connected to the power supply terminal is lower than a set value, the operation switching means changes the step-down voltage change characteristic of the step-down circuit with respect to a change in the voltage of the power supply connected to the power supply terminal. When the voltage of a power supply connected to the power supply terminal is equal to or higher than a set value, an operation switching signal input to the input terminal is received, and the step-down circuit responds to a change in the voltage of the power supply connected to the power supply terminal. The change characteristic of the step-down voltage is switched to the second step-down voltage characteristic.

Further, according to a third aspect of the present invention, in the semiconductor device according to the second aspect, the first step-down voltage characteristic is:
In a range where the voltage of the power supply connected to the power supply terminal is less than the set value, the change in the step-down voltage is small with respect to the change in the voltage of the power supply. When the voltage of the power supply is less than the set value, the step-down voltage changes according to the change of the voltage of the power supply.

According to a fourth aspect of the present invention, in the semiconductor device according to the first, second, or third aspect, the operation switching means is such that the voltage of the power supply connected to the power supply terminal is higher than a set value. In this case, only when the operation switching signal is input to the input terminal, the operation state in which the voltage of the power supply connected to the power supply terminal is equal to or higher than the set value is switched to the second operation mode.

According to a fifth aspect of the present invention, there is provided a semiconductor device having a power supply terminal and a substrate voltage generation circuit for generating a substrate voltage to be supplied to a semiconductor substrate, wherein the semiconductor device is connected to the power supply terminal. Voltage detection means for detecting when the voltage of the power supply to be supplied is equal to or higher than a set value, and when the voltage of the power supply connected to the power supply terminal is lower than the set value, the substrate voltage generation circuit Is switched to a first substrate voltage value, and when the voltage of a power supply connected to the power supply terminal is equal to or higher than a set value, the substrate voltage value generated by the substrate voltage generation circuit is changed to a second substrate voltage value. Substrate voltage switching means for switching to a substrate voltage value.

According to a sixth aspect of the present invention, in the semiconductor device of the fifth aspect, the second substrate voltage value is a voltage value lower than the first substrate voltage value (a negative value having a large absolute value). It is characterized by the following.

According to a seventh aspect of the present invention, in the semiconductor device according to the fifth or sixth aspect, an input terminal to which a switching signal is input is provided, and the substrate voltage switching means is connected to a power supply terminal. When the voltage of the power supply is equal to or higher than a set value, the value of the substrate voltage generated by the substrate voltage generation circuit is switched to the second substrate voltage value only when a switching signal is input to the input terminal. It is characterized by.

Further, in the semiconductor device according to the present invention, a power supply terminal, an input terminal to which a switching signal is input, and a boosted voltage higher than a voltage of a power supply connected to the power supply terminal are generated. A boosting voltage generation circuit, wherein when a switching signal is not input to the input terminal, a boosting voltage characteristic of the boosting voltage generation circuit is switched to a first boosting voltage characteristic, and a switching signal is input to the input terminal. And a step-up voltage characteristic switching means for switching the step-up voltage characteristic of the step-up voltage generation circuit to the second step-up voltage characteristic.

According to a ninth aspect of the present invention, in the semiconductor device according to the eighth aspect of the present invention, the semiconductor device further comprises a voltage detecting means for detecting when a voltage of a power supply connected to the power supply terminal is equal to or higher than a set value. The voltage characteristic switching means changes the boosted voltage characteristic of the boosted voltage generation circuit to the second boosted voltage only when the voltage detecting means detects a power supply voltage equal to or higher than the set value when the switching signal is input to the input terminal. It is characterized by switching to voltage characteristics.

According to a tenth aspect of the present invention, in the semiconductor device according to the eighth or ninth aspect, the value of the boosted voltage in the second boosted voltage characteristic is equal to the value of the first boosted voltage characteristic. Is set lower than the value of the boost voltage.

According to an eleventh aspect of the present invention, in the semiconductor device according to the second aspect, another input terminal to which another operation switching signal is input, and the other operation switching signal is input to the other input terminal. In this case, the step-down circuit is provided with connection means for connecting the internal terminal for outputting the step-down voltage and the power supply terminal.

According to a twelfth aspect of the present invention, in the semiconductor device according to the eighth aspect, another input terminal to which another operation switching signal is input, and the other operation switching signal to the other input terminal. Is input, the boosted voltage generation circuit includes connection means for connecting an internal terminal for outputting a boosted voltage and a power supply terminal.

According to a thirteenth aspect of the present invention, in the semiconductor device according to the eleventh or twelfth aspect, only when the voltage of the power supply connected to the power supply terminal is equal to or higher than the set value, the other input terminal And a limiting circuit for allowing input of another operation switching signal.

[0030] In addition, the invention according to claim 14 is based on claim 1, claim 2, claim 4, claim 5, claim 7, claim 8, claim 9, claim 11, or claim 12. 14. A switching signal generating circuit according to claim 13, wherein an operation switching signal is generated by continuously entering a predetermined mode in a normal operation state in which a voltage connected to a power supply terminal is less than a set value a plurality of times. Is provided separately.

According to a fifteenth aspect of the present invention, in the semiconductor device according to the fourteenth aspect, the switching signal generating circuit is configured to enter the CBR self-refresh mode in the DRAM a plurality of times in succession, thereby providing an operation switching signal. Is generated.

With the above arrangement, according to the first to fourth aspects of the present invention, while the step-down voltage is finely changed,
Screening inspections and the like can be performed under a high-voltage power supply.

According to the fifth to seventh aspects of the present invention, during operation under a high power supply voltage such as burn-in operation, the substrate voltage of the substrate voltage generation circuit is generated lower than during normal operation. Even if the substrate voltage rises due to the increase in the substrate current accompanying the increase in the operating current, the substrate voltage does not reach the voltage value at which the latch-up phenomenon occurs, so that the normal operation of the circuit can be ensured.

Further, according to the present invention, the boosted voltage of the boosted voltage generating circuit is generated lower during the operation under the high power supply voltage such as the burn-in operation than in the normal operation. This prevents the boosted voltage from being excessively boosted, thereby suppressing an increase in the load on the transistor and improving the reliability of the circuit.

In addition, according to the present invention, even when the characteristics of the transistors forming the step-down circuit and the step-up voltage generation circuit vary, the characteristics of this transistor are high at the time of a high power supply voltage such as burn-in operation. Since the power supply voltage of the voltage is used as the step-down voltage and the step-up voltage, the step-down voltage and the step-up voltage can be stabilized irrespective of the variation in the characteristics of the transistor, and the change in the acceleration coefficient can be suppressed or prevented. Inspection and the like can be performed with high accuracy.

In addition, in the inventions according to the fourteenth and fifteenth aspects, a signal that does not occur in a normal use state is used as an operation switching signal. Therefore, in a normal use state of a user or the like, a high power supply voltage such as a burn-in operation is used. In this case, it is possible to reliably prevent the shift to the special mode, and it is not necessary to add a terminal pin.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a configuration of a semiconductor device according to a first embodiment of the present invention, in particular, a portion of a step-down circuit thereof. In the figure, 1 is a power supply terminal Vcc
A potential supply circuit for supplying the potential of the power supply connected to the node 1 to the node 1. T101 is a PMOS transistor that constitutes the potential supply circuit 1 and supplies a potential to the output node 1.
Reference numeral 2 denotes a reference voltage generation circuit that generates a reference voltage applied to the node 2. Reference numeral 3 denotes a comparator which compares the potential of the node 1 with the reference voltage of the node 2 and, when the potential of the node 1 (internal terminal) (supply voltage to the internal circuit) is lower, a low-level signal Is output to the node 3.

Inside the reference voltage generating circuit 2, a constant voltage source 201, a high voltage detecting circuit (voltage detecting means) 202,
AND gate 203, OR gate 204, and NMOS
A transistor T201 is provided. The constant voltage source 20
1 generates a predetermined constant voltage and outputs the constant voltage to the node 2. The high-voltage detection circuit 202 outputs a high-level signal when the power supply voltage is higher than the detection voltage (set value).
Is output to The input 1 (input terminal) is an input terminal of an operation switching signal (hereinafter, when referred to as an “input terminal”, it means not only an external pin but also an internal terminal), and the operation input to this terminal The switching signal and the output of the OR gate 204 (potential of the node 4) are input. In the transistor T201, when the node 4 is connected to the gate, and the potential of the node 4 is at a high level (that is, at the time of a high power supply voltage), the power supply terminal is connected to the node 2 and the reference voltage of the node 2 is raised.

In FIG. 1, T4 is a voltage supply P
A MOS transistor (connection means) having a gate connected to an input 2 (another input terminal) to which another operation switching signal is input, and when the potential of the input 2 is at a low level,
Power supply terminal Vcc is connected to node 1.

Next, the operation of this embodiment will be described. The operation switching signal of the input 2 is normally at the High level, and the voltage supply PMOS transistor T4 is off.

In this state, when a low-level operation switching signal is input to input 1, the output of AND gate 203 is always at the low level. Therefore, node 4 is determined by the output of high voltage detection circuit 202. . Therefore, the voltage characteristic of the node 1 with respect to the power supply voltage is the same as that of the conventional example shown in FIG. 15 described above. As the step-down voltage characteristic of the node 1 with respect to the power supply voltage, the first step-down voltage characteristic of FIG.
Operation mode) is obtained.

Next, when a high-level signal is input to the input 1, the output of the AND gate 203 is determined by the voltage level of the node 4. The initial state of the voltage of the node 4 is at the low level. When the power supply voltage is lower than the detection level of the high voltage detection circuit 202, the node 4 remains at the Low level, the operation switching signal of the input 1 is not accepted, and the step-down voltage characteristic of the node 1 with respect to the power supply voltage is as shown in FIG. Are identical. On the other hand, when the power supply voltage is
When the detection level becomes equal to or higher than the detection level of 02, the output thereof becomes a high level, the node 4 also becomes a high level, and the operation switching signal of the input 1 can be received. If the operation switching signal is received even once, the AND gate 20
3 is always at the high level, and the output of the high voltage detection circuit 202 is subsequently changed to Lo.
Even when the w level is reached, the High level is maintained.
Therefore, the node 2 is connected to the power supply terminal via the transistor T201, and the reference voltage of the node 2 is a value obtained by subtracting the threshold voltage Vtn of the transistor T201 from the power supply voltage. Becomes the step-down voltage characteristic (second operation mode) shown in FIG. Therefore, the AND gate 203 and OR of the reference voltage generation circuit
The gate 204 constitutes the operation switching means 205 of claim 1.

Therefore, if the power supply voltage is high voltage detection circuit 202
In a burn-in operation or the like in which a high voltage is equal to or higher than the detection level, even after the power supply voltage falls below the detection level, it is possible to switch to an operation state in which the potential of the node 1 is finely changed according to the change in the power supply voltage. It is possible to perform a screening test or the like satisfactorily.

Further, when the operation switching signal of the input 2 is at the low level, the transistor T4 is turned on. Therefore, the power supply terminal and the node 1 are connected, and the voltage of the node 1 does not depend on the reference potential of the node 2 and becomes the same potential as the power supply voltage. During the period of the low level, the characteristics shown in FIG. Therefore, in the burn-in operation or the like, even after the power supply voltage falls below the detection level, the potential of the node 1 can be finely changed according to the change in the power supply voltage, and the screening test and the like can be performed satisfactorily. It is possible. In this case, the potential of the node 1 is not lower than the power supply voltage by the threshold voltage Vtn of the transistor T201, and is equal to the power supply voltage.

(Modification of Reference Voltage Generating Circuit) FIG. 5 shows a modification of the reference voltage generating circuit 2. In the reference voltage generation circuit 2 'shown in FIG.
And an inverter 402 are added. The AND gate (restriction circuit) 401 receives the output of the high voltage detection circuit 202 and the operation switching signal of the input 1, and the voltage of the power supply connected to the power supply terminal Vcc is equal to or higher than the detection level of the high voltage detection circuit 202. The output of the operation switching signal of the input 1 is permitted only when the operation is performed, and the output is input to the OR gate 204. Also, the inverter 402 inverts the output of the OR gate 204 and inputs the inverted output to the input 2 of FIG. The other configuration is the same as the reference voltage generation circuit 2 of FIG.
The same reference numerals are given and the description is omitted.

Therefore, in this modification, as shown in FIG. 6, as long as the operation switching signal of input 1 is at the low level, the potential of node 4 is maintained at the low level. Therefore, even when the power supply voltage exceeds the detection level of the high voltage detection circuit 202, the transistor T201 does not conduct, the reference voltage of the node 2 is fixed to the constant voltage of the constant voltage source 201, and the voltage of the node 1 Held at voltage.

On the other hand, as shown in FIG. 7, when the power supply voltage is equal to or higher than the detection level of the high voltage detection circuit 202, the output of the AND gate 401 (that is, the node 402) is input 1 for the first time.
Can be received, and at this time, Hig
When the h level operation switching signal is input to the input 1, the nodes 402 and 4 also become High level. Thereafter, as in the first embodiment, the AND gate 20
3 is fixed to the High level, so that even if the power supply voltage once drops above the detection level of the high voltage detection circuit 202 and then falls below the detection level, the node 4 The high level is maintained as long as the operation switching signal of the input 1 does not become the low level. As a result, the state in which the node 2 is connected to the power supply terminal via the NMOS transistor T201 is maintained, so that the potential of the node 1 can be finely changed according to the change in the power supply voltage, and the screening test and the like can be performed satisfactorily. It can be carried out.

Here, when the power supply voltage is high voltage detection circuit 202
Even when the power supply voltage is equal to or higher than the detection level, unless the operation switching signal of the input 1 becomes High level,
Since the potential of the node 1 does not change in accordance with the power supply voltage, and thus a screening test or the like cannot be performed, if the operator controls a change in the potential of the operation switching signal to the input 1, a transition to a special mode such as a burn-in operation is made. A function to understand and check is provided. Further, the voltage detection level of the high voltage detection circuit 202 can be set low.

Since the output of the inverter 402 is input to the input 2 of FIG. 1, the input 1 is input when the power supply voltage is equal to or higher than the detection level of the high voltage detection circuit 202 as shown in FIG.
Is controlled to a high level, the shift to a special mode such as burn-in is understood, and only when the operation mode of FIG.
Of the PMOS transistor T4, the voltage of the node 1 can be changed according to the change of the power supply voltage.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 9 shows a configuration of a substrate voltage generation circuit of a semiconductor device. In FIG. 1, reference numeral 5 denotes a charge pump circuit for generating a semiconductor substrate voltage (substrate voltage);
Is a high voltage detection circuit that outputs a low level when the power supply voltage is higher than the detection level, and 7 is an inverter that generates a signal for driving the charge pump circuit 5. T5 and T7 are PMOS transistors for resistance, T8,
T9 is a resistance NMOS transistor.

T6 is Lo of the high voltage detection circuit 6.
Upon receiving the w-level output signal, it becomes conductive, and the power supply terminal Vcc
A switch (substrate voltage switching means) composed of a PMOS transistor that connects the transistor and the node 6 and functions as a resistor. The transistors T5, T8 and T9 are connected to a power supply terminal Vc
c and a substrate voltage terminal VBB (hereinafter referred to as a VBB terminal) in series, and two transistors T5 and T8
(Node 6) is connected to the input side of the inverter 7. The transistor 7 and the switch T6 are connected in series, and this series circuit is connected in parallel with the transistor T5. When the potential of the VBB terminal (substrate voltage) increases, the potential of the node 6 increases, and the charge pump circuit 5 operates to lower the substrate voltage (negative potential).
When the potential of the BB terminal decreases, the potential of the node 6 decreases, and the charge pump circuit 5 stops.

Next, the operation of this embodiment will be described. When the power supply voltage is lower than the detection level of the high voltage detection circuit 6, the output is at the High level, and the PMOS transistor T6 is off. Therefore, the voltage of the node 6 is determined by the resistance of the transistor T5 and the resistance of the transistor T8.
And the divided voltage value with the total resistance value of T9. on the other hand,
When the power supply voltage is higher than the detection level of the high voltage detection circuit 6, its output goes to the low level, and the PMOS transistor T6 becomes conductive. Therefore, the voltage at the node 6 is determined by the divided voltage of the combined resistance of the transistors T5 and T6 and the total resistance of the transistors T8 and T9.
That is, depending on whether the power supply voltage is higher or lower than the detection level of the high voltage detection circuit 6, the potential of the node 6 is changed, and as a result, the detection level of the substrate voltage for operating the charge pump circuit 5 is switched. When the power supply voltage is high, the detection level of the substrate voltage is changed to a low level, and the substrate voltage V
BB is a potential during normal operation (first substrate voltage value) (for example,
(1.5 V) (for example, -1.8 V). As a result, during operation such as burn-in at a high power supply voltage, even if the substrate current increases due to an increase in the current consumption and the substrate voltage rises, the maximum value of the substrate voltage is not so high. It is possible to prevent instability of the circuit operation due to the increase in the number.

In FIG. 9, the high voltage detection circuit 202 is replaced with the high voltage detection circuit 202 of the reference voltage generation circuit 2 'of FIG. 5 shown in the modification of the first embodiment in place of the high voltage detection circuit 6.
It is also possible to provide the gates 203 and 401 and the OR gate 204, and connect the output side (that is, the node 4) of the OR gate 204 to the node 7. In this case, in particular, the operation switching signal of input 1 at the time of the high power supply voltage and the input 1 is High.
Only at the time of the h level, the detection level of the substrate voltage VBB is switched, so that the substrate voltage VBB can be maintained at a lower value than in the normal operation.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 10 shows a boosted voltage generation circuit of a semiconductor device. In the figure, 8 is a charge pump circuit for generating a boosted voltage, 9 is an inverter for generating a drive signal for the charge pump circuit 8, 10 is an AND gate, input 5 is an input terminal to which an operation switching signal is input, Input 4 is another input terminal to which another operation switching signal is input, T10, T
12 is a PMOS transistor for resistance, T13 is N for resistance
It is a MOS transistor. The transistors T10 and T13 are connected in series, and this series circuit
pp and the ground terminal Vss. The potential at the connection point of the transistors T10 and T13 (that is, the node 8) is input to the inverter 9 as a reference voltage. The output of the inverter 9 and the operation switching signal of the input 4 are input to the AND gate 10, and the output of the AND gate 10 is input to the charge pump circuit 8 as a drive signal.

In the figure, T11 is a switch composed of a PMOS transistor (step-up voltage characteristic switching means).
By receiving the low-level operation switching signal of the input 5 and conducting it, the boosting terminal Vpp is connected to the node 8 and functions as a resistor.

Further, T14 is a switch (connection means) composed of a PMOS transistor, which receives another operation switching signal of the input 4 and becomes conductive when this operation switching signal is at a low level, so that the power supply terminal 20 (this An external power supply Vcc or a dedicated internal power supply is connected to the terminal).
Connect to pp.

When the potential of the boosting terminal Vpp decreases, the potential of the node 8 also decreases and the charge pump circuit 8 operates. On the other hand, when the potential of the boosting terminal Vpp increases, the potential of the node 8 also increases and the charge pump circuit 8 operates. The circuit 8 stops. The output voltages Vi of the step-down circuit shown in FIG. 1 are connected to the gates of the PMOS transistors T10 and T12.
nt is applied.

Next, the operation of this embodiment will be described. The operation switching signal of the input 4 is normally controlled to a high level. Therefore, the PMOS transistor T14 is off, and the power supply terminal Vcc and the boost terminal Vpp are disconnected. The high-level operation switching signal of the input 5 is input to the AND gate 10.

In the above state, the operation switching signal of the input 5 becomes H
When controlled to the high level, the PMOS transistor T11 is off. Therefore, the potential of the node 8 is determined by the divided voltage value of the resistance of the two transistors T10 and T13. On the other hand, the operation switching signal of input 5 is Lo.
When controlled to the w level, the PMOS transistor T11 is in a conductive state. Therefore, the potential of the node 8 is determined by the divided voltage of the combined resistance of the three transistors T10, T11, and T12 and the resistance of the transistor T13. Therefore, at the time of a high power supply voltage such as burn-in, if the operation switching signal of the input 5 is controlled to the Low level, the potential of the node 8 can be changed to be higher than that in the normal operation, and the detection of the boosted voltage for driving the charge pump circuit 8 is performed. The level can be changed to a low level, and the generated boosted voltage is lower than the boosted voltage of the first boosted voltage characteristic in the normal operation.
, The over-boosting can be prevented, and the reliability is improved.

When the operation switching signal of the input 4 is at the low level, the output of the AND gate 10 is always at the low level and is not affected by the reference voltage of the node 8, so that the charge pump circuit 8 does not operate. At the same time, PM
Since the OS transistor T14 is conductive, the boost terminal Vpp is connected to the power terminal Vcc, and the boost voltage becomes equal to the power voltage. Therefore, when the operation switching signal of the input 4 is controlled to a low level at the time of a high power supply voltage such as burn-in, the screening test can be performed by applying the high power supply voltage to the boosting terminal Vpp. In this case, since the power supply terminal Vcc is connected to the boosting terminal Vpp, the power can be supplied even in an operation state where power consumption is large.

Although not shown, the input 5 includes the first
The node 4 of the reference voltage generation circuit 2 'of the modification of the embodiment may be connected. In this case, in particular, only when the power supply voltage is high and the operation switching signal of the input 1 is at the High level, the detection level of the boosted voltage can be switched to maintain the boosted voltage at a lower value than in the normal operation. Excessive boosting of the boosted voltage at the time of the power supply voltage can be prevented, and the reliability of the boosted voltage generation circuit can be improved.

Further, although not shown, the input 4 is connected to the output of the inverter 402 of the reference voltage generating circuit 2 '(ie,
(Node 403) may be connected. In this case, in particular, the operation switching signal of input 1 at the time of the high power supply voltage and the input 1 is High.
Only at the time of the h level, the transistor T14 becomes conductive and the power supply terminal Vcc can be connected to the boosting terminal Vpp. Therefore, an arbitrary voltage (power supply voltage) can be externally applied to the boosting terminal Vp.
It is possible to shift to this operation after confirming that p is given.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 11 shows the input 1 of the circuit of FIG. 1 showing the first embodiment, the input 1 of FIG. 5 showing a modification thereof, and FIG. 10 showing the third embodiment. Input 5
1 shows a circuit for generating an operation switching signal applied to the circuit. The generating circuit shown in FIG. 1 utilizes a self-refresh signal of a DRAM.

In the figure, reference numeral 11 denotes a high voltage detection circuit which outputs a high level signal to the node 9 when the power supply voltage is higher than the detection level, and 12 denotes the / RAS signal and /
A signal generation circuit for generating a CBR (CAS Before RAS) self-refresh signal based on the CAS signal;
Only when it receives a level signal, it is activated, and the number of outputs of the CBR self-refresh signal from the signal generation circuit 12 is counted. 15 is A for counting number detection
The ND gate receives an output of the counter circuit 13 and a CBR self-refresh signal from the signal generation circuit 12. A latch circuit 14 latches the output of the AND gate 13 and includes two inverters 60.
The latch circuit 14 outputs an operation switching signal (high-level signal) from the node 11.

Next, the operation of this embodiment will be described. First, when the power supply voltage is lower than the detection voltage of the high voltage detection circuit 11, the output (node 12) of the counter circuit 13 becomes inactive since the counter circuit 13 is inactive as shown in FIG. Therefore, even if the CBR self-refresh signal is output a plurality of times from the signal generation circuit 12, the node 11 keeps the Low level and the node 11 does not output the operation switching signal.

On the other hand, when the power supply voltage is higher than the detection level of the high voltage detection circuit 11, the node 9 goes high as shown in FIG.
3 is in an activated state.
It becomes possible to count the BR self-refresh signal. In this state, if the CBR self-refresh signal is input to the counter circuit 13 a plurality of times (twice in the figure),
The output of the AND gate 15 (potential of the node 13) is High.
At this time, the node 11 outputs a high-level signal (operation switching signal). Once the potential of the node 13 becomes High level, the level of the node 11 is fixed by the latch circuit 14, so that the node 11 holds the output of the operation switching signal unless the power is turned off.

Here, the continuous output of the CBR self-refresh signal a plurality of times is not allowed due to the specification of the DRAM.
The operation switching signal is not output at the h level. Therefore, in the present embodiment, even when the power supply voltage is higher than the detection level of the high voltage detection circuit 11, the CBR self-refresh signal is output a plurality of times before the special mode such as the burn-in operation is performed. By performing the transition, a screening test or the like can be performed, and therefore, it is possible to reliably prevent the transition to the burn-in operation by mistake in the normal use state by the use of the user or the like. Moreover, there is no need to use a new terminal.

[0072]

As described above, according to the first to fourth aspects of the present invention, it is possible to perform a screening test or the like under a high voltage power supply while finely changing the step-down voltage.

According to the fifth to seventh aspects of the present invention, during operation under a high power supply voltage such as burn-in operation, even if the substrate voltage increases due to an increase in the substrate current, this substrate voltage is not increased. It is possible to prevent the voltage from rising to the value at which the latch-up phenomenon occurs, and to ensure the normal operation of the circuit.

Further, according to the invention as set forth in claims 8 to 10, during operation under a high power supply voltage such as burn-in operation, excessive boosting of the boosted voltage is prevented, thereby suppressing an increase in the load on the transistor. Thus, the reliability of the circuit can be improved.

In addition, according to the present invention, the power supply voltage is used as the step-down voltage and the step-up voltage at the time of a high power supply voltage such as a burn-in operation. By stabilizing the step-down voltage and the step-up voltage, a change in the acceleration coefficient can be suppressed or prevented, and a screening test or the like can be performed with high accuracy.

In addition, according to the present invention, a signal which does not occur in a normal use state is used as an operation switching signal. It is possible to reliably prevent a transition to the special mode using the power supply voltage, and it is not necessary to add a terminal pin.

[Brief description of the drawings]

FIG. 1 is a diagram showing a step-down circuit of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a voltage characteristic of an output node with respect to a power supply voltage in a first (normal) operation mode by the step-down circuit of the embodiment.

FIG. 3 is a diagram showing a voltage characteristic of an output node with respect to a power supply voltage in a second (special) operation mode by the step-down circuit of the embodiment.

FIG. 4 is a diagram showing a voltage characteristic of an output node with respect to a power supply voltage when a power supply terminal and an internal terminal (step-down terminal) are connected by the step-down circuit of the embodiment.

FIG. 5 is a diagram showing a modification of the reference voltage generation circuit of the embodiment.

FIG. 6 is a diagram showing an operation when an operation switching signal is at a low level in a modification of the reference voltage generation circuit of the embodiment.

FIG. 7 is a diagram showing a voltage characteristic of an output node with respect to a power supply voltage in a second operation mode in a modification of the reference voltage generation circuit of the embodiment.

FIG. 8 is a diagram showing a voltage characteristic of an output node with respect to a power supply voltage when a power supply terminal and an internal terminal (step-down terminal) are connected in a modification of the reference voltage generation circuit of the embodiment.

FIG. 9 is a diagram illustrating a substrate voltage generation circuit according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating a boosted voltage generation circuit according to a third embodiment of the present invention.

FIG. 11 is a diagram illustrating an operation switching signal generation circuit according to a fourth embodiment of the present invention.

FIG. 12 is a diagram showing a timing chart when the power supply voltage is lower than the detection level of the high-voltage detection circuit in the operation switching signal generation circuit of the embodiment.

FIG. 13 is a diagram showing a timing chart in the case where the power supply voltage is equal to or higher than the detection level of the high voltage detection circuit in the operation switching signal generation circuit of the embodiment.

FIG. 14 is a diagram showing a step-down circuit of a conventional semiconductor device.

FIG. 15 is a diagram showing a step-down voltage characteristic of a step-down circuit of a conventional semiconductor device with respect to an external power supply voltage.

[Explanation of symbols]

Reference Signs List 1 potential supply circuit 2, 2 'reference voltage generation circuit Vcc power supply terminal 3 comparator 5, 8 charge pump circuit 201 constant voltage source 11, 202 high voltage detection circuit 12 signal generation circuit 13 counter circuit 14 latch circuit 203 AND gate 204 OR Gate 205 Operation switching means T4, T14 PMOS transistor (connection means) T6 switch (substrate voltage switching means) T11 switch (boost voltage characteristic switching means) 401 Other AND gate (limit circuit) 402 Inverter T6, T12, T14 PMOS transistor

Claims (15)

[Claims] 1. A semiconductor device having a power supply terminal and an input terminal to which an operation switching signal is input, and having at least two or more operation modes, wherein a voltage of a power supply connected to the power supply terminal is higher than a set value. A voltage detecting means for detecting a time, receiving an output of the voltage detecting means, and when a voltage of a power supply connected to the power supply terminal is lower than a set value, switching an operation state to a first operation mode; When the voltage of the connected power supply is equal to or higher than the set value, the operation switching signal input to the input terminal is received, and the operation state after the voltage of the power supply connected to the power supply terminal falls below the set value is changed to the second state. And an operation switching means for switching to the operation mode. 2. The semiconductor device according to claim 1, further comprising: a step-down circuit for stepping down a voltage of a power supply connected to the power supply terminal to generate a step-down voltage. At this time, the change characteristic of the step-down voltage of the step-down circuit with respect to the change of the voltage of the power supply connected to the power supply terminal is switched to the first step-down voltage characteristic, and the voltage of the power supply connected to the power supply terminal is equal to or higher than a set value. When receiving the operation switching signal input to the input terminal, the step-down circuit changes the step-down voltage change characteristic of the step-down circuit with respect to a change in the voltage of the power supply connected to the power terminal to the second step-down voltage characteristic. 2. The semiconductor device according to claim 1, wherein 3. The first step-down voltage characteristic is a characteristic in which, when the voltage of a power supply connected to a power supply terminal is less than the set value, a change in the step-down voltage is small with respect to a change in the voltage of the power supply. The second step-down voltage characteristic is a characteristic in which the step-down voltage changes according to a change in the voltage of the power supply when the voltage of the power supply connected to the power supply terminal is less than the set value. 3. The semiconductor device according to 2. 4. The operation switching means, when a voltage of a power supply connected to a power supply terminal is higher than a set value,
Only when the operation switching signal is input to the input terminal
4. The semiconductor device according to claim 1, wherein an operation state when a voltage of a power supply connected to the power supply terminal is equal to or higher than a set value is switched to a second operation mode. 5. A semiconductor device comprising a power supply terminal and a substrate voltage generation circuit for generating a substrate voltage to be supplied to a semiconductor substrate, wherein a detection is made when a voltage of a power supply connected to the power supply terminal is equal to or higher than a set value. Receiving the output of the voltage detecting means, and when the voltage of a power supply connected to the power supply terminal is lower than a set value, the value of the substrate voltage generated by the substrate voltage generating circuit is changed to a first substrate voltage. Substrate voltage switching means for switching the substrate voltage value generated by the substrate voltage generation circuit to a second substrate voltage value when the voltage of the power supply connected to the power supply terminal is equal to or higher than a set value. A semiconductor device characterized by the above-mentioned. 6. The semiconductor device according to claim 5, wherein said second substrate voltage value is lower than said first substrate voltage value. 7. An input terminal to which a switching signal is input, wherein the substrate voltage switching means is provided when the voltage of a power supply connected to the power supply terminal is equal to or higher than a set value and the switching signal is input to the input terminal. 7. The semiconductor device according to claim 5, wherein a value of the substrate voltage generated by said substrate voltage generation circuit is switched to a second substrate voltage value. 8. A semiconductor device comprising: a power supply terminal; an input terminal to which a switching signal is input; and a boosted voltage generation circuit that generates a boosted voltage higher than a voltage of a power supply connected to the power supply terminal. When the switching signal is not input to the input terminal, the boosted voltage characteristic of the boosted voltage generation circuit is switched to the first boosted voltage characteristic, and when the switching signal is input to the input terminal, the boosted voltage generation circuit A semiconductor device comprising: boosted voltage characteristic switching means for switching a boosted voltage characteristic of a circuit to a second boosted voltage characteristic. 9. A voltage detecting means for detecting when a voltage of a power supply connected to the power supply terminal is equal to or higher than a set value, wherein the boosted voltage characteristic switching means, when a switching signal is input to an input terminal, 9. The semiconductor device according to claim 8, wherein the boosted voltage generation circuit switches the boosted voltage characteristic to the second boosted voltage characteristic only when the voltage detection means detects a power supply voltage equal to or higher than the set value. 10. The boosted voltage value in the second boosted voltage characteristic is set lower than the boosted voltage value in the first boosted voltage characteristic. Semiconductor device. 11. An input terminal to which another operation switching signal is input, an internal terminal for outputting a step-down voltage by the step-down circuit when the another operation switching signal is input to the other input terminal, and a power supply. 3. The semiconductor device according to claim 2, further comprising connection means for connecting the terminal. 12. An input terminal to which another operation switching signal is input, and an internal terminal to which the boosted voltage generation circuit outputs a boosted voltage when the another operation switching signal is input to the other input terminal. 9. The semiconductor device according to claim 8, further comprising connection means for connecting the power supply terminal to the power supply terminal. 13. A limiting circuit which permits input of another operation switching signal to another input terminal only when a voltage of a power supply connected to a power supply terminal is equal to or higher than a set value. The semiconductor device according to claim 11 or 12. 14. A switching signal generating circuit for generating an operation switching signal by continuously entering a predetermined mode in a normal operation state in which a voltage connected to a power supply terminal is lower than a set value a plurality of times, and The semiconductor device according to claim 1, 2, 4, 5, 5, 7, 8, 9, 9, 11, 12, or 13, characterized in that: 15. The semiconductor device according to claim 14, wherein the switching signal generating circuit generates an operation switching signal by continuously entering a CBR self-refresh mode in the DRAM a plurality of times.