JPH10294471A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

An object of the present invention is to provide a source and gate structure capable of realizing a high gate withstand voltage and a high production yield when applying silicon carbide to a high withstand voltage static induction transistor, and a method of manufacturing the same. It is to be. In a silicon carbide static induction transistor, a p-type gate region is formed on a surface of a semiconductor substrate so as to partially overlap an n-type source region. [Effect] The alignment accuracy between the source region and the gate region is not required, and the gate breakdown voltage can be increased by silicon carbide, so that the production yield is greatly improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a silicon carbide semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art One of semiconductor devices is an electrostatic induction transistor. This transistor has a source region on a front surface of a semiconductor substrate, a drain region on a back surface, and a high resistivity region serving as a current path between the source region and the drain region. In an electrostatic induction transistor, a current flowing through a high specific resistance region is turned on / off by controlling a voltage applied to a gate region on a semiconductor surface.

FIG. 2 shows a basic configuration of a conventional static induction transistor. The transistor has a high impurity concentration n-type source region 4 and a high impurity concentration n-type drain region 2 and a low impurity concentration between the two regions 2 and 4. A concentration n-type drift region 1 is provided. The high impurity concentration p is on the same side as the high impurity concentration n-type source region 4.
The gate region 3 is provided, and the current is turned on / off by the function of the gate region 3.

In the electrostatic induction transistor as described above, the low impurity concentration n-type drift region 1 between the high impurity concentration n-type source region 4 and the high impurity concentration n-type drain region 2
Is turned on / off by the expansion of the depletion layer due to the voltage applied to the high impurity concentration p-type gate region 3. As the withstand voltage of the static induction transistor is increased, the voltage applied to the high impurity concentration p-type gate region 3 increases in order to block the voltage between the source and the drain. Although it is necessary to increase the breakdown voltage of the n-type source region 4, the high impurity concentration p-type gate region 3 and the high impurity concentration n-type
Cannot ensure the withstand voltage between the gate and the source by the direct junction of Therefore, a low impurity concentration n-type drift region 1 is provided between the high impurity concentration p-type gate region 3 and the high impurity concentration n-type source region 4, and the high impurity concentration p-type gate region 3 and the high impurity concentration n-type source region 4 Ensure the pressure resistance of

[0005]

The conventional gate and source structures are required to have strict alignment accuracy on the gate side and finished dimensional accuracy. First, the source of the static induction transistor is
The specified voltage applied between the drains is blocked by the reverse bias voltage between the gate and the source. Here, the voltage amplification factor μ is defined as a gate voltage with respect to a source-drain voltage to be controlled. With a 5 kV-class electrostatic induction transistor and a voltage amplification factor μ of 100, the gate-source withstand voltage is 50 V. When this is made of silicon, the distance between the gate region 3 and the source region 4 needs to be 2.5 μm or more. In the conventional gate structure, extremely strict processing accuracy is required, and the yield does not increase even if technologies such as a stepper exposure method and self-alignment are used.

[0006] Recently, silicon carbide has attracted attention as a semiconductor material other than silicon. Silicon carbide is considered to be most suitable for a high breakdown voltage element and a high-temperature semiconductor element because the maximum electric field strength is at least one order of magnitude higher than silicon and the band gap is large. When an electrostatic induction transistor with a withstand voltage of 5 kV and a voltage amplification factor of μ100 is made of silicon carbide, the distance between the gate and the source is 0.25 μm. Therefore, fine processing that is at least 10 times that of the silicon process is required, and it is extremely difficult to achieve such processing accuracy with existing device process technology.

If the distance between the gate and the source is made wider than 0.25 μm and the semiconductor device is manufactured by a feasible processing technique, the following problems occur. The drift region concentration of the electrostatic induction transistor having a withstand voltage of 5 kV class is 10 ¹³ cm ³ for silicon, and 10 ¹⁵ cm ³ for silicon carbide. Therefore,
The extension of the depletion layer of silicon carbide is about 1/10 that of silicon. If the processing accuracy has a margin, the gate voltage required for blocking increases, and the blocking characteristics deteriorate.

As another means, it is conceivable to lower the drift region concentration so that the depletion layer easily spreads. However, when this measure is taken, the resistivity of the drift region increases, and the low on-resistance, which is an advantage of the electrostatic induction transistor using silicon carbide, is sacrificed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a structure and a manufacturing method capable of realizing a high gate breakdown voltage and a high manufacturing yield when applying silicon carbide to an electrostatic induction transistor. To provide.

[0010]

A semiconductor device according to the present invention has a silicon carbide semiconductor substrate whose main material is silicon carbide (SiC). This silicon carbide semiconductor substrate has a first
A conductivity type drift region, a first conductivity type source region and a second conductivity type gate region extending inward from the surface of the silicon carbide semiconductor substrate, adjacent to the drift region, and having a higher impurity concentration than the drift region. And. further,
A drain electrode is electrically connected to the drift region, and a source electrode and a gate electrode contact the source region and the gate region, respectively. Here, a main current flows between the drain electrode and the source electrode, and ON / OFF of the main current is controlled by a voltage applied to the gate electrode. Here, one of the main features of the present invention is that the source region and the gate region are provided so as to be in contact with each other.

In the semiconductor device according to the present invention,
Since the source region and the gate region are provided so as to be in contact with each other, not so high precision is required for mask alignment when patterning these regions. In addition, since silicon carbide is used as a main material, a high gate breakdown voltage can be obtained even if the source region and the gate region both having a high impurity concentration are brought into contact. Therefore, a high gate breakdown voltage can be obtained with a high production yield.

Further, in order to increase the voltage amplification factor μ, the position where the distance between the gate regions opposed to each other across the source region is the narrowest position is deeper than the source region in the silicon carbide semiconductor substrate. Is preferred.

Note that a semiconductor layer of the first conductivity type or the second conductivity type having a higher impurity concentration than the drift region may be interposed between the drain electrode and the drift layer. In the case of a semiconductor layer of the first conductivity type, the semiconductor device according to the present invention operates as an electrostatic induction transistor (SIT), while in the case of a semiconductor layer of the second conductivity type, an electrostatic induction thyristor (SI thyristor) ).

In order to form the gate region of the silicon carbide semiconductor device having the structure according to the present invention, ion implantation with high energy or under high temperature is suitable. As a mask suitable for high energy ion implantation,
In the method for manufacturing a silicon carbide semiconductor according to the present invention,
A multilayer film in which an organic film, an inorganic film, and a resistor are sequentially stacked is used. Further, as a mask suitable for ion implantation under a high temperature state, a multilayer film in which silicon nitride and refractory metal silicide are sequentially stacked is used. In the present invention, the first conductivity type and the second conductivity type are either p-type or n-type, and are opposite to each other.

[0015]

Embodiments of the present invention will be described. In the following structure, only one channel is shown. In order to obtain a large current, a multi-channel structure in which many of them are arranged in parallel may be used.

FIG. 1 shows a sectional structure of a static induction transistor having a surface gate structure according to an embodiment of the present invention.

In a semiconductor substrate made of silicon carbide, an n-type drain region 2 having a relatively high impurity concentration extends from one surface (lower side of the figure) of the semiconductor substrate to the inside of the semiconductor substrate. Then, an n-type drift region 1 having an impurity concentration lower than that of this region is adjacent. Further, an n-type source region 4 having a higher impurity concentration than the n-type drift region 1 extends from the other surface (upper side in the figure) of the semiconductor substrate into the semiconductor substrate and into the n-type drift region 1. At both ends of the n-type source region 4, a p-type gate region 3 extending from the other surface of the semiconductor substrate into the semiconductor substrate and into the n-type drift region 1 and having an impurity concentration higher than that of the n-type drift region 1 is provided.
The mold source region 4 is provided so as to partially contact with the mold source region 4 so that both regions overlap. The p-type gate region 3 is an n-type source region 4
It extends deeper into the semiconductor substrate. That is, the depth of the pn junction between p-type gate region 3 and n-type drift region 1 is deeper than the depth of the junction between n-type source region 4 and n-type drift region 1. On one surface of the semiconductor substrate,
When the drain electrode 22 contacts the n-type drain region 2, n
Drift region 1 is electrically connected. On the other surface of the semiconductor substrate, source electrode 21 contacts n-type source region 4, and gate electrode 20 contacts p-type gate region 3 at both ends of n-type source region 4. The drain electrode 22, the source electrode 21, and the gate electrode 20 are connected to the drain terminal 32, the source terminal 31, and the gate terminal 30, respectively. Through these terminals, the electrostatic induction transistor of this embodiment is connected to an external circuit.

In this embodiment, the p-type gate region 3 having a high impurity concentration is in contact with the n-type source region having a high impurity concentration. However, since the material of the semiconductor substrate is silicon carbide, the p-type gate region 3 is formed. The breakdown voltage of the pn junction between the region 3 and the n-type source region 4, that is, the gate breakdown voltage can be increased. in this way,
Even if the p-type gate region 3 and the n-type source region 4 make contact, the gate breakdown voltage can be increased, that is, the p-type gate region 3
A high gate breakdown voltage can be obtained without providing a semiconductor region having a lower impurity concentration than these regions between the p-type gate region 3 and the n-type source region 4 in the manufacturing process. High precision is not required for mask alignment for aligning the pattern of the region 4 with the pattern. Depending on the pattern shape, it is possible to eliminate the need for mask alignment. Therefore, the variation in the magnitude of the gate breakdown voltage can be reduced in the manufacturing process, and the manufacturing yield is improved. Further, since the area of the source region can be increased, the current can be increased.

FIG. 3 is a sectional view showing a method of manufacturing the static induction transistor of FIG. 3A shows a case where a low impurity concentration n-type drift region 1 is formed on an n-type drain region 2 made of a high impurity concentration n-type semiconductor substrate by epitaxial growth. Subsequently, as shown in FIG. 2B, a p-type impurity such as aluminum is ion-implanted into the surface of the low-impurity-concentration n-type drift region 1 by using a gate region forming mask 10 which is an ion-shielding mask, thereby forming a high impurity concentration. A p-type gate region 3 is formed. Further, as shown in FIG. 2C, a high impurity concentration n-type source region 4 is formed by ion implantation of an n-type impurity such as nitrogen using the mask 11. At this time, the high impurity concentration n-type source region 4 is in contact with the high impurity concentration p-type gate region 3 so as to overlap each other. Subsequently, a gate electrode 20, a source electrode 21, and a drain electrode 22 are formed as shown in FIG.

Since silicon has a small impurity diffusion coefficient of about 1 / 10,000 that of silicon, thermal diffusion is not practical. Therefore, the ion implantation method is a preferable means for forming the high impurity concentration p-type gate region 3 of the silicon carbide static induction transistor. Therefore, a high impurity concentration p-type gate region 3 of a high withstand voltage static induction transistor is formed by ion implantation.
The study of the present inventor on the formation of is described below.

Conventionally, in the field of silicon semiconductor, since the high impurity concentration p-type gate region 3 of the static induction transistor needs to be formed deep, thermal diffusion of impurities has been used. Usually, in a 5 kV-class electrostatic induction transistor, the depth of the high impurity concentration p-type gate region 3 needs to be 60 μm. In the ion implantation, even if implantation is performed at a high energy of 10 MeV, the implantation depth is 10 μm, and it is difficult to implant up to a depth of 60 μm.

Silicon carbide can make the depth of the high impurity concentration p-type gate region 3 approximately 5 μm. This depth can be formed by ion implantation of about 5 MeV. Therefore, in the case of silicon carbide, the high impurity concentration p-type gate region 3
Can be used for ion implantation.

The depletion layer generated between the high impurity concentration p-type gate region 3 and the high impurity concentration n-type source region 4 at the time of gate reverse bias mainly has a high impurity concentration so as to extend in the direction of the high impurity concentration p-type gate region 3. It is desirable that the impurity concentration of the high impurity concentration p-type gate region 3 be lower than that of the impurity concentration n-type source region 4. The reasons 1, 2, and 3 will be described below.

1. Silicon carbide has a deeper impurity level than silicon, and is particularly remarkable at an acceptor level.
When boron is used as the acceptor, the acceptor level of boron in silicon is 45 meV, whereas that of silicon carbide is as deep as about 300 meV. Therefore, of the acceptors at the lattice position, the ratio of those that are activated at room temperature is several percent. Therefore, in order to make the high impurity concentration p-type gate region 3 high in carrier concentration such that the depletion layer does not spread, a large amount of ions must be implanted, which causes defects.

2. In order to increase the voltage amplification factor μ, it is necessary to form a deeper pn junction in the high impurity concentration p-type gate region 3 than in the high impurity concentration n-type source region 4. Therefore, when forming the p-type gate region 3 having a high impurity concentration, ions must be implanted with high energy. However, implanting deep and large amounts of ions causes defects. 3. When the high impurity concentration n-type source region 4 has a high concentration,
When current flows in the on state, electrons are injected from the source. The injected electrons cause conductivity modulation and reduce the substrate resistance.

FIG. 4 is an example of a cross-sectional structure of an electrostatic induction transistor formed by ion implantation utilizing the low impurity diffusion coefficient of silicon carbide. As in FIG. 1, the high impurity concentration n-type source region 4 is formed so as to overlap the high impurity concentration p-type gate region 3, but a plurality of (two in this embodiment) located at both ends of the n-type source region 4 are formed. Is located at a position deeper than the n-type source region 4 having a high impurity concentration, and in the present embodiment, at a substantially central portion in the depth direction of the p-type gate region. is there.
The reason why the high impurity concentration p-type gate region 3 can be formed as shown in FIG. 4 will be described below.

FIG. 5 shows contour lines of the implanted ion concentration when the silicon carbide substrate immediately after the ion implantation is viewed from the lateral direction. The ion concentration decreases in the order of the contour lines 40, 41, and 42. The reason why the implanted ions reach the back side of the mask is that the implanted ions are scattered in the lateral direction due to nuclear collision between the implanted ions and the substrate atoms. Immediately after implantation of silicon, the ion concentration distribution has a shape in which the central portion swells in the lateral direction. However, since the implanted ions are redistributed by annealing for defect recovery and activation of impurity ions, this distribution shape cannot be maintained. Since silicon carbide has an extremely small impurity diffusion coefficient of 1/10000 that of silicon, redistribution due to annealing does not occur and the shape immediately after implantation is maintained.

With the above structure, when the semiconductor device is turned off, the pn junction formed by the high impurity concentration p-type gate region 3 and the low impurity concentration n-type drift region 1 is separated from the high impurity concentration n-type source region 4 by a distance. Since the depletion layer extending to the low impurity concentration n-type drift region 1 contacts, the voltage amplification factor μ increases. When the high impurity concentration p-type gate region 3 is formed by ion implantation, the position where the channel width is the narrowest and the position where the impurity concentration is the highest match as shown in FIG. For this reason, the depletion layer spreads most toward the low impurity concentration n-type drift region 1 at the position where the channel width is the narrowest. Therefore, the source-drain voltage can be blocked with a small gate voltage.

In order to increase the voltage amplification factor μ, the high impurity concentration p-type gate region 3 shown in FIG. 4 needs to have a depth of about several μm. Therefore, ions must be implanted with high energy. In order to shield high energy ions, a thick mask is required. In order to realize the distribution shape shown in FIG. 5, scattering of implanted ions on the mask side wall must be avoided. Therefore, it is advantageous that the mask is as thin as possible. As a material of the mask 10, an organic film, a resist, a metal, silicide, SiO ₂ or the like can be considered.

Further, by the multilayer resist method, it becomes possible to process the mask side surface perpendicular to the semiconductor substrate surface, and it is possible to prevent ion scattering on the mask side wall. FIG. 6 shows a method of processing a multilayer resist. As shown in (a),
A laminated structure of an organic film 12, an inorganic intermediate layer 13, and a resist 14 is formed on the surface of a semiconductor substrate. The inorganic intermediate layer 13 is used to prevent the organic film 12 and the resist 14 from being mixed. Subsequently, the resist 14 is processed by an exposure process as shown in FIG. Next, as shown in (c), the processing of the inorganic intermediate layer 13 is performed by etching using the resist 14 as a mask. Finally, as shown in FIG.
The pattern 2 is formed by dry etching by O ₂ -RIE using the resist 14 and the inorganic intermediate layer 13 as a mask. A specific example of the organic film 12 is a polyimide resin. After the step (c), ion implantation is performed using the multilayer mask.

Since silicide has a large shielding effect against implanted ions, the mask can be made thinner, and the scattering of implanted ions on the side walls of the mask can be suppressed. In addition, metal causes a phenomenon called channeling in which implanted ions pass through the mask. Therefore, when a metal is used, it is necessary to form an amorphous film between the metal and the surface of the semiconductor substrate to prevent channeling.

By implanting silicon carbide while heating at a high temperature, defects at the time of implantation can be reduced. If the mask material has heat resistance, it can be used for high-temperature ion implantation. FIG. 7 shows an embodiment using a mask material which has high heat resistance, has a large ion shielding effect even when thin, and is easy to remove after ion implantation. The mask has a laminated structure of refractory metal silicide 16 on silicon nitride 15. Refractory metal silicide satisfies heat resistance and shielding effect. By making the portion in contact with the semiconductor substrate nitrogen silicon, removal of the mask after ion implantation is facilitated. In addition,
Examples of the refractory metal silicide include tungsten silicide and molybdenum silicide.

FIG. 8 shows another embodiment in which the contact resistance between the gate electrode and the high impurity concentration p-type gate region 3 is reduced as compared with FIG. The surface of the p-type gate region 3 having a high impurity concentration in contact with the gate electrode is formed as a p-type region 5 having a higher impurity concentration. As shown in FIG. 5, the surface concentration is reduced by one-stage ion implantation. Therefore, p-type impurities are ion-implanted at a lower energy than in the first stage, using the same mask as used for forming the p-type gate region 3 having a high impurity concentration. At this time, the ion species to be implanted may be the same as in the first stage or may be different. Since this implantation is intended to reduce the contact resistance of the gate electrode, a shallow junction is sufficient.

FIG. 9 shows another embodiment of the electrostatic induction transistor in which the voltage amplification factor μ is further improved from that of FIG. FIG. 9 shows a high impurity concentration p at both ends of the n-type source region 4 as in FIG.
The position where the distance between the mold gate regions 3 is the narrowest is located deeper than the n-type source region 4 having a high impurity concentration, and it is characteristic that the position is located deeper than in FIG.

FIG. 10 shows a method of manufacturing the static induction transistor shown in FIG. An n-type drift region 1 having a low impurity concentration is formed on an n-type drain region 2 formed of an n-type semiconductor substrate having a high impurity concentration by epitaxial growth. Subsequently, as shown in FIG. 10A, a first-stage ion implantation region 6 is formed on the surface of the low impurity concentration n-type drift region 1 by ion implantation of a p-type impurity such as aluminum. If the side wall of the mask at the time of ion implantation is close to a right angle to the substrate surface, the shape of the first stage ion implantation region 6 reflects the effect of the lateral scattering of the implanted ions, as shown in FIG. The narrowest position is inside the substrate surface. Next, as shown in FIG. 10B, ions are implanted at a higher energy than the first stage to form a second-stage ion implantation region 7. Lateral scattering is determined by energy loss due to nuclear collisions between implanted ions and substrate atoms. As the injection energy increases, the energy loss due to nuclear collision increases monotonically, so that the lateral scattering distance increases. As described above, the same ions or different ions are implanted in multiple stages with different energies, thereby obtaining FIG.
A shape as shown in (c) can be formed.

The energy loss due to nuclear collision is greater for heavier elements. Therefore, the heavier the element, the lower the shape. Finally, as shown in FIG. 10E, an n-type source region 4 is formed by ion implantation of an n-type impurity such as nitrogen. Next, an electrode is formed.

FIG. 11 is a perspective view of the silicon carbide static induction transistor of FIG. As described above, the impurity level of silicon carbide, particularly the acceptor level, is deep. When boron is used as the acceptor, even if the impurity concentration is on the order of 10 ¹⁸ cm ³ , only a few% of them are activated, and the substantial carrier concentration is about 10 ¹⁶ cm ³ . In this case, the resistivity of the p-type gate region 3 is several hundred mΩ · cm, and the voltage drop along the gate region cannot be ignored. Therefore, the silicon carbide static induction transistor needs to form a gate electrode along the high impurity concentration p-type gate region 3. 11, 20 is a gate electrode, 21 is a source electrode,
30 is a gate terminal and 31 is a source terminal. With the surface gate structure as shown in FIG. 11, the gate electrode 20 can be spread along the high impurity concentration p-type gate region 3. Therefore, the surface gate structure is a gate structure suitable for a silicon carbide static induction transistor.

FIG. 12 shows an embodiment using polysilicon for the gate electrode. In the silicon carbide static induction transistor, a current flowing through the low impurity concentration n-type drift region 1 between the high impurity concentration n-type source region 4 and the high impurity concentration n-type drain region 2 is changed to a high impurity concentration p-type gate region 3. Of the depletion layer due to the voltage applied to
It is turned on and off. Therefore, since the current flowing through the gate electrode is only the capacity of the depletion layer formed at the time of ON / OFF, polysilicon functions as the gate electrode despite having a higher resistivity than a metal such as aluminum. By using polysilicon for the gate electrode, high-temperature characteristics are more stable than that of a metal electrode such as aluminum. Further, since insulation by an oxide film or the like is facilitated, multilayer wiring is possible, and a source electrode can be deposited on one surface. Therefore, alignment accuracy at the time of source electrode deposition becomes unnecessary, and the manufacturing yield can be improved. As the gate electrode, silicide or salicide other than polysilicon can be used.

It should be noted that the present invention is not limited to the above-described embodiment, and the conductivity types of p and n may be different. Also,
The invention is also applicable to static induction thyristors. In the case of an electrostatic induction thyristor, in FIG.
May be changed to p-type.

[0040]

As described above, according to the present invention,
The alignment accuracy between the source region and the gate region is not required, and the manufacture of the high withstand voltage static induction transistor is facilitated. Also,
A large source area can be obtained, and a large current can be obtained. Further, by providing a position having the narrowest channel width inside the substrate, a large gate-source voltage can be blocked with a small gate voltage, and the voltage amplification factor μ improves.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a silicon carbide static induction transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional silicon static induction transistor.

3A to 3D are cross-sectional views illustrating steps of manufacturing the silicon carbide static induction transistor of FIG. 1 in the order of (a) to (d).

FIG. 4 is a cross-sectional view of a silicon carbide static induction transistor having further improved blocking characteristics according to another embodiment of the present invention.

FIG. 5 is a contour line of ion concentration immediately after ion implantation into a semiconductor substrate using a mask.

FIG. 6 is a cross-sectional view showing a multilayer resist processing method in the order of (a) to (c).

FIG. 7 is a sectional view showing a mask for forming the structure of FIG. 4;

FIG. 8 is a cross-sectional view of a silicon carbide static induction transistor in which the contact resistance with the gate electrode is reduced from that in FIG.

FIG. 9 is a cross-sectional view of a silicon carbide static induction transistor having further improved blocking characteristics according to another embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing process of the silicon carbide static induction transistor of FIG. 8 in the order of (a) to (e).

FIG. 11 is a perspective view of a silicon carbide static induction transistor after forming electrodes according to the embodiment of the present invention.

FIG. 12 is a cross-sectional view of a silicon carbide static induction transistor after forming electrodes according to an embodiment of the present invention.

[Explanation of symbols]

1 ... n-type drift region, 2 ... n-type drain region, 3 ... p
Gate region, 4... N-type source region, 5... P-type region, 6
... First stage ion implantation region, 7 second stage ion implantation region, 10 gate region forming mask, 11 source region forming mask, 12 organic film, 13 inorganic intermediate layer, 14
... resist, 15 ... silicon nitride, 16 ... high melting point metal silicide, 20 ... gate electrode, 21 ... source electrode, 22 ...
Drain electrode, 23... Gate polysilicon electrode, 24
... Metal electrode for source, 25 ... Oxide film, 30 ... Gate terminal, 31 ... Source terminal, 32 ... Drain terminal, 40 ... Ion concentration contour (high), 41 ... Ion concentration contour (medium), 42 ... Ion concentration Contour line (low).

Claims (10)

[Claims] A first conductivity type drift region, a silicon carbide semiconductor substrate extending from a surface of the silicon carbide semiconductor substrate to an inside thereof, adjacent to the drift region, and having a lower impurity concentration than the drift region. A source region of a first conductivity type and a gate region of a second conductivity type, wherein a drain electrode is electrically connected to the drift region; a source electrode is in contact with the source region; A gate electrode is in contact with the gate electrode, and the source region and the gate region are in contact with each other. 2. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration of said gate region is lower than an impurity concentration of said source region. 3. The silicon carbide semiconductor device according to claim 1, further comprising a plurality of said gate regions, said plurality of gate regions facing each other across said source region, and said plurality of gate regions facing each other. A silicon carbide semiconductor device, wherein the position where the distance is the smallest is deeper than the source region in the silicon carbide semiconductor substrate. 4. The silicon carbide semiconductor device according to claim 3, wherein an impurity concentration in a portion of said gate region on said surface of said silicon carbide semiconductor substrate is a portion in said interior of said silicon carbide semiconductor substrate. A silicon carbide semiconductor device characterized by having a higher impurity concentration than the above. 5. The silicon carbide semiconductor device according to claim 1, wherein a material of said gate electrode is at least one material selected from polysilicon, silicide, and salicide. Elementary semiconductor devices. 6. The silicon carbide semiconductor device according to claim 1, wherein said drain electrode is electrically connected to said drift region via a first conductivity type semiconductor layer having a higher impurity concentration than said drift region. A silicon carbide semiconductor device, comprising: 7. The silicon carbide semiconductor device according to claim 1, wherein said drain electrode is electrically connected to said drift region via a second conductivity type semiconductor layer having a higher impurity concentration than said drift region. A silicon carbide semiconductor device. 8. A silicon carbide semiconductor substrate of the first conductivity type,
A first step of forming a multilayer film in which an organic film, an inorganic film, and a resist are sequentially laminated from the substrate surface side; and a step of partially opening the multilayer film and exposing the surface of the silicon carbide semiconductor substrate. 2. A method for manufacturing a silicon carbide semiconductor device, comprising: a second step; and, after the second step, a third step of implanting impurity ions of a second conductivity type using the multilayer film as a mask. 9. A semiconductor substrate of a first conductivity type silicon carbide,
A first step of forming a multilayer film in which silicon nitride and a refractory metal silicide are sequentially laminated from the substrate surface side; and partially opening the multilayer film to expose the surface of the silicon carbide semiconductor substrate. A method of manufacturing a silicon carbide semiconductor device, comprising: a second step; and, after the second step, a third step of implanting impurity ions of a second conductivity type using the multilayer film as a mask. . 10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein said refractory metal silicide is tungsten silicide or molybdenum silicide.