JPH10294666A - Signal processing circuit - Google Patents

Abstract

(57) [Problem] To realize a signal processing circuit capable of achieving high performance, small size, and low cost of a pre / post filter by using a digital low-pass filter. SOLUTION: An analog low-pass filter 10
A band component of the input analog signal S _IN equal to or higher than the Nyquist frequency is attenuated, input to the n-times ADC 20, converted into a digital signal by the digital / analog conversion circuit 202 according to the multiplied clock signal CLKna, and has a steep cutoff characteristic. The high-pass noise is attenuated by the low-pass filter and input to the digital signal processing circuit 30. The processing result of the digital signal processing circuit 30 is input to the n × speed DAC 40, and the digital low-pass filter 40
2, the harmonic component is attenuated, converted into an analog signal by the digital / analog conversion circuit 403, the harmonic component is attenuated by the analog low-pass filter 50, and output as the processing result S _OUT .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a signal processing circuit, for example, an analog / digital conversion circuit and a digital / analog conversion circuit, to convert an analog signal into a digital signal, process the converted signal, and convert the processing result into an analog signal. The present invention relates to a signal processing circuit for converting and outputting.

[0002]

2. Description of the Related Art In recent years, with the advance of LSI technology, various digital signal processing circuits have been realized by super LSI circuits, and small and inexpensive signal processing circuits have become widespread. For example, a video signal (video signal) processing apparatus is also digitized in many conventional analog circuits. Such a digitized signal processing circuit can not only achieve a reduction in size and cost, but also can easily achieve higher performance of the circuit than a conventional analog signal processing circuit.

In a conventional analog signal processing circuit,
An example where high performance is required is a broadcast video signal processing circuit. In the video signal processing circuit, analog /
An analog pre-filter or post-filter used in a digital conversion circuit (hereinafter, referred to as an ADC) and a digital / analog conversion circuit (hereinafter, referred to as a DAC) has a high-performance flat pass characteristic and a steep cutoff characteristic, and furthermore, Flat group delay characteristics are required.

FIG. 11 shows a configuration example of a conventional signal processing circuit using an ADC and a DAC. As shown,
The signal processing circuit according to the present embodiment includes an analog low-pass filter LPFa1 as a pre-filter, an analog / digital conversion circuit ADC1, a digital signal processing circuit PDC, a digital / analog conversion circuit DAC1, and an analog low-pass filter LPFa2 as a post filter.

As shown, the conversion frequency fa of the ADC 1 is
Is, for example, 18 MHz and the conversion frequency fd of the DAC 1
Is, for example, 13.5 MHz, unlike fa.
The input signal S _IN is passed through the pre-filter LPFa1, and after the harmonic components higher than the Nyquist frequency are attenuated, the ADC
1 and converted into a digital signal D _IN and input to a digital signal processing circuit DPC. Signal processing circuit D
The PC performs desired processing on the input signal D _IN , and outputs the processing result as a digital signal D _OUT . The output signal D _OUT is again converted into an analog signal S _O by the DAC 1 and is input to an analog low-pass filter LPFa2 as a post filter. The analog low-pass filter LPFa2 attenuates the harmonic noise component generated by the conversion of DAC1, and the output signal S
Output as _OUT .

Low-pass filter L as pre-filter
The PFa1 attenuates frequency components equal to or higher than the Nyquist frequency fa / 2 to remove aliasing components, thereby sampling a digital signal D1 obtained by the ADC1.
_IN prevents generation of noise due to aliasing components.
FIG. 12A shows a gain characteristic of a low-pass filter LPFa1 as a pre-filter. As shown, the cutoff frequency of the pre-filter is fa / 2, and the gain of the pre-filter is kept flat in the frequency band of 0 to fa / 2 and attenuates rapidly in the frequency band of fa / 2 or more. And has a steep cutoff characteristic. The low-pass filter LPFa2 as a post filter is a DA filter.
Harmonic noise component generated by the digital / analog converter included in the output signal S _O of C1 is attenuated to achieve accurate signal generation. FIG. 12B shows a gain characteristic of a low-pass filter LPFa2 as a post filter. As shown, the cutoff frequency of the post filter is fb / 2, and the gain of the post filter is 0 to
fb / 2 is kept flat in the frequency band of fb / 2
It abruptly attenuates in the above frequency band and has a steep cutoff characteristic.

In this embodiment, the digital signal processing circuit DPC is a multi-rate processing circuit having different input / output clocks.

[0008]

By the way, the above-mentioned conventional analog / digital conversion circuit and digital / digital
In a signal processing circuit using an analog conversion circuit, ADC 1
The pre-filter and the post-filter used for removing the harmonic components before and after the DAC 1 are analog filters. For example, in broadcast video signal processing, high-performance filter characteristics, that is, flat passband characteristics, steep cutoff characteristics, and flat group delay characteristics are required, and these characteristics are to be realized by analog filters. In this case, since a high-order filter is required, there is a disadvantage that the apparatus becomes large and the filter becomes expensive.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a signal processing circuit capable of realizing high performance, small size, and low cost.

[0010]

In order to achieve the above object, a signal processing circuit according to the present invention is a signal processing circuit for converting an input analog signal into a digital signal and processing the converted signal. , A multiplying circuit for supplying a multiplied clock signal, an analog / digital converting circuit for converting the input analog signal into a digital signal in accordance with the multiplied clock signal, and a digital signal output from the analog / digital converting circuit And a digital filter that attenuates the higher harmonic components, converts the frequency in accordance with the external clock signal, and outputs the result.

A signal processing circuit according to the present invention is a signal processing circuit for converting an input analog signal into a digital signal, processing the converted signal, converting the processed result into an analog signal, and outputting the analog signal. A multiplying circuit for multiplying by a multiplication ratio and supplying a multiplied clock signal; and performing a frequency conversion process on the result of the digital signal processing, and a harmonic component in the signal after the frequency conversion process according to the multiplied clock signal. And a digital / analog conversion circuit for converting an output signal of the digital filter into an analog signal.

A signal processing circuit according to the present invention is a signal processing circuit for converting an input analog signal into a digital signal, processing the converted signal, converting the processing result into an analog signal, and outputting the analog signal. A multiplying circuit for multiplying by a multiplication ratio and supplying a multiplied clock signal, an analog / digital converting circuit for converting the input analog signal into a digital signal based on the multiplied clock signal, and an output from the analog / digital converting circuit A first digital filter that attenuates a harmonic component of the digital signal, performs a frequency conversion process in accordance with the external clock signal and outputs the digital signal, and an external clock signal for the output signal of the first digital filter. A signal processing circuit for performing predetermined processing according to the external clock signal and the multiplied clock signal A second digital filter that performs a frequency conversion process on the processing result of the signal processing circuit, attenuates and outputs a harmonic component in the signal after the frequency conversion process according to the multiplied clock signal, And a digital / analog conversion circuit for converting an output signal of the second digital filter into an analog signal.

Further, in the present invention, preferably, there is provided a first analog filter for attenuating a harmonic component of the analog signal and inputting the signal to the analog / digital conversion circuit.
The first analog filter has a more moderate cutoff characteristic than the first digital filter, and further, a second analog filter that attenuates a harmonic component of an analog signal output from the digital / analog conversion circuit. The second analog filter has a more moderate cutoff characteristic than the second digital filter.

Further, the signal processing circuit of the present invention is a signal processing circuit for converting an input analog signal into a digital signal, processing the converted signal, converting the processed result into an analog signal, and outputting the analog signal. Is multiplied at a first multiplication ratio, a first multiplication circuit for supplying a first multiplication clock signal, and a second input clock signal are multiplied at a second multiplication ratio.
A second multiplying circuit for supplying a second multiplied clock signal;
An analog / digital conversion circuit for converting the input analog signal into a digital signal based on the first multiplied clock signal; and attenuating a harmonic component of the digital signal output from the analog / digital conversion circuit. A first digital filter that converts the frequency in accordance with the input clock signal of the first digital filter and outputs the converted signal, performs a predetermined process on the output signal of the first digital filter, and further converts the first and second clock signals. A digital processing circuit for performing frequency conversion based on the frequency;
A second digital filter for performing frequency conversion on the processing result of the digital processing circuit in accordance with the multiplied clock signal of the second digital filter to attenuate harmonic components, and converting an output signal of the second digital filter into an analog signal And a digital / analog conversion circuit.

According to the present invention, the input analog signal is a multiplied clock obtained by multiplying the input clock signal by a predetermined multiplication ratio after the harmonic component is attenuated by, for example, an analog filter having a gentle cutoff characteristic. According to the signal, the signal is converted into a digital signal by an analog / digital conversion circuit, the frequency is further converted, and the converted signal is output to a digital processing circuit. A predetermined processing is performed by a digital processing circuit, the processing result is frequency-converted, and is converted into an analog signal by a digital / analog conversion circuit according to the multiplied clock signal. As a result of the conversion, harmonic components are attenuated by an analog filter having a gentle cutoff characteristic, and output. As a result, it is sufficient for the analog filter provided in the input and output sections to have a gradual cutoff characteristic, and a small and inexpensive analog filter can be used.
It is possible to realize a high-performance filter having steep cutoff characteristics, flat pass characteristics and flat group delay characteristics equivalently without increasing the scale of the circuit.

In the case where the input side and the output side operate according to clock signals having different frequencies,
First and second multiplying circuits having respective multiplying ratios generate first and second multiplied clock signals, and an analog / digital conversion circuit and a digital filter in an input section respond to the first multiplied clock signal. The digital filter and the digital / analog conversion circuit of the output section operate according to the second multiplied clock signal.
Further, in this case, in the signal processing circuit, multi-rate processing is performed according to the frequency of the clock signal on the input side and output side, and frequency conversion processing is performed on the digital signal. The multi-rate processing can be performed at the stage of digital filter processing on the input side or digital filter processing on the output side.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a signal processing circuit according to the present invention. The signal processing circuit of the present embodiment includes an analog low-pass filter 10 (LPF1), an n-speed analog / digital conversion circuit (hereinafter, referred to as an n-speed ADC) 2
0, digital signal processing circuit 30, n-times digital /
An analog conversion circuit (hereinafter, referred to as n-times DAC) 40 and an analog low-pass filter 50 (LPF4) are provided.

The analog low-pass filter 10 is composed of a simple analog filter and has a gentle cutoff characteristic. FIG. 2A shows the low-pass filter L
9 shows gain characteristics of PF1. As shown, LP
The gain of F1 is kept flat in the band of 0 to fa / 2, and gradually decreases in the frequency band of fa / 2 or more. Here, the frequency fa is the frequency of the clock signal CLKa input to the n-times ADC. A low-pass filter having such a gain characteristic can be easily configured by a general analog circuit, and a small-sized and low-cost filter circuit can be realized.

The n-times ADC 20 includes a clock n-times PLL circuit 201 as a multiplication circuit, an analog / digital converter 202, and a digital low-pass filter 203.
(LPF2), and the n-times speed DAC 40 includes a digital low-pass filter 402 (LPF3) and a digital / analog conversion circuit 403.

In the n-times ADC 20, a clock n-times PLL circuit 201 is provided as a multiplication circuit, and the frequency of the input clock signal CLKa is multiplied by a multiplication ratio n to generate a multiplied clock signal CLKna having a frequency nfa.
It is supplied to the double-speed ADC 20 and the n-times DAC 40, respectively.

The analog / digital conversion circuit 202 operates according to the multiplied clock signal CLKna, converts an analog signal from the analog low-pass filter 10 into a digital signal, and outputs the digital signal to the digital low-pass filter 203. The digital low-pass filter 203 operates according to the multiplied clock signal CLKna and the clock signal CLKa, reduces harmonic noise of the input signal, converts the frequency by multi-rate processing, and outputs the converted signal to the digital signal processing circuit 30.

The digital low-pass filter 203 (LP
The gain characteristic of F2) is shown in FIG. As shown in the drawing, the LPF 2 has a flat pass characteristic in a band of 0 to fa / 2, and the gain sharply decreases in a band of fa / 2 or more. That is, the LPF 2 has a flat pass characteristic in the pass band and a steep cutoff characteristic.

The digital signal processing circuit 30 operates according to the clock signal CLKa, performs signal processing on the input digital signal, and outputs the processing result to the n-times DAC 40.
Output to

In the n × speed DAC 40, a digital low-pass filter 402 and a digital / analog conversion circuit 403 are provided. The digital low-pass filter 402 operates according to the clock signal CLKa and the multiplied clock signal CLKna.
The frequency component is attenuated by the harmonic component of the processing result of 0, and further subjected to frequency conversion by multi-rate processing, and output to the digital / analog conversion circuit 403. FIG. 2C shows a gain characteristic of the digital low-pass filter 403 (LPF3). As shown in the drawing, the LPF 3 has almost the same gain characteristics as the LPF 2, has a flat pass characteristic in a band of 0 to fa / 2, and has a sudden decrease in gain in a band of fa / 2 or more. That is, the LPF 3 has a flat pass characteristic in a pass band and a steep cutoff characteristic.
The digital / analog conversion circuit 403 operates according to the multiplied clock signal CLKna, converts the output signal of the LPF 3 into an analog signal, and outputs the analog signal.

The digital low-pass filters LPF2 and LPF3 shown in FIGS. 2 (b) and 2 (c) are, for example, linear phase type and employ a multi-tap high-order filter to provide a steep cutoff characteristic and an ideal filter. Group delay characteristics can be realized.

The analog low-pass filter 50 attenuates the harmonic components of the output signal of the digital / analog conversion circuit 403 and outputs the result of the filtering process. FIG.
(D) shows a gain characteristic of the analog low-pass filter 50 (LPF4). As shown, LPF4 is 0
Has a flat gain characteristic within the band of
In two or more frequency bands, the gain gradually decreases. Therefore, the analog low-pass filter 50 can be easily configured by a general analog circuit, and a small-sized and low-cost filter circuit can be realized.

Hereinafter, the operation of the signal processing circuit of the present embodiment will be described with reference to FIG. In the signal processing circuit of the present embodiment, the analog signal S _IN is input to the analog low-pass filter 10, and the Nyquist frequency fa /
Harmonic components in two or more bands are attenuated and input to the n-times speed DAC 20. In the n-times DAC 20, the frequency of the input clock signal CLKa is multiplied by n by the clock n-times PLL circuit having the multiplication ratio n, and the frequency nf
A multiplied clock signal CLKna of a is generated. The analog / digital conversion circuit 202 converts the output signal of the analog low-pass filter 10 into a digital signal in accordance with the multiplied clock signal CLKna, and the digital low-pass filter 203 having a steep cutoff characteristic has a frequency of fa / 2 or more. The harmonic components are attenuated and output to the digital signal processing circuit 30.

In the digital signal processing circuit 30, predetermined processing is performed on the input digital signal, and the processing result is output to the n × speed DAC 40. In the n × speed DAC 40, the harmonic noise component is attenuated by the digital low-pass filter 402 having a steep cutoff characteristic, and the result of the filtering is output to the digital / analog conversion circuit 403. The digital signal input by the digital / analog conversion circuit 403 is converted into an analog signal, and the harmonic noise component is attenuated by the analog low-pass filter 50, and is output as the processing result S _OUT .

In this embodiment, the operation clock signals on the input side and the output side are the same. That is, the frequency of the input clock signal CLKa is multiplied by n by the clock n-times PLL circuit, and the multiplied clock signal CLKna is converted into the n-times ADC 20 on the input side and the n-times DAC 40 on the output side.
Is supplied as an operation clock signal. n-speed ADC20
, The digital low-pass filter 203 processes the digital signal from the analog / digital conversion circuit 202 in accordance with the multiplied clock signal CLKna, thins out the sampling points to 1 / n, and returns the original clock signal C
Output according to LKa. In the n-speed DAC 40, the digital low-pass filter 402 performs an interpolation process on the processing result from the digital signal processing circuit 30, for example, performs frequency conversion by inserting zero, and then performs a low-pass filter process according to the multiplied clock signal CLKna. Output to the digital / analog conversion circuit 403.

In the overdrive system in which the input and output sides are driven by the same multiplied clock signal, the digital low-pass filters LPF2 and LPF3 perform multi-processing, but the coefficients are fixed coefficients because they are low-pass filtering of integer multiples. It is simpler than the processing of a coefficient time-varying equation in general multi-rate processing.

As described above, according to the present embodiment, the analog low-pass filter 10 attenuates the band component of the input analog signal S _IN equal to or higher than the Nyquist frequency, inputs the signal to the n-times ADC 20, and outputs the multiplied clock signal CL.
The signal is converted into a digital signal by a digital / analog conversion circuit 202 according to Kna, and a high-frequency noise is attenuated by a digital low-pass filter having a steep cutoff characteristic. The result of the signal processing by the digital signal processing circuit 30 is input to the n × speed DAC 40 and the digital low-pass filter 40
2, the harmonic component is attenuated by the digital / analog conversion circuit 403, and the analog component is attenuated by the analog low-pass filter 50 and output as the processing result S _OUT. It can be configured with a simple type filter having gain characteristics, can be realized with a small and inexpensive circuit, and a digital filter can realize a low-pass filter with equivalently high performance characteristics, miniaturization of the entire signal processing circuit, low cost Can be realized.

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the signal processing circuit according to the present invention. As shown, in the signal processing circuit of the present embodiment, the analog low-pass filter 1 on the input side is used.
The 0 and n-times speed DAC 20 is the same as that of the first embodiment of the present invention described above, and the digital signal processing circuit 30
The a, m double speed DAC 40a is different from that of the first embodiment. In this embodiment, the input side and the output side are driven by different clock signals CLKa and CLKd,
For this reason, in the present embodiment, multi-rate processing is performed on a digital signal obtained by sampling on the input side, and the frequency of the signal is changed to the operation clock signal CLK on the output side.
It is necessary to match d. In this embodiment, the multi-rate processing is performed by the digital signal processing circuit 30a. Hereinafter, the present embodiment will be described focusing on the digital signal processing circuit 30a and the m-speed DAC 40a.

The digital signal processing circuit 30a according to the present embodiment performs multi-rate processing as described above and performs frequency conversion of digital signals, in addition to performing normal digital signal processing. As shown, the digital signal processing circuit 30a receives both the clock signal CLKa on the input side and the clock signal CLKd on the output side and performs multi-rate processing according to these clock signals.

On the input side of this embodiment, a digital signal is obtained by sampling at the sampling frequency fa and input to the digital signal processing circuit 30a. The digital signal processing circuit 30a performs multi-rate processing in addition to normal signal processing on the input digital signal, and converts the frequency of the digital signal into a drive frequency fd on the output side, and supplies it to the output side. Is done.

FIG. 4 shows the concept of multi-rate processing. In FIG. 4, the left side shows the frequency spectrum of the signal, and the right side shows the waveform of the signal. Here, the input analog signal is sampled at a sampling frequency of fa = 18 MHz, for example, and the sampling frequency fd = 13.5 MHz by multi-rate processing.
Is converted into a digital signal. A common clock frequency of 5 is used as the least common multiple of the sampling frequency on the input / output side.
4 MHz can be calculated. Then, the input side clock signal CLKa is tripled in speed and the output side clock signal CLKd is set to 4 times.
A double clock speed achieves a common clock frequency.

As shown in FIG. 4A, an analog signal is sampled at a sampling frequency fa. Then, as shown in FIG. 4B, triple sampling points are obtained by zero insertion between the data obtained by sampling, and the result is equivalently sampling an analog signal at a triple sampling frequency. Then, harmonic noise components generated by zero insertion or the like are attenuated by the digital low-pass filter, and the signal waveform shown in FIG. 4C is obtained. This is equivalent to a signal sampled at 54 MHz. On the other hand, as a result of reducing the number of sampling points to 1/4 by thinning out by 1/4, equivalently, the sampling frequency f
A data sequence sampled at d = 13.5 MHz is obtained. By such multi-rate processing, the sampling frequency of digital signals can be equivalently converted by digital signal processing means such as zero insertion and a digital low-pass filter in the digital signal processing area. Useful when driven.

As shown in FIG. 3, the m-speed DAC 40a on the output side in this embodiment comprises a clock m-speed PLL circuit 401, a digital low-pass filter 402, and a digital / analog conversion circuit 403. The clock m-times PLL circuit 401 uses the input clock signal CLKd as a reference clock signal and multiplies the frequency of the clock signal CLKd by m to generate a multiplied clock signal CLKmd. m-multiplied clock signal CLKmd
Are supplied to a digital low-pass filter 402 and a digital / analog conversion circuit 403, respectively. The digital low-pass filter 402 performs a frequency conversion process on the processing result from the digital signal processing circuit 30 a using zero-inserted data, performs a low-pass filter process according to the multiplied clock signal CLKmd, and outputs the result to the digital / analog conversion circuit 403. . As shown in FIG. 5C, the digital low-pass filter 402 has a flat pass characteristic in a band of 0 to fd / 2, and the gain sharply decreases in a band of fd / 2 or more. I do. That is, the low-pass filter 402 has a flat pass characteristic in a pass band and a steep cutoff characteristic.

FIGS. 5A and 5B show the input-side analog low-pass filter 10 in this embodiment.
5D shows the characteristics of the gain of the digital low-pass filter 203 of the n-times DAC 20, and FIG. 5D shows the gain characteristics of the analog low-pass filter 50 on the output side.

In this embodiment, for example, the frequency fa of the input side clock signal CLKa is 18.0 MHz, whereas the frequency fd of the output side clock signal CLKd is 1
3.5 MHz. On the input side, the input analog signal S _IN
A band component equal to or higher than the Nyquist frequency (fa / 2) is attenuated through the analog low-pass filter 10,
Input to DC20. In the n-times speed ADC 20, sampling is performed according to the multiplied clock signal CLKna, and an analog signal is converted into a digital signal. Then, the harmonic component is attenuated by the digital low-pass filter 203 having a steep cutoff characteristic, and only the band component equal to or lower than the Nyquist frequency is left and output to the signal processing circuit 30a.

Desired digital signal processing is performed by the signal processing circuit 30a, multi-rate processing is performed according to the frequency of the clock signals CLKa and CLKd on the input side and output side, and sampling is performed on the input side. The sampling frequency of the data series is adjusted to the sampling frequency on the output side. The output signal of the digital signal processing circuit is input to the m-times DAC 40a, and the high-frequency noise is attenuated by the digital low-pass filter 402.
The digital / analog conversion circuit 403 converts the signal into an analog signal. Furthermore, an analog low-pass filter 5
By 0, harmonic components are attenuated, and a signal S _OUT is output as a processing result.

As described above, according to the present embodiment, the input and output sides are driven by different clock signals, the input signal S _IN is input to the n-times ADC 20 through the analog low-pass filter 10, and the multiplied clock signal is input. CL
Sampling is performed according to Kna, harmonic components are attenuated by the digital low-pass filter 203, the frequency is converted by thinning-out processing, and output to the digital signal processing circuit 30a. Desired digital signal processing is performed by the digital signal processing circuit 30a, and further multi-rate processing is performed according to the input / output clock signal.
a, and frequency-converted by the digital low-pass filter 402, attenuates harmonic components in accordance with the multiplied clock signal CLKmd, is converted into an analog signal by the digital / analog conversion circuit 403, and is converted by the analog low-pass filter 50. Wave components are attenuated and output.

In the above-described embodiment, the input clock signal CLKa and the output clock signal CLKd are synchronized (for example, from a common clock signal having a frequency of 54 MHz to a clock signal CLKa of 18 MHz and 13.5 MHz for the input / output side). CLKd is created). If the clock signal on the input / output side is asynchronous, it is necessary to control the timing by inserting a FIFO circuit in an appropriate path. As described above, when the frequencies of the input / output clock signals are different, but these clock signals are synchronized, an appropriate multi-rate process is performed by the digital signal processing circuit so that the analog / digital conversion circuit and the digital / analog conversion circuit can be used. Then, a similar operation is performed.

Third Embodiment FIGS. 6 and 7 are circuit diagrams showing a third embodiment of the signal processing circuit according to the present invention. In the present embodiment, the coefficients of the digital low-pass filters on the input and output sides are time-varying coefficients, and accordingly, multi-rate processing is performed by the n-speed ADC on the input side or the m-speed DAC on the output side.

The frequency conversion of a digital signal is performed, for example, by
In the video signal processing, a signal from a CCD having a high horizontal resolution (clock signal frequency fa = 18 MHz) is converted to 13.5.
This is necessary when converting to a signal of MHz. The principle of the frequency conversion is explained with reference to FIG. For example, to convert a digital signal sampled by a clock signal having a frequency fa into an output frequency fd, first, FIG.
As shown in (b), the frequency is increased to the least common multiple by the zero insertion method, and as shown in FIG. 4 (c), the harmonic component is attenuated by a low-pass filter to leave only the signal component.
Next, as shown in FIG. 4D, frequency conversion can be realized by performing thinning sampling.

In this case, the calculation of the zero insertion data is actually omitted, and the low-pass filter operation is calculated as a coefficient time-varying equation at the output rate. That is, given the input sampling frequencies fa and fd, the least common multiple fo = LCM
If (fa, fd), the frequency fo is the required oversampling frequency. Here, the oversampling ratio is (Ko = fo / fa), the thinning ratio is (Ks = fd / fo), and the oversampling conversion ratio is (K = Ko / Ks = fd / fa). At the time of oversampling, since the calculation of the zero insertion point is unnecessary, the coefficient of the low-pass filter at that point can be omitted, and the clock signal of the low-pass filter is converted to the output side clock signal CLK
When processing is performed in synchronization with d, the conversion value can be output by repeating the coefficient switching calculation with the oversampling magnification Ko. This is a low-pass filter in which so-called Ko switching of coefficients is performed.

In the example of FIG. 4, the sampling frequency is 1
This is a so-called down-rate conversion, which converts from 8 MHz to 13.5 MHz. The basic principle is the same in the case of up-rate conversion. However, in circuit structure, up-rate conversion and down-rate conversion are slightly different. In the conversion, since the output of the low-pass filter is obtained by the clock signal having the higher frequency, the timing control is controlled so that the input data is read or held twice at a certain timing, which is suitable for such control. A circuit with a structure is chosen. On the other hand, in the case of down-rate conversion, the input signal is skipped and subjected to low-pass filtering, and the timing control structure and circuit are different from those of up-rate conversion. Since these are coefficient time-varying processes, they are complicated and have a somewhat large gate scale. Conventionally, it is customary to raise a gate array of a dedicated conversion circuit and incorporate it into a circuit. These circuits can be easily incorporated into an ADC or a DAC and mounted on a chip, thereby suppressing variations in the circuits and realizing a very small, inexpensive, and high-performance signal processing circuit.

FIG. 6 shows an example of a signal processing circuit for performing frequency conversion by the m-speed DAC 40a on the output side. In the signal processing circuit of the present example, the input-side analog low-pass filter 10, n-times speed DAC 20, and digital signal processing circuit 30 are the same as those of the first embodiment shown in FIG. The output side m-times speed DAC 40a is different from that of the first embodiment.

As shown in FIG. 6, the m.times.
Reference numeral 0a denotes an m-speed PLL circuit 401, a digital low-pass filter 402a, and a digital / analog conversion circuit 403. The clock m-speed PLL circuit 401 multiplies the input clock signal CLKd by m to generate a multiplied clock signal CLKmd, and supplies the multiplied clock signal CLKmd to the digital low-pass filter 402 and the digital / analog conversion circuit 403, respectively. The digital low-pass filter 402a receives the clock signal C on the input side.
LKa and the multiplied clock signal CLKmd are received, and the frequency conversion is performed on the digital signal from the digital signal processing circuit 30 in accordance with these clock signals. Here, the sampling frequency of the digital signal from the digital signal processing circuit 30 is fa = 18 MHz, for example, like the input side clock signal CLKa. Frequency fd = 1 of clock signal CLKd on the output side
The frequency is 3.5 MHz, and this clock signal CLKd is multiplied by 4 to obtain a 54 MHz multiplied clock signal CLK.
Assume that md is generated.

The multi-rate processing is performed by the digital low-pass filter 402a. The digital signal from the digital signal processing circuit 30 is a multiplied clock signal CLK.
The rate is converted according to the frequency of md. The digital low-pass filter 402a attenuates harmonic noise components in the input signal, and further converts the rate. Then, the converted signal is output to the digital / analog conversion circuit 403 and converted into an analog signal. The analog signal output from the digital / analog conversion circuit 403 is output after the high-frequency noise component is attenuated by the analog low-pass filter 50.

FIG. 7 shows an example of a signal processing circuit in which multi-rate processing is performed by the input side n-times speed DAC 20a. In the example of FIG. 7, in the n-times speed DAC 20a,
The digital low-pass filter 203a receives the multiplied clock signal CLKna from the clock n-times PLL circuit 201 and the clock signal CLKd on the output side, and reduces the high-frequency noise component and reduces the frequency of the digital signal from the analog / digital conversion circuit 202. Conversion is performed. For example, if a digital signal having a sampling frequency of 18 MHz is input from the analog / digital conversion circuit 202, the digital low-pass filter 203
a indicates that the high frequency noise of the input signal is reduced and the clock signal CLKd is changed in accordance with the clock signal CLKd on the output side.
, For example, fd = 13.5 MHz.

The signal output from the n × speed ADC 20 a is subjected to desired processing by the digital signal processing circuit 30, and further, the analog signal S is output by the output side m × speed DAC 40 a and analog low pass filter 50.
Converted to _OUT and output.

In the above two examples of the present embodiment, the digital signal processing circuit 30 of FIG. 6 operates according to the clock signal CLKa on the input side, but the digital signal processing circuit 30 of FIG. Output side clock signal C
It differs by operating according to LKd.

Fourth Embodiment FIGS. 8 to 10 show circuit examples of an n-times ADC 20a, an m-times DAC 40a, and a clock n (m) -times PLL circuit which can be applied to the above-described embodiments of the present invention. The n-speed ADC 20a shown in FIG.
Circuit 201, analog / digital conversion circuit 202, digital low-pass filter 203a, and switch SW
1. Clock n-times PLL circuit 2
A frequency multiplier 01 multiplies the frequency of the input clock signal CLKa by a predetermined multiplication factor n to generate a multiplied clock signal CLKna, which is supplied to the analog / digital conversion circuit 202 and the digital low-pass filter 203a.
The analog / digital conversion circuit 202 converts the input analog signal into a digital signal according to the multiplied clock signal CLKna, and outputs the digital signal to the digital low-pass filter 203a. The digital low-pass filter 203a performs multi-rate processing according to an external setting input. Further, the clock signal input to the digital low-pass filter 203a by the switch SW1 changes the clock signal CLKa on the input side or the clock signal CLKb on the output side.
Can be selected. Digital low-pass filter 2
03a, the harmonic noise component of the digital signal from the analog / digital conversion circuit 202 is attenuated, and further designated by an external setting input according to the input multiplied clock signal CLKna and the clock signal selected from the switch SW1. Multi-rate processing is performed based on the coefficient and the conversion rate ratio, and a frequency-converted digital signal is output.

FIG. 9 shows an m-times speed DAC 4 provided on the output side.
0a is shown. As shown in the figure, the m-speed DAC of the present embodiment includes a clock m-speed PLL circuit 401, a switch SW2, a digital low-pass filter 402a, and a digital / analog conversion circuit 403. The clock m-times PLL circuit 401 converts the frequency of the input clock signal CLKd to a multiplication ratio m set from the outside.
To generate a multiplied clock signal CLKmd, which are supplied to the digital low-pass filter 402a and the digital / analog conversion circuit 403, respectively.

The switch SW2 selects either the clock signal CLKe or CLKd input from the outside and inputs it to the digital low-pass filter 402a. The digital low-pass filter 402a attenuates the high-frequency noise component of the input digital signal, performs multi-rate processing, converts the rate of the digital signal, and outputs the converted signal to the digital / analog conversion circuit 403. Note that the frequency conversion processing in the digital low-pass filter 402a is performed based on a coefficient and a conversion rate ratio set from the outside, and further according to the clock signal input from the switch SW2 and the multiplied clock signal CLKmd. The output signal of the digital low-pass filter 402a is converted into an analog signal by the digital / analog conversion circuit 403 and output.

FIG. 10 shows that the input clock signal CLK is
(M) shows the configuration of a clock double-speed PLL circuit that generates a multiplied clock signal CLK by multiplying. As shown in the figure, the clock double-speed PLL circuit of the present example is provided with a phase comparator 20.
5, low-pass filter 206, voltage-controlled oscillator (VC
O) 207 and a counter 208.

The phase comparator 205 has an external clock signal CLK as a reference clock signal and a counter 208.
Is output. The phase comparator 205 compares the phases of the input signals, and outputs a signal corresponding to the comparison result. The low-pass filter 206 attenuates the harmonic component of the output signal of the phase comparator 205 and outputs it to the voltage-controlled oscillator 207 as a control signal. The voltage control oscillator 207 controls the oscillation frequency of the oscillation signal according to the input signal, and outputs the oscillation signal to the counter 208. Then, the counter 208 performs a counting operation in accordance with an external setting input, and inputs the counting result to the phase comparator 205. Note that a clock double-speed PLL circuit that multiplies a clock at a predetermined multiplication rate includes an analog type and a digital type. In the present invention, which one to use is not particularly limited, and it goes without saying that the present invention can be applied to either an analog or digital PLL circuit.

The clock double-speed PLL configured as described above
The circuit operates as a multiplier and multiplies the frequency of the input clock signal CLK according to an externally set value to generate a multiplied clock signal CLKn (m).

The configuration examples of the n-speed ADC and the m-speed DAC applicable to the signal processing circuit of the present invention and the clock double-speed PLL circuit used in these circuits have been described above. Not limiting,
Needless to say, the present invention can be realized by a circuit having a similar function.

[0060]

As described above, according to the signal processing circuit of the present invention, there are advantages that a high-performance filter characteristic can be realized and variation in the circuit can be suppressed. Further, according to the present invention, downsizing and cost reduction can be realized by the conventional signal processing circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a signal processing circuit according to the present invention.

FIG. 2 is a graph showing gain characteristics of each filter according to the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the signal processing circuit according to the present invention.

FIG. 4 is a diagram illustrating the concept of multi-rate processing.

FIG. 5 is a graph showing a gain characteristic of each filter according to the second embodiment.

FIG. 6 is a circuit example showing a third embodiment of a signal processing circuit according to the present invention, and is a circuit diagram of a signal processing circuit that performs multi-rate processing on an output side.

FIG. 7 is a circuit example showing a third embodiment of a signal processing circuit according to the present invention, and is a circuit diagram of a signal processing circuit that performs multi-rate processing on an input side.

FIG. 8 is a circuit diagram showing a configuration of an n-speed ADC applicable to the present invention.

FIG. 9 is a circuit diagram showing a configuration of an m-speed DAC applicable to the present invention.

FIG. 10 is a circuit diagram showing a configuration of a clock double-speed PLL circuit.

FIG. 11 is a circuit diagram showing a configuration of a conventional signal processing circuit.

FIG. 12 is a graph showing gain characteristics of a filter of a conventional signal processing circuit.

[Explanation of symbols]

10, 50 ... analog low-pass filter, 20, 20a
... n-speed ADC, 40, 40a ... m-speed DAC, 30,
30a: Digital signal processing circuit, 201, 401: Clock double-speed PLL circuit, 202: Analog / digital conversion circuit, 203, 203a: Digital low-pass filter, 402, 402a: Digital low-pass filter, 403: Digital / analog conversion circuit.

Claims (14)

[Claims] 1. A signal processing circuit for converting an input analog signal into a digital signal and processing the same, comprising: a multiplying circuit for multiplying an external clock signal at a predetermined multiplying ratio and supplying a multiplied clock signal; And an analog / digital conversion circuit for converting the input analog signal into a digital signal in accordance with the external clock signal, and attenuating harmonic components of the digital signal output from the analog / digital conversion circuit in accordance with the external clock signal. A signal processing circuit having a digital filter that outputs the result. 2. The signal processing circuit according to claim 1, wherein the digital filter converts a frequency of the digital signal having the harmonic component attenuated by performing a thinning process in accordance with the external clock signal. 3. A signal processing circuit for converting an input analog signal into a digital signal, processing the converted signal, converting the processed result into an analog signal, and outputting the converted signal. A multiplying circuit that supplies a signal; a digital filter that performs frequency conversion processing on the processing result, attenuates and outputs harmonic components in the signal after the frequency conversion processing according to the multiplied clock signal, And a digital / analog conversion circuit for converting an output signal of the digital filter into an analog signal. 4. The signal processing circuit according to claim 3, wherein the digital filter converts the frequency by performing an interpolation process on the processing result. 5. The signal processing circuit according to claim 3, wherein said digital filter converts a frequency by performing zero insertion on said processing result. 6. A signal processing circuit for converting an input analog signal into a digital signal, processing the converted signal, converting the processed result into an analog signal, and outputting the converted signal. A multiplying circuit for supplying a signal; an analog / digital converting circuit for converting the input analog signal into a digital signal based on the multiplied clock signal; and an attenuating harmonic component of the digital signal output from the analog / digital converting circuit. A first digital filter that performs frequency conversion processing in accordance with the external clock signal and outputs the result, and performs predetermined processing on an output signal of the first digital filter in accordance with the external clock signal A digital processing circuit, and the digital clock according to the external clock signal and the multiplied clock signal. A second digital filter that performs frequency conversion processing on the processing result of the digital processing circuit, attenuates and outputs harmonic components in the signal after the frequency conversion processing according to the multiplied clock signal, And a digital / analog conversion circuit for converting an output signal of the digital filter into an analog signal. 7. A first analog filter for attenuating a harmonic component of the analog signal and inputting the signal to the analog / digital conversion circuit, wherein the first analog filter is compared with the first digital filter. 7. The signal processing circuit according to claim 6, wherein the signal processing circuit has a gentle cutoff characteristic. 8. A second analog filter for attenuating a harmonic component of an analog signal output from the digital / analog conversion circuit, wherein the second analog filter is compared with the second digital filter. 7. The signal processing circuit according to claim 6, which has a gentle cutoff characteristic. 9. The signal processing circuit according to claim 6, wherein said multiplying circuit comprises a PLL circuit using said input clock signal as a reference signal. 10. A signal processing circuit for converting an input analog signal into a digital signal, processing the converted signal, converting the processed result into an analog signal, and outputting the analog signal, wherein the first input clock signal is multiplied by a first multiplication ratio. And the first
A first multiplying circuit for supplying a multiplied clock signal of a second input clock signal; and a second multiplying circuit for multiplying the second input clock signal by a second multiplying ratio.
A second multiplying circuit for supplying a multiplied clock signal, an analog / digital converting circuit for converting the input analog signal into a digital signal based on the first multiplied clock signal, and an output from the analog / digital converting circuit. A first digital filter for attenuating a harmonic component of the digital signal, converting a frequency in accordance with the first input clock signal, and outputting the converted signal; And a digital processing circuit for performing frequency conversion based on the frequencies of the first and second clock signals; and performing a frequency conversion on a processing result of the digital processing circuit in accordance with the second multiplied clock signal. And a second digital filter for attenuating harmonic components; Signal processing circuit and a digital / analog converter circuit for converting the force signal to an analog signal. 11. A first attenuator for attenuating harmonic components of said analog signal and inputting said signal to said analog / digital conversion circuit.
11. The signal processing circuit according to claim 10, further comprising an analog filter, wherein the first analog filter has a more moderate cutoff characteristic than the first digital filter. 12. A second attenuating harmonic component of an analog signal output from said digital / analog conversion circuit.
11. The signal processing circuit according to claim 10, further comprising an analog filter, wherein the second analog filter has a gentler cutoff characteristic than the second digital filter. 13. A signal processing circuit for converting an input analog signal into a digital signal for processing, converting the processing result into an analog signal and outputting the analog signal, wherein the first input clock signal is multiplied by a first multiplication ratio. And the first
A first multiplying circuit for supplying a multiplied clock signal of a second input clock signal; and a second multiplying circuit for multiplying the second input clock signal by a second multiplying ratio.
A second multiplying circuit for supplying a multiplied clock signal, an analog / digital converting circuit for converting the input analog signal into a digital signal based on the first multiplied clock signal, and an output from the analog / digital converting circuit. A first digital filter that attenuates a harmonic component of the digital signal, performs a frequency conversion process in accordance with the first multiplied clock signal and the second input clock signal, and outputs the result. A digital processing circuit for performing predetermined processing on the output signal of the filter in accordance with the second input clock signal; and frequency conversion of the processing result of the digital processing circuit in accordance with the second multiplied clock signal A second digital filter for performing a process to attenuate harmonic components; Signal processing circuit and a digital / analog converter circuit for converting an output signal of the data into an analog signal. 14. A signal processing circuit for converting an input analog signal into a digital signal for processing, converting the processing result into an analog signal, and outputting the converted signal, wherein the first input clock signal is multiplied by a first multiplication ratio. And the first
A first multiplying circuit for supplying a multiplied clock signal of a second input clock signal; and a second multiplying circuit for multiplying the second input clock signal by a second multiplying ratio.
A second multiplying circuit for supplying a multiplied clock signal, an analog / digital converting circuit for converting the input analog signal into a digital signal based on the first multiplied clock signal, and an output from the analog / digital converting circuit. A first digital filter that attenuates a harmonic component of the digital signal and performs a frequency conversion process in accordance with the first input clock signal; A digital processing circuit that performs a predetermined process according to an input clock signal; and performs a frequency conversion process on a processing result of the digital processing circuit according to the first input clock signal and the second multiplied clock signal. A second digital filter for attenuating harmonic components, and an output of the second digital filter. Signal processing circuit and a digital / analog converter circuit for converting an analog signal to issue.